SOURCE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY APPARATUS INCLUDING THE SAME

Abstract

A source driving circuit includes a source driver circuit, an intermediate voltage generator, and a switching control unit. The source driver circuit receives display data and generates a source driving voltage corresponding to the received display data. The intermediate voltage generator generates an intermediate source driving voltage. The switching control unit receives a plurality of control signals for selectively applying the source driving voltage and the intermediate source driving voltage to data lines of a display as a driving voltage and controls an order of transition to final levels of a common electrode voltage and the driving voltage. The common electrode voltage may be applied to a common electrode of a liquid crystal capacitor coupled to the data line of the display.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the accompanying drawings.

FIG. 1 is a diagram illustrating a conventional display system.

FIG. 2 is a schematic diagram illustrating a conventional source driving circuit used in the system of FIG. 1.

FIG. 3 is a diagram illustrating a conventional common voltage driver circuit.

FIG. 4 is a timing diagram illustrating a source driving voltage driven by the source driving circuit of FIG. 2 and a common electrode voltage driven by the common voltage driver circuit of FIG. 3.

FIG. 5 is a diagram illustrating a source driving circuit according to an exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a common voltage driver circuit that drives the common electrode voltage according to an exemplary embodiment of the present invention.

FIG. 7 is a schematic diagram illustrating a source driving circuit without the switching control unit in the source driving circuit of FIG. 5 for explaining the effect of reduction of the current consumption according to an exemplary embodiment of the present invention.

FIG. 8 is a timing diagram illustrating output signals of the source driving circuit of FIG. 7 and the common voltage driver circuit of FIG. 6 according to the control signals.

FIG. 9 is a timing diagram illustrating transitions of the output voltages of the source driving circuit of FIG. 5 and the common voltage driver circuit of FIG. 6.

FIG. 10 is a timing diagram illustrating transitions of the output voltages of the source driving circuit of FIG. 5 and the common voltage driver circuit of FIG. 6 in case of the best case pattern.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention now will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout this application.

FIG. 5 is a diagram illustrating a source driving circuit according to an exemplary embodiment of the present invention. The source driving circuit may be employed in the system of FIG. 1.

Referring to FIG. 5, a source driving circuit 500 includes a source driver circuit 510 that generates a source driving voltage for driving a corresponding data line Dm, a switching control unit 530, a grayscale voltage generator 540, and an intermediate voltage generator 560. The source driving circuit 500 may be implemented in the source driver IC 120 of FIG. 1. The source driver circuit 510 may be assigned for each data line Dm, and the grayscale voltage generator 540 and the intermediate voltage generator 560 are commonly utilized by all source drivers.

The source driver circuit 510 and the grayscale voltage generator 540 operate in a similar manner as the source driver circuit 120i and the grayscale voltage generator 230 of FIG. 2 described hereinabove.

The intermediate voltage generator 560 includes a voltage regulator 562, and may further include a capacitor 564. The voltage regulator 562 provides a regulated output voltage R_VGc irrespective of a change of an input voltage VGc. The input voltage VGC may correspond to one of the reference grayscale voltages, or may it correspond to a central reference grayscale voltage. The voltage level of the regulated output voltage R_VGc may be the same as the voltage level of the input voltage VGc. The capacitor 564 may be selectively connected to an output terminal of the voltage regulator 562 for stabilizing the regulated output voltage R_VGc.

The switching control unit 530 includes a panel type selector 531, a first switching signal controller 533, a second switching signal controller 535, a first switch 537, and a second switch 539.

The panel type selector 531 outputs a panel select signal based on a most significant bit (MSB) of the display data Dm and a panel type signal NW_SEL. The MSB of the display data Dm directs that the display data Dm is close to a worst case pattern or a best case pattern. According to exemplary embodiments of the present invention, the display data Dm may correspond to the worst case pattern when the MSB corresponds to “0”, whereas the display data Dm may correspond to the best case pattern when the MSB corresponds to “1”. According to exemplary embodiments of the present invention, the panel type signal NW_SEL may correspond to logic “1” when the panel type corresponds to a normal black panel, whereas the panel type signal NW_SEL may correspond to logic “0” when the panel type corresponds to a normal white panel. The opposite situation may be possible according to other exemplary embodiments. The panel type selector 531 may be implemented with an exclusive OR gate. In summary, the panel type selector 531 outputs logic “1” when the MSB of the display data and the panel type signal NW_SEL are different from each other.

The first switching signal controller 533 receives a first control signal E_CR_ON and a second control signal L_CR_ON, and selectively outputs one of the first control signal E_CR_ON and the second control signal L_CR_ON in response to an output signal (panel select signal) of the panel type selector 531. The first switching signal controller 533 may be implemented with a 2-to-1 multiplexer. The first control signal E_CR_ON corresponds to a switching control signal between the regulated output voltage R_VGc of the intermediate voltage generator 560 and the source output Sout so that the source output Sout may transit to the final level prior to VCOM. The second control signal L_CR_ON corresponds to a switching control signal between the regulated output voltage R_VGc of the intermediate voltage generator 560 and the source output Sout so that the source output Sout and VOM may transit to respective final levels simultaneously. That is, when the first control signal E_CR_ON is selected as an output signal I_CR_ON of the first switching signal controller 533, the source output Sout transits to final level prior to VCOM whereas the source output Sout and VCOM transit to respective final levels when the second control signal L_CR_ON is selected as the output signal I_CR_ON of the first switching signal controller 533.

The second switching signal controller 535 receives a third control signal E_GRAY_ON and a fourth control signal L_GRAY_ON, and selectively outputs one of the third control signal E_GRAY_ON and the fourth control signal L_GRAY_ON in response to the panel select signal. The second switching signal controller 535 may be implemented with a 2-to-1 multiplexer. The third control signal E_GRAY_ON corresponds to a switching control signal between the output of the buffer 517 and the source output Sout so that the source output Sout may transit to the final level prior to VCOM. The fourth control signal L_GRAY_ON corresponds to a switching control signal between the output of the buffer 517 and the source output Sout, so that the source output Sout and VCOM may transit to respective final levels simultaneously. That is, when the third control signal E_GRAY_ON is selected as an output signal I_GRAY_ON of the second switching signal controller 535, the source output voltage Sout transits to the final level prior to VCOM, whereas the source output voltage Sout and VCOM transit to respective final levels when the second control signal L_GRAY_OM is selected as the output signal I_CR_ON of the second switching signal controller 535.

The first switch 537 selectively connects the regulated output voltage R_VGc as the source output voltage Sout. The second switch 539 selectively connects the output of the buffer 517 as the source output Sout.

The arrangement of the liquid crystal material in the liquid crystal capacitor Ceq varies according to a voltage difference between the source output Sout and the VCOM voltage, thereby operating the display panel.

FIG. 6 is a circuit diagram illustrating a common voltage driver circuit that drives the common electrode VCOM voltage according to an exemplary embodiment of the present invention. The common voltage driver circuit 600 may be employed in the system of FIG. 1.

Referring to FIG. 6, the common voltage driver circuit 600 includes first and second drivers 610 and 620, switches 630 and 640, capacitors 670 and 680, and an intermediate voltage output circuit 650.

The intermediate voltage output circuit 650 includes a third driver 651 that buffers and outputs a reference voltage VDD fed thereto, and switches 653 and 655 that are controlled by intermediate voltage control signals VCIR and VSSR respectively. The switch 653 is controlled to connect the output of the third driver 651 to the VCOM node N, and the switch 655 is controlled to connect the VCOM node N to a ground voltage VSS.

FIG. 7 is a diagram illustrating a source driving circuit without the switching control unit used in the source driving circuit of FIG. 5 for explaining the effect of a reduction of the current consumption, according to an exemplary embodiment of the present invention. FIG. 8 is a timing diagram illustrating output signals of the source driving circuit of FIG. 7 and the common voltage driver circuit of FIG. 6 according to control signals. FIG. 8 will be explained with reference to FIGS. 6 and 7. The worst case pattern of the display data is assumed in FIG. 8. The output of the common voltage driver circuit of FIG. 6 will be explained first and the source output Sout of the source driving circuit of FIG. 7 will be explained later. The control signal GRAY_ON is a switching control signal that controls switch 539 between the output of the buffer 517 and the source output Sout. In addition, control signal CR_ON is a switching control signal that controls switch 537 between the output of the intermediate voltage generator 560 and the source output Sout.

At this time, control signal CR_ON is disabled, and control signal GRAY_ON is enabled. In addition, the source output Sout is driven to VH, because the worst case pattern is assumed.

Referring to FIG. 8, in the time period before time T1, with polarity control signal M at logic “0”, the control signal VCML_ON is enabled (the switch 640 is closed), and control signals VCMH_ON, VCIR and VSSR are disabled. Accordingly, the common electrode VCOM is driven to VCOML by the second driver 620. The control signal CR_ON is in the disabled state, and the control signal is in the enabled state. In addition, the source output Sout is driven to VH, because the worst case pattern of the display data is assumed.

At time T1, the polarity signal M switches to logic “1” to invert the display data, the control signal VCML_ON is disabled to cause the switch 640 to be opened, and control signal VSSR is enabled to cause to the switch 655 to be closed, thereby connecting the VCOM node N to an intermediate voltage VSS (for example, ground). During time period P1, VCOM is driven to VSS from VCOML. At time T1, control signal CR_ON is enabled, and control signal GRAY_ON is disabled. Accordingly, the switch 537 is closed, and the switch 539 is opened. Dining time period P1, the source output Sout is driven to VGc.

At time T2, the control signal VSSR is disabled to cause the switch 655 to be opened, the control signal VCIR is enabled to cause the switch 653 to be closed, thereby connecting the VCOM node N to the output of the third driver 651. Accordingly, during time period P2, VCOM is driven to an intermediate voltage (VDD) from VSS by using VDD power supply. During time period P2, the source output Sout is maintained at VGc, because control signals CR_ON and GRAY_ON are in the same state as in time period P1.

At time T3, the control signal VCIR is disabled to cause the switch 653 to be opened, and the control signal VCMH_ON is enabled to cause the switch 630 to be closed, thereby connecting the output of the first driver 610 to the VCOM node N. Therefore, during time period P3, VCOM is driven to VCOMH from the intermediate voltage (VDD) by the first driver 610. At time T3, the control signal CR_ON is disabled to cause the switch 537 to be opened, and the control signal GRA_ON is enabled to cause the switch 539 to be closed, thereby driving the source output Sout to VL from VGc.

At time T4, the polarity control signal M switches to logic “0” that indicates display data having a “positive” polarity, the control signal VCMH_ON is disabled to cause the switch 640 to be opened, and the control signal VCIR is enabled to cause the switch 653 to be closed, thereby connecting the VCOM node N to the output of the third driver 651. During time interval P4, VCOM is driven to VDD from VCOMH by the third driver 651. At time T4, the control signal CR_ON is enabled to cause the switch 537 to be closed, and the control signal GRAY_ON is disabled to cause the switch 539 to be opened, thereby driving the source output Sout to VGc from VL during time period P4.

At time T5, the control signal VCIR is disabled to cause the switch 653 to be opened, and the control signal VCMH_ON is enabled to cause the switch 630 to be closed, thereby connecting the VCOM node N to VSS. During time period P5, VCOM is driven to VSS from VDD. The source output Sout is maintained at VGc, because control signals CR_ON and GRAY_ON are in the same state as they were during the time period P4.

At time T6, the control signal VSSR is disabled to cause the switch 655 to open, and the control signal VCML_ON is enabled to cause the switch 640 to be closed, thereby connecting the VCOM node N to the output of the second driver 620. During time interval P5, VCOM is driven to VCOML from VSS. At time T6, the control signal CR_ON is disabled to cause the switch 537 to be opened, and the control signal GRAY_ON is enabled to cause the switch 539 to be closed, thereby driving the source output Sout to VH from VGc during time period P6.

In FIG. 8, the average load current consumption for VCOMH driven from AVDD is formulated by the following Equation 5.

I _VCOMH=(m(VCOMH−VDD+VGc)Ceq)/2T=(m(VCOMH−VDD+(VH−VL)/2)Ceq)/2T,   [Equation 5]

where m denotes a number of source channels, Ceq denotes a capacitance of an equivalent capacitor, and T denotes a toggling period of VCOM.

In addition, the average load current consumption for VCOML driven from VCL is formulated by the following Equation 6.

I _VCOML=(m(VGc−VCOML)Ceq)/2T=(m((VH−VL)/2−VCOML)Ceq)/2T   [Equation 6]

Further, the average load current consumption for a source driven from AVDD is formulated by the following Equation 7.

I _SRC=(m(VGc−VCOML)Ceq)/2T=(m((VH−VL)/2−VCOML)Ceq)/2T   [Equation 7]

Further, the average load current consumption for VDD is formulated by the following Equation 8.

I _VDD=(m(VGc−(VH−VL−VGc−VCOML)Ceq)2T=m*VCOML*Ceq/2T   [Equation 8]

When AVDD corresponds to an output voltage boosted by ‘a’ from an external input power supply voltage, and VCL corresponds to an output voltage boosted by ‘−b’ from the external input power supply voltage, the total average current consumption is formulated by following Equation 9.

$\begin{array}{cc}{I}_{\mathrm{TOT}}=m\left(a\left(\mathrm{VCOMH}-\mathrm{VDD}+\mathrm{VH}-\mathrm{VL}-\mathrm{VCOML}\right)+b\left(\mathrm{VH}-\mathrm{VL}\right)/2-\mathrm{VCOML}\right)+\mathrm{VCOML})\mathrm{Ceq})/2T& \left[\mathrm{Equation}9\right]\end{array}$

When Equation 9 is subtracted from Equation 4, a difference of the current consumptions may be obtained as the following Equation 10.

m((a+b)*VCOMH−(a+1)VCOML+(a+b/2)(VH−VL)+a*VDD)Ceq)/2T   [Equation 10]

The current consumption is reduced by the amount of equation 10 when the common voltage generator of FIG. 6 and the source driving circuit of FIG. 7 are employed, compared to when the sourcing driving circuit of FIG. 2 and the common voltage generator of FIG. 3 are employed. In addition, VCOML is a negative value, thus, the reduction of current consumption is relatively large.

FIG. 9 is a timing diagram illustrating transitions of the output voltages of the source driving circuit of FIG. 5 and the common voltage driver circuit of FIG. 6. FIG. 9 will be explained with reference to FIGS. 5 and 6. The worst case pattern is assumed in FIG. 9. The output signal of the common voltage driver circuit of FIG. 6 will be explained first, and the output signal of the source driving circuit of FIG. 5 will be explained later. In FIG. 9, the output signal of the panel type selector 531 is assumed to be logic “1”. That is, the MSB of the display data Dm and the panel select signal NW_SEL are different from each other in FIG. 9.

Referring to FIG. 9, in the time period before time T1, with polarity control signal M at logic “0”, the control signal VCML_ON is enabled (the switch 640 is closed), and control signals VCMH_ON, VCIR and VSSR are disabled. Accordingly, the common electrode VCOM is driven to VCOML by the second driver 620. In the time period before time T1, latch control signal S_LATCH is in the disabled state, control signals E_CR_ON and L_CR_ON are in the disabled state, and control signals E_GRAY_ON and L_GRAY_ON are in the enabled state. Accordingly, the first switching control signal I_CR_ON is in the disabled state to cause the switch 537 to be in the off state, and the second switching control signal I_GRAY_ON is in the enabled state to cause the switch to be in the on state. Therefore, the source output Sout is driven to VH, which is the highest grayscale reference voltage.

At time T1, the polarity signal M switches to logic “1” to invert the display data, the control signal VCML_ON is disabled to cause the switch 640 to be opened, and control signal VSSR is enabled to cause to the switch 655 to be closed, thereby connecting the VCOM node N to an intermediate voltage VSS (for example, ground). During the time period P1, VCOM is driven to VSS from VCOML.

While the exemplary embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the present invention. At time T1, control signals E_CR_ON aid L_CR_ON are enabled, and control signals E_GRAY_ON and L_GRAY_ON are disabled. Therefore, the first, output signal I_CR_ON is enabled to cause the switch 537 to be closed, and the second output signal I_GRAY_ON is disabled to cause the switch 539 to be opened, thereby connecting the output of the intermediate voltage generator 560 to the source output Sout. During time period P1, the source output Sout is driven to VGc from VH.

At time T2, the control signal VSSR is disabled to cause the switch 655 to be opened, the control signal VCIR is enabled to cause the switch 653 to be closed, thereby connecting the VCOM node N to the output of the third driver 651. Accordingly, during time period P2, VCOM is driven to VDD from AVSS by using the power supply VDD. During time period P2, the source output Sout is maintained at VGc, because the signals E_CR_ON, L_CR_ON, E_GRAY_ON, L_GRAY_ON, I_CR_ON and I_GRAY_ON are in the same state as during time period P1.

During time period P3, VCOM is maintained at VDD, the same state as time period P2. At time T3, the control signal E_CR_ON is disabled, and the first output signal I_CR_ON is disabled accordingly to cause the switch 537 to be opened, and the control signal E_GRAY_ON is disabled, and the second output signal I_GRAY_ON is disabled accordingly to cause the switch 539 to be closed, thereby connecting the output of the buffer 517 to the source output Sout. During time period P3, the source output Sout is driven to VL, the lowest grayscale reference voltage, from VGc. Accordingly, the source output Sout transits to the final level (VL) prior to VCOM.

At time T4, the control signal VCIR is disabled to cause the switch 653 to be opened, and the control signal VCMH_ON is enabled to cause switch 630 to be closed, and thereby connecting the output of the first driver 610 to the VCOM node N. During time interval P4, VCOM is driven to VCOMH from VDD by the first driver 610. During time period P4, the source output Sout is maintained at VL, the same state as during time period P3.

At time T5, the polarity control signal M switches to logic “0”, the control signal VCMH_ON is disabled to cause the switch 630 to be opened, and the control signal VCIR is enabled to cause the switch 653 to be closed, thereby connecting the VCOM node N to the output of the third driver 651. During time period P5, VCOM is driven to VCOMH from VDD. At time T5, control signals E_CR_ON and R_CR_ON are enabled, and control signals E_GRAY_ON and I_GRAY_ON are disabled. Accordingly, the output signal I_GRAY_ON is disabled to cause the switch 539 to be opened, and the output signal I_CR_ON is enabled to cause the switch 537 to be closed, thereby connecting the output of the intermediate voltage generator 560 to the source output Sout. Accordingly, the source output Sout is driven to VL from VGc.

At time T6, the control signal VCIR is disabled to cause the switch 653 to be opened, and the control signal VSSR is enabled to cause the switch 655 to be closed, thereby connecting the VCOM node N to an intermediate voltage (VSS). During time period P6, VCOM is driven to VSS from VDD, and the source output Sout is maintained at VGc as in time period P5. During time period P7, VCOM is maintained at VSS as during time period P6.

At time T7, the control signal E_CR_ON is disabled, and the output signal I_CR_ON is disabled to cause the switch 537 to be opened. In addition, the control signal E_CR_ON is enabled, and the output signal I_GRAY_ON is enabled to cause the switch 539 to be closed, thereby connecting the output of the buffer 517 to the source output Sout. Therefore, during time period P7, the source output is driven to VH from VGc. During time period P7, the source output transits to a final level (VH) prior to VCOM.

At time T8, the control signal VSSR is disabled to cause the switch 655 to be opened, and the control signal VCML_ON is enabled to cause the switch 640 to be closed, thereby connecting the VCOM node N to the output of the second driver 620. Therefore, during time period P8, the VCOM is driven to VCOML from VSS, and the source output Sout is maintained at VH as in time period P7.

In FIG. 9, unlike in FIG. 8, the source output Sout transits to a final level (VL) prior to VCOM during time period P3, and the source output Sout transits to a final level (VH) prior to VCOM during time period P7.

In FIG. 9, the average load current consumption for VCOMH driven from AVDD is formulated by the following Equation 11.

I _VCOMH=(m(VCOMH−VDD)Ceq)/2T,   [Equation 11]

where m denotes a number of source channels, Ceq denotes an equivalent capacitance, and T denotes a toggling period of VCOM.

In addition, the average load current consumption for VCOML driven from VCL is formulated by the following Equation 12.

I _VCOML =−m*VCOML*Ceq/2T   [Equation 12]

Further, the average load current consumption for source driven from AVDD is formulated by the following Equation 13.

I _SRC=(m((VH−VL)/2−VCOML)Ceq)/2T  [Equation 13]

Further, the average load current consumption of source driver for VDD is formulated by the following Equation 14.

I _VDD =m*VCOML*Ceq/2T   [Equation 14]

In addition, the average load current consumption of VCOM driver for VDD is formulated by the following Equation 15.

I _VDD =m(VH−VL)/2*Ceq)/2T   [Equation 15]

When AVDD corresponds to an output voltage boosted by “a” from an external input power supply voltage, and VCL corresponds to an output voltage boosted by “−b” from the external input power supply voltage, the total average current consumption is formulated by the following Equation 16.

I _TOT =m(a(VCOMH−VDD+(1−b)VCOML+(VH−VL)/2)Ceq)/2T   [Equation 16]

When Equation 16 is subtracted from Equation 9, a difference of the current consumptions may be obtained as the following Equation 17.

m(a(VH−VL−VCOML)+(b−1)(VH−VL)/2)Ceq/2T   [Equation 17]

The current consumption is reduced by the amount of Equation 10 when the common voltage generator of FIG. 6 and the source driving circuit of FIG. 5 are employed, compared to when the sourcing driving circuit of FIG. 7 and the common voltage generator of FIG. 6 are employed, in addition, VCOML is a negative value, thus reduction of current consumption is relatively large.

FIG. 10 is a timing diagram illustrating transitions of the output voltages of the source driving circuit of FIG. 5 and the common voltage driver circuit of FIG. 6 in the case of the best case pattern. The best case pattern is assumed to be present and, thus, the output of the panel type selector 531 corresponds to logic “0”.

In FIG. 10, timing diagrams are the same as in FIG. 9, except for the output signals I_CR_ON and I_GRAY_ON. Accordingly, time periods P3 and P4 will be explained.

At time T3, the output signal I_CR_ON is disabled, and the output signal I_GRAY_ON is enabled. The output signal I_CR_ON is identical to the control signal L_CR_ON, and the output signal I_GRAY_ON is identical to the control signal L_GRAY_ON. The control signal L_GRAY_ON corresponds to a switching control such that the source output Sout and VCOM may transit simultaneously to respective final levels. Therefore, VCOM and the source output Sout transit simultaneously to respective final levels (VCOMH and VH). At time T6, the output signal I_CR_ON is disabled, and the output signal I_GRAY_ON is enabled. Accordingly, VCOM and the source output Sout transit simultaneously to respective final levels (VCOML and VL) during time period P6. That is, reduction of current consumption is relatively large when VCOM and the source output Sout transit simultaneously to respective levels in the case of the best case pattern.

As described above, the source driving circuit, the method of driving the data line of the display, and the liquid crystal display apparatus including the same according to the exemplary embodiments of the present invention may significantly reduce current consumption by controlling timing of the transition to final levels of the source output and VCOM.

Having thus described exemplary embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof as hereinafter claimed.

Claims

1. A source driving circuit comprising: a source driver circuit that receives display data and generates a source driving voltage corresponding to the received display data;an intermediate voltage generator that generates an intermediate source driving voltage; anda switching control unit that receives a plurality of control signals for selectively applying the source driving voltage and the intermediate source driving voltage to data lines of a display as a driving voltage and controls an order of transition to final levels of a common electrode voltage and the driving voltage, the common electrode voltage being applied to a common electrode of a liquid crystal capacitor coupled to the data line of the display.

2. The source driving circuit of claim 1, wherein the switching control unit comprises: a panel type selector that outputs a panel select signal based on a data pattern bit of the display data and a panel type signal of the plurality of control signals;a first switching signal controller that controls a timing for applying the intermediate source driving voltage to the data lines based on the panel select signal and first and second control signals of the plurality of control signals;a second switching signal controller that controls a timing for applying the source driving voltage to the data lines based on the panel select signal and third and fourth control signals of the plurality of control signals;a first switch that selectively connects the intermediate source driving voltage to the data lines in response to an output signal of the first switching signal controller; anda second switch that selectively connects the source driving voltage to the data lines in response to an output signal front the first switching signal controller.

3. The source driving circuit of claim 2, wherein the panel type selector comprises an exclusive-OR gate.

4. The source driving circuit of claim 2, wherein the first and second control signals control a transition timing of the intermediate source driving voltage to a final level.

5. The source driving circuit of claim 4, wherein the first switching signal controller comprises a 2-to-1 multiplexer.

6. The source driving circuit of claim 4, wherein the driving voltage transits to a final level prior to the final level of the common electrode voltage when the first switching signal controller selects the first control signal.

7. The source driving circuit of claim 4, wherein the driving voltage and the common electrode voltage transit simultaneously to respective final levels when the second switching signal controller selects the second control signal.

8. The source driving circuit of claim 2, wherein the third and fourth control signals control a transition timing of the source driving voltage to the final level.

9. The source driving circuit of claim 4, wherein the second switching signal controller comprises a 2-to-1 multiplexer.

10. The source driving circuit of claim 9, wherein the driving voltage transits to the final level prior to the common voltage when the second switching signal controller selects the third control signal.

11. The source driving circuit of claim 9, wherein the common electrode voltage and the driving voltage transit simultaneously to respective final levels when the second switching signal controller selects the fourth control signal.

12. The source driving circuit of claim 1, wherein the intermediate source driving voltage corresponds to a reference grayscale voltage.

13. The source driving circuit of claim 12, wherein the intermediate source driving voltage corresponds to a central reference grayscale voltage.

14. A liquid crystal display (LCD) apparatus including: a liquid crystal display panel that includes a plurality of gate lines and a plurality of data lines;a gate driver that drives the plurality of gate lines; anda source driver that drives the plurality of data lines, the source driver comprising: a source driver circuit that receives display data and generates a source driving voltage corresponding to the received display data; anda switching control unit that receives a plurality of control signals for selectively applying the source driving voltage and the intermediate source driving voltage to the plurality of data lines as a driving voltage and controls order of transition to final levels of a common electrode voltage and the driving voltage, the common electrode voltage being applied to a common electrode terminal of a liquid crystal capacitor coupled to each of the plurality of data lines.

15. The LCD apparatus of claim 14, wherein the switching control unit comprises: a panel type selector that outputs a panel select signal based on a data pattern bit of the display data and a panel type signal of the plurality of control signals;a first switching signal controller that controls a timing for applying the intermediate source driving voltage to the data lines based on the panel select signal and first and second control signals of the plurality of control signals;a second switching signal controller that controls a timing for applying the source driving voltage to the data lines based on the panel select signal and third and fourth control signals of the plurality of control signals;a first switch that selectively connects the intermediate source driving voltage to the data lines in response to an output signal of the first switching signal controller; anda second switch that selectively connects the source driving voltage to the data lines in response to an output signal of the first switching signal controller.

16. The LCD apparatus of claim 15, wherein the first and second control signals control a transition timing of the intermediate source driving voltage to a final level.

17. The LCD apparatus of claim 15, wherein the third and fourth control signals control a transition timing of the source driving voltage to a final level.

18. The LCD apparatus of claim 14, wherein the intermediate source driving voltage corresponds to a central reference grayscale voltage.

19. The LCD apparatus of claim 14, further comprising: a common voltage driver circuit that drives the common electrode voltage.

20. The LCD apparatus of claim 19, wherein the common voltage driver circuit comprises: a first driver circuit that outputs a first common voltage;a second driver circuit that outputs a second common voltage;a first intermediate switch that selectively connects the first common voltage to a common electrode of the display panel in response to a first intermediate control signal;a second intermediate switch that selectively connects the second common voltage to the common electrode in response to a second intermediate control signal; andan intermediate voltage output circuit that outputs one or more intermediate common voltages to the common electrode in response to one or more intermediate control signals.

21. The LCD apparatus of claim 20, wherein the first common voltage corresponds to a high common voltage and the second common voltage corresponds to a low common voltage.

22. The LCD apparatus of claim 21, wherein the common voltage driver circuit drives the common electrode from the low common voltage to the high common voltage by driving the common electrode with the one or more intermediate common voltages before outputting the high common voltage.

23. The LCD apparatus of claim 21, wherein the common voltage driver circuit drives the common electrode from the high common voltage to the low common voltage by driving the common electrode with the one or more intermediate common voltages before outputting the low common voltage.

24. A method of driving data lines of a display, comprising: generating a source driving voltage corresponding to received display data;generating an intermediate source driving voltage;receiving a plurality of control signals for selectively applying the source driving voltage and the intermediate source driving as a driving voltage to a data line of the display; andcontrolling an order of a transition to final levels of a common electrode voltage, the source driving voltage and the intermediate source driving voltage, the common electrode voltage being applied to a common electrode terminal of a liquid crystal capacitor coupled to the data line of the display.

25. The method of claim 24, wherein the step of controlling an order of the transition comprises, outputting a panel select signal based on a data pattern bit of the display data and a panel type signal of the plurality of control signals;applying the intermediate source driving voltage to the data lines by a first switching based on the panel select signal and first and second control signals of the plurality of control signals; andapplying the source driving voltage to the data lines by a second switching based on the panel select signal and third and fourth control signals of the plurality of control signals.

26. The method of claim 25, wherein the panel select signal is inactivated when the data pattern bit and the panel type signal are inactivated exclusively.

27. The method of claim 25, wherein one of the first and second control signals is selected in the first switching.

28. The method of claim 27, wherein the driving voltage transits to a final level prior to the common electrode voltage when the first control signal is selected in the first switching.

29. The method of claim 27, wherein the driving voltage and the common electrode voltage transit simultaneously to respective final levels when the second control signal is selected in the first switching.

30. The method of claim 25, wherein one of the third and fourth control signals is selected in the second switching.

31. The method of claim 30, wherein the driving voltage transits to a final level prior to the common electrode voltage when the third control signal is selected in the second switching.

32. The method of claim 30, wherein the source driving voltage and the common electrode voltage transit simultaneously to respective final levels when the fourth control signal is selected in the second switching.