Patent Grant
12094388
This application is a national phase entry under 35 USC 371 of International Patent Application No. PCT/CN2021/125843 filed on Oct. 22, 2021, which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technologies, and in particular, to a source driving circuit, a source driving method, a display device and a display driving method.
With the increasing development of display technologies, consumers' requirements for performance of display devices are gradually increasing. In order to enhance product competitiveness of the display device, increasing a resolution and increasing a display frame rate of the display device become two effective manners.
However, as the resolution and the display frame rate increase, a time for supplying a voltage to data lines by a driver chip in the display device is shortened, a charging time of sub-pixels in each row is shortened, and a gray scale displayed by the sub-pixel is different from a target gray scale. As a result, a display effect of the display device is reduced.
In an aspect, a source driving circuit is provided. The source driving circuit includes a logic and control sub-circuit, a latch sub-circuit and an output sub-circuit.
The logic and control sub-circuit is coupled to a source data signal terminal, a gate start signal terminal, a mode switching signal terminal, an initial latch enable signal terminal and a source output enable signal terminal. The logic and control sub-circuit is configured to: receive a source data signal from the source data signal terminal and convert the source data signal into a data signal; and output a first latch signal, a second latch signal, a first enable signal and a second enable signal according to a gate start signal from the gate start signal terminal, a first mode switching signal from the mode switching signal terminal, an initial latch enable signal from the initial latch enable signal terminal and a source output enable signal from the source output enable signal terminal.
The latch sub-circuit is coupled to the logic and control sub-circuit, and the latch sub-circuit is configured to: receive the data signal from the logic and control sub-circuit; latch an odd-numbered row of data in the data signal in an odd-numbered frame under control of the first latch signal; and latch an even-numbered row of data in the data signal in an even-numbered frame under control of the second latch signal.
The output sub-circuit is coupled to the latch sub-circuit and the logic and control sub-circuit, and the output sub-circuit is configured to: receive the odd-numbered row of data in the odd-numbered frame, and output the odd-numbered row of data in a first set duration under control of the first enable signal, the first set duration being greater than a charging time of sub-pixels in the even-numbered row of a display device to which the source driving circuit applies, and being less than or equal to twice the charging time of the sub-pixels in the even-numbered row; and receive the even-numbered row of data in the even-numbered frame, and output the even-numbered row of data in a second set duration under control of the second enable signal, the second set duration being greater than a charging time of sub-pixels in the odd-numbered row of the display device, and being less than or equal to twice the charging time of the sub-pixels in the odd-numbered row.
In some embodiments, in the odd-numbered frame, the first set duration is twice the charging time of the sub-pixels in the even-numbered row; and/or, in the even-numbered frame, the second set duration is equal to twice the charging time of the sub-pixels in the odd-numbered row.
In some embodiments, the logic and control sub-circuit includes: a mask signal generation module, a latch signal generation module and an enable signal generation module.
The mask signal generation module is coupled to the gate start signal terminal and the mode switching signal terminal. The mask signal generation module is configured to generate a first mask signal and a second mask signal according to the gate start signal and the first mode switching signal.
The latch signal generation module is coupled to the mask signal generation module and the initial latch enable signal terminal. The latch signal generation module is configured to, generate the first latch signal according to the first mask signal and the initial latch enable signal, and generate the second latch signal according to the second mask signal and the initial latch enable signal.
The enable signal generation module is coupled to the mask signal generation module and the source output enable signal terminal. The enable signal generation module is configured to, generate the first enable signal according to the first mask signal and the source output enable signal, and generate the second enable signal according to the second mask signal and the source output enable signal.
In some embodiments, the mask signal generation module includes a distinguishing unit and a generation unit.
The distinguishing unit is coupled to a pulse signal terminal, the gate start signal terminal and the mode switching signal terminal. The distinguishing unit is configured to output a pair of row representation signals and a pair of frame representation signals according to a pulse signal from the pulse signal terminal, the gate start signal and the first mode switching signal. The pair of row representation signals represent the odd-numbered row and the even-numbered row, and the pair of frame representation signals represent the odd-numbered frame and the even-numbered frame.
The generation unit coupled to the distinguishing unit, and the generation unit is configured to generate the first mask signal and the second mask signal according to the pair of row representation signals, the pair of frame representation signals, and an inverted and delayed signal of the source output enable signal.
In some embodiments, the distinguishing unit includes a NAND gate, a first NOT gate, a first flip-flop, a first AND gate, and a second flip-flop.
For the NAND gate, a first input terminal of the NAND gate is coupled to the pulse signal terminal, and a second input terminal of the NAND gate is coupled to the gate start signal terminal.
For first NOT gate, an input terminal of the first NOT gate is coupled to an output terminal of the NAND gate.
For the first flip-flop, an enable terminal of the first flip-flop is coupled to an output terminal of the first NOT gate, a reset terminal of the first flip-flop is coupled to the mode switching signal terminal, a first output terminal and a second output terminal of the first flip-flop are coupled to the generation unit, and an input terminal of the first flip-flop is coupled to the first output terminal of the first flip-flop; the first output terminal of the flip-flop is configured to output the first frame representation signal, and the second output terminal of the first flip-flop is configured to output the second frame representation signal; the first frame representation signal and the second frame representation signal are inverted, and constitute the pair of frame representation signals.
For the first AND gate, a first input terminal of the first AND gate is coupled to the output terminal of the NAND gate, and a second input terminal of the first AND gate is coupled to the mode switching signal terminal.
For the second flip-flop, an enable terminal of the second flip-flop is coupled to the pulse signal terminal, a reset terminal of the second flip-flop is coupled to an output terminal of the first AND gate, a first output terminal and a second output terminal of the second flip-flop are coupled to the generation unit, and an input terminal of the second flip-flop is coupled to the first output terminal of the second flip-flop; the first output terminal of the second flip-flop is configured to output a first row representation signal, and the second output terminal of the second flip-flop is configured to output a second row representation signal; the first row representation signal and the second row representation signal are inverted, and constitute the pair of row representation signals.
In some embodiments, the generation unit includes a multiplier and a third flip-flop.
For the multiplier, a first input terminal and a second input terminal of the multiplier are coupled to the distinguishing unit, and are configured to receive the pair of row representation signals; and a third input terminal and a fourth input terminal of the multiplier are coupled to the distinguishing unit, and are configured to receive the pair of frame representation signals.
For the third flip-flop, an input terminal of the third flip-flop is coupled to an output of the multiplier, an enable terminal of the third flip-flop is configured to receive the inverted and delayed signal of the source output enable signal, and an output terminal of the third flip-flop is configured to output the first mask signal and the second mask signal.
In some embodiments, the latch signal generation module includes a second NOT gate and a second AND gate.
For the second NOT gate, an input terminal of the second NOT gate is coupled to the mask signal generation module.
For the second AND gate, wherein a first input terminal of the second AND gate is coupled to an output terminal of the second NOT gate, a second input terminal of the second AND gate is coupled to the initial latch enable signal terminal, and an output terminal of the second AND gate is configured to output the first latch signal in the odd-numbered frame and output the second latch signal in the even-numbered frame.
In some embodiments, the enable signal generation module includes a signal generator.
For the signal generator, an input terminal of the signal generator is coupled to the source output enable signal terminal, and an enable terminal of the signal generator is coupled to the mask signal generation module; and an output terminal of the signal generator is configured to output the first enable signal and the second enable signal.
In some embodiments, the logic and control sub-circuit is further configured to receive and output the initial latch enable signal and the source output enable signal according to the gate start signal and a second mode switching signal from the mode switching signal terminal.
The latch sub-circuit is further configured to latch the odd-numbered row of data and the even-numbered row of data in the data signal in each frame under control of the initial latch enable signal.
The output sub-circuit is further configured to output the odd-numbered row of data and the even-numbered row of data under control of the source output enable signal.
In some embodiments, the source driving circuit further includes a level conversion and digital-to-analog conversion sub-circuit.
The level conversion and digital-to-analog conversion sub-circuit is coupled to the latch sub-circuit and the output sub-circuit, and the level conversion and digital-to-analog conversion sub-circuit is configured to: receive the odd-numbered row of data in the odd-numbered frame, and perform level conversion and digital-to-analog conversion on the odd-numbered row of data; and receive the even-numbered row of data in the even-numbered frame, and perform the level conversion and digital-to-analog conversion on the even-numbered row of data.
In some embodiments, the source driving circuit further includes an output buffer.
The output buffer is coupled to the latch sub-circuit and the output sub-circuit, and the output buffer is configured to: receive the odd-numbered row of data in the odd-numbered frame, and temporarily store the odd-numbered row of data; and receive the even-numbered row of data in the even-numbered frame, and temporarily store the even-numbered row of data.
In some embodiments, the first set duration is equal to the second set duration.
In another aspect, a source driving method is provided. The source driving method includes:
In some embodiments, the first set duration is twice the charging time of the sub-pixels in the even-numbered row in the odd-numbered frame; and/or the second set duration is twice the charging time of the sub-pixels in the odd-numbered row in even-numbered frame.
In some embodiments, generating the first latch signal and the first enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal, includes:
Generating the second latch signal and the second enable signal according to the gate start signal, the first mode switching signal, the initial latch enable signal and the source output enable signal, includes:
In some embodiments, generating the first mask signal according to the gate start signal and the first mode switching signal, includes:
Generating the second mask signal according to the gate start signal and the first mode switching signal, includes:
The first row representation signal is at a low level in a time of the odd-numbered row and at a high level in a time of the even-numbered row; the first frame representation signal is at a low level in a time of the odd-numbered frame and at a high level in a time of the even-numbered frame; or the first row representation signal is at the high level in the time of the odd-numbered row and at the low level in the time of the even-numbered row; the first frame representation signal is at the high level in the time of the odd-numbered frame and at the low level in the time of the even-numbered frame.
In yet another aspect, a display device is provided. The display device includes: a plurality of source driving circuits each being as described in any one of the above embodiments, at least one timing control circuit and a display panel.
The at least one timing control circuit is configured to output the source data signal, the gate start signal, the first mode switching signal, a second mode switching signal, the initial latch enable signal and the source output enable signal. Each timing control circuit is coupled to at least two source driving circuits.
The display panel is coupled to the at least one timing control circuit and the plurality of the source driving circuits.
In some embodiments, the display device includes two timing control circuits. The plurality of source driving circuits are divided into two groups, and each group of source driving circuits are coupled to a timing control circuit in the two timing control circuits. A refresh frequency of the timing control circuit is X, and an amount of image data that is capable of being transmitted in each frame is Y; a target refresh frequency of the display panel is X0, and an amount of target image data that is required for each frame is Y0; and a product of X and Y equals half a product of X0 and Y0
In yet another aspect, a display driving method is provided, which is applied to the display device described in any one of the above embodiments. The display driving method includes:
In some embodiments, in the odd-numbered frame, for sub-pixels in two adjacent rows, when a charging time of sub-pixels in an odd-numbered row in the two adjacent rows reaches half the first set duration, sub-pixels in an even-numbered row in the two adjacent rows of are turned on for charging; and in the even-numbered frame, for the sub-pixels in the two adjacent rows, when a charging time of the sub-pixels in the even-numbered row in the two adjacent rows reaches half of the second set duration, the sub-pixels in the odd-numbered row are turned on for charging.
In order to describe technical solutions in the present disclosure more dearly, accompanying drawings to be used in some embodiments of the present disclosure will be introduced briefly below. Obviously, the accompanying drawings to be described below are merely accompanying drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art may obtain other drawings according to these accompanying drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, and are not limitations on actual sizes of products, actual processes of methods and actual timings of signals involved in the embodiments of the present disclosure.
Technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure shall be included in the protection scope of the present disclosure.
Unless the context requires otherwise, throughout the specification and the claims, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as an open and inclusive meaning, i.e., “including, but not limited to”. In the description of the specification, the terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.
Hereinafter, the terms such as “first” and “second” are used for descriptive purposes only, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with “first” or “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the terms “a plurality of”, “the plurality of” and “multiple” each mean two or more unless otherwise specified.
In the description of some embodiments, terms such as “coupled” and “connected” and their derivatives may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term “coupled” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.
The phrase “applicable to” or “configured to” used herein means an open and inclusive expression, which does not exclude devices that are applicable to or configured to perform additional tasks or steps.
In addition, the phrase “based on” used is meant to be open and inclusive, since a process, step, calculation or other action that is “based on” one or more of the stated conditions or values may, in practice, be based on additional conditions or value exceeding those stated.
As used herein, terms such as “about”, “substantially” or “approximately” include a stated value and an average value within an acceptable range of deviation of a particular value. The acceptable range of deviation is determined by a person of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).
As used herein, the term “equal” includes a stated condition and a condition similar to the stated condition. A range of the similar condition is within an acceptable range of deviation of a particular value. The acceptable range of deviation is determined by a person of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, the term “equal” includes absolute equality and approximate equality, and an acceptable range of deviation of the approximate equality may be, for example, a difference between two equals of less than or equal to 5% of either of the two equals.
As shown in
The display device 1000 includes a plurality of source driving circuits 100, at least one timing control circuit 200 and a display panel 300.
The timing control circuit 200 is configured to output a source data signal WDT, a gate start signal WGSP, a first mode switching signal WOD1, a second mode switching signal WOD2, an initial latch enable signal WLA and a source output enable signal WSOE. Each timing control circuit 200 is coupled to at least two source driving circuits 100.
In some examples, as shown in
In some examples, as shown in
The display panel 300 is coupled to the at least one timing control circuit 200 and the plurality of source driving circuits 100.
In some examples, as shown in
For example, the source driving circuits 100 may each be located on one chip-on-film, chip-on-films may be bonded on one printed circuit board 302, each timing control circuit 200 may be coupled to printed circuit board(s) 302, and two printed circuit board 302 may be coupled by a flexible circuit board 301.
It can be understood that, the number of the source driving circuits 100 in
For example, as shown in
The plurality of sub-pixels 310 may be arranged in multiple rows along a column direction. For example, the dotted box Q in
The source driving circuits 100 may provide data to sub-pixels 310 in each row through the plurality of data lines DL.
In some examples, as shown in
For example, the grayscale control circuit 400 is coupled to the timing control circuit 200 and the source driving circuits 100. The grayscale control circuit 400 may be configured to provide a gamma signal to the source driving circuits 100 according to image data from the timing control circuit 200.
For example, the gate driving circuit 500 may be coupled to the timing control circuit 200. The timing control circuit 200 may control the gate driving circuit 500 to provide gate scan signals to sub-pixels 310 in respective rows through the plurality of gate lines GL, so as to control a charging time of sub-pixels in each row.
In some embodiments, as shown in
A refresh frequency of the timing control circuit 200 is X, and an amount of image data that is capable of being transmitted in each frame is Y; a target refresh frequency of the display panel 300 is X0 and an amount of target image data that is required for each frame is Y0; and
The display device 1000 includes the two timing control circuits 200. In this way, the refresh frequency X of the timing control circuit 200 may be half the target refresh frequency X0, so that the amount of the image data Y that is capable of being transmitted in each frame is the same as the amount of the target image data Y0 that is required for each frame; or the refresh frequency X of the timing control circuit 200 may be the same as the target refresh frequency X0, so that the amount of the image data Y that is capable of being transmitted in each frame is half the amount of the target image data Y0 that is required for each frame. Therefore, the display device has low performance requirements on the timing control circuit 200, and the timing control circuit 200 is easy to get, which helps reduce the manufacturing costs of the timing control circuit 200. As a result, the manufacturing costs of the display device 1000 are reduced.
For example, in a case where the target refresh frequency of the display panel 300 is 120 Hz, the refresh frequency of the timing control circuit 200 may be 60 Hz.
As shown in
The logic and control sub-circuit 10 is coupled to a source data signal terminal Vin, a gate start signal terminal GSP, a mode switching signal terminal ODEN, an initial latch enable signal terminal LAT and a source output enable signal terminal SOE. The logic and control sub-circuit 10 is configured to: receive the source data signal WDT from the source data signal terminal Vin and convert the source data signal WDT into a data signal WD; and output a first latch signal W1, a second latch signal W2, a first enable signal W3 and a second enable signal W4 according to the gate start signal WGSP from the gate start signal terminal GSP, the first mode switching signal WOD1 from the mode switching signal terminal ODEN, the initial latch enable signal WLA from the initial latch enable signal terminal LAT and the source output enable signal WSOE from the source output enable signal terminal SOE.
For example, converting the source data signal WDT into the data signal WD may be realized by means such as data inversion, serial-to-parallel conversion, data sampling to process the source data signal WDT, so as to convert the source data signal WDT into the data signal WD. The means of converting the source data signal WDT into the data signal WD are not limited in the embodiments of the present disclosure.
The latch sub-circuit 20 is coupled to the logic and control sub-circuit 10. The latch sub-circuit 20 is configured to: receive the data signal WD from the logic and control sub-circuit 10; latch an odd-numbered row of data WD1 in the data signal WD in an odd-numbered frame under control of the first latch signal W1; and latch an even-numbered row of data WD2 in the data signal WD in an even-numbered frame under control of the second latch signal W2.
The output sub-circuit 30 is coupled to the logic and control sub-circuit 10 and the latch sub-circuit 20. Referring to
For example, the source data signal WDT, the gate start signal WGSP, the first mode switching signal WOD1, the initial latch enable signal Wu and the source output enable signal WSOE may be provided by the timing control circuit 200.
For example, the gate start signal WGSP may serve to indicate the start of each frame, that is, the gate driving circuit 500 starts to provide gate scan signals for sub-pixels 310 in respective rows through the plurality of gate lines GL.
For example, a variation of an output voltage of the source driving circuit 100 in the odd-numbered frame may be as shown in a waveform of the WOUT in
In the odd-numbered frame, the odd-numbered row of data WD1 in the data voltage WD (e.g., 1, 3, 5 and 7 in
For example, in
For example, in
It will be noted that, in
In some embodiments of the present disclosure, the source driving circuit 100 outputs the odd-numbered row of data WD1 in the first set duration T1 in the odd-numbered frame, the first set duration T1 is greater than the charging time of the sub-pixels in the even-numbered row, and is less than or equal to twice the charging time of the sub-pixels in the even-numbered row; and the source driving circuit 100 outputs the even-numbered row of data WD2 in the second set duration T2 in the even-numbered frame, the second set duration T2 is greater than the charging time of the sub-pixels in the odd-numbered row, and is less than or equal to twice the charging time of the sub-pixels in the odd-numbered row. Therefore, the charging time of the sub-pixels 310 in the odd-numbered row in the odd-numbered frame is relatively long, which helps ensure that the sub-pixels 310 in the odd-numbered row can display a target gray scale in the odd-numbered frame; and the charging time of the sub-pixels 310 in the even-numbered row in the even-numbered frame is also relatively long, which helps ensure that the sub-pixels 310 in the even-numbered row can display a target gray scale in the even-numbered frame.
In some embodiments, referring to
In some other embodiments, referring to
In yet some other embodiments, in the odd-numbered frame, the first set duration T1 is twice the charging time of the sub-pixels in the even-numbered row; and in the even-numbered frame, the second set duration T2 is twice the charging time of the sub-pixels in the odd-numbered row. In this case, the charging time of the sub-pixels 310 in the odd-numbered row in the odd-numbered frame is longer, and the charging time of the sub-pixels 310 in the even-numbered row in the even-numbered frame is also longer. When the charging is completed, the output voltage of the source driving circuit 100 to the sub-pixels in the odd-numbered row in the odd-numbered frame can reach the maximum value, and the output voltage of the source driving circuit 100 to the sub-pixels in the even-numbered row in the even-numbered frame can reach the maximum value, and they both do not change. Thus, it is further ensured that the sub-pixels 310 in the odd-numbered row can display the target gray scale in the odd-numbered frame, and the sub-pixels 310 in the even-numbered row can display the target gray scale in the even-numbered frame.
In some embodiments, the first set duration T1 is equal to the second set duration T2. In this case, the charging time of the sub-pixels 310 in the odd-numbered row in the odd-numbered frame and the charging time of the sub-pixels 310 in the even-numbered row in the even-numbered frame are the same, and a charging time of the sub-pixels 310 in the even-numbered row in the odd-numbered frame and a charging time of the sub-pixels in the odd-numbered row in the even-numbered frame are the same. This helps simplify a circuit configuration of the source driving circuit 100, and reduce the design difficulty of the source driving circuit 100, thereby reducing manufacturing costs of the source driving circuit 100.
For example, the first set duration T1 and the second set duration T2 may both be 3.7 microseconds. The charging time of the sub-pixels in the even-numbered row may be 1.85 microseconds in the odd-numbered frame. The charging time of the sub-pixels in the odd-numbered row may be 1.85 microseconds in the even-numbered frame.
Of course, in the embodiments of the present disclosure, the first set duration T1, the second set duration T2, the charging time of the sub-pixels in the even-numbered row and the charging time of the sub-pixels in the odd-numbered row are not limited thereto.
In some embodiments, as shown in
The latch signal generation module 12 is coupled to the mask signal generation module 11 and the initial latch enable signal terminal LAT. The latch signal generation module 12 is configured to, generate the first latch signal W1 according to the first mask signal W5 and the initial latch enable signal WLA, and generate the second latch signal W2 according to the second mask signal W6 and the initial latch enable signal WLA.
The enable signal generation module 13 is coupled to the mask signal generation module 11 and the source output enable signal terminal SOE. The enable signal generation module 13 is configured to, generate the first enable signal W3 according to the first mask signal W5 and the source output enable signal WSOE, and generate the second enable signal W4 according to the second mask signal W6 and the source output enable signal WSOE.
In some embodiments, as shown in
The distinguishing unit 111 is coupled to a pulse signal terminal CHOP, the gate start signal terminal GSP and the mode switching signal terminal ODEN. The distinguishing unit 111 is configured to output a pair of row representation signals (WL1, WL1B) and a pair of frame representation signals (WF1, WF1B) according to a pulse signal WCH from the pulse signal terminal CHOP, the gate start signal WGSP and the first mode switching signal WOD1. The pair of row representation signals (Wu, WL1B) represent the odd-numbered row and the even-numbered row, and the pair of frame representation signals (WF1, WF1B) represent the odd-numbered frame and the even-numbered frame.
For example, a rising edge of the pulse signal WCH from the pulse signal terminal CHOP may be at a same time as a rising edge of the source output enable signal WSOE.
For example, the first row representation signal WL1 is at a low level in a time of the odd-numbered row and at a high level in a time of the even-numbered row; the first frame representation signal WF1 is at a low level in a time of the odd-numbered frame and at a high level in a time of the even-numbered frame.
Alternatively, the first row representation signal WL1 is at the high level in the time of the odd-numbered row and at the low level in the time of the even-numbered row; the first frame representation signal WF1 is at the high level in the time of the odd frame and at the low level in the time of the even-numbered frame.
The generation unit 112 is coupled to the distinguishing unit 111. The generation unit 112 is configured to generate the first mask signal W5 and the second mask signal W6 according to the pair of row representation signals (WL1, WL1B), the pair of frame representation signals (WF1, WF1B) and an inverted and delayed signal WSBD of the source output enable signal WSOE.
For example, the timing control circuit 200 may generate the inverted and delayed signal WSBD of the source output enable signal WSOE and then provide this signal to an inverted and delayed signal terminal SOEBD of the source driving circuit 100. Based on this, referring to
For example, the source driving circuit 100 may also obtain the inverted and delayed signal WSBD of the source output enable signal WSOE by performing an inversion and delay processing on the source output enable signal WSOE. Referring to
For example, the inverting and delaying module 14 may include a resistor-capacitance (RC) delay circuit. Of course, the inverting and delaying module 14 in the embodiments of the present disclosure is not limited thereto.
For example, as shown in
For the NAND gate 1111, a first input terminal of the NAND gate 1111 is coupled to the pulse signal terminal CHOP, and a second input terminal of the NAND gate 1111 is coupled to the gate start signal terminal GSP.
For the first NOT gate 1112, an input terminal of the first NOT gate 1112 is coupled to an output terminal of the NAND gate 1111.
For the first flip-flop 1113, an enable terminal of the first flip-flop 1113 is coupled to an output terminal of the first NOT gate 1112, a reset terminal of the first flip-flop 1113 is coupled to the mode switching signal terminal ODEN, a first output terminal Q and a second output terminal Q of the first flip-flop 1113 are coupled to the generation unit 112, and an input terminal D of the first flip-flop 1113 is coupled to the first output terminal Q of the first flip-flop 1113. The first output terminal Q of the first flip-flop 1113 is configured to output the first frame representation signal WF1, and the second output terminal Q of the first flip-flop 1113 is configured to output the second frame representation signal WF1B. The first frame representation signal WF1 and the second frame representation signal WF1B are inverted, and constitute the pair of frame representation signals (WF1, WF1B).
For the first AND gate 1114, a first input terminal of the first AND gate 1114 is coupled to the output terminal of the NAND gate 1111, and a second input terminal of the first AND gate 1114 is coupled to the mode switching signal terminal ODEN.
For the second flip-flop 1115, an enable terminal of the second flip-flop 1115 is coupled to the pulse signal terminal CHOP; a reset terminal of the second flip-flop 1115 is coupled to an output terminal of the first AND gate 1114, an first output terminal
For example, the first flip-flop 1113 and the second flip-flop 1115 may be edge D type flip-flops. Enable terminals of the first flip-flop 1113 and the second flip-flop 1115 are valid at rising edges of respective signals transmitted thereto.
For example, as shown in
A first input terminal and a second input terminal of the multiplier 1121 are coupled to the distinguishing unit 111, and are configured to receive the pair of row representation signals (WL1, WL1B). A third input terminal and a fourth input terminal of the multiplier 1121 are coupled to the distinguishing unit 111, and are configured to receive the pair of frame representation signals (WF1, WF1B).
For the third flip-flop 1122, an input terminal D of the third flip-flop 1122 is coupled to an output terminal of the multiplier 1121. An enable terminal of the third flip-flop 1122 is configured to receive the inverted and delayed signal WSBD of the source output enable signal WSOE, and an output terminal Q of the third flip-flop 1122 is configured to output the first mask signal W5 and the second mask signal W6.
For example, the third flip-flop 1122 may be an edge D type flip-flop. The enable terminal of the third flip-flop 1122 is valid at a rising edge of a signal transmitted thereto.
For example, as shown in
For the second NOT gate 121, an input terminal of the second NOT gate 121 is coupled to the mask signal generation module 11.
For the second AND gate 122, a first input terminal of the second AND gate 122 is coupled to an output terminal of the second NOT gate 121, and a second input terminal of the second AND gate 122 is coupled to the initial latch enable signal terminal LAT. An output terminal of the second AND gate 122 is configured to output the first latch signal W1 in the odd-numbered frame and the second latch signal W2 in the even-numbered frame.
For example, as shown in
An input terminal IN of the signal generator 131 is coupled to the source output enable signal terminal SOE, and an enable terminal ENB of the signal generator 131 is coupled to the mask signal generation module 11. An output terminal OUT of the signal generator 131 is configured to output the first enable signal W3 and the second enable signal W4.
For example, in the odd-numbered frame, timings of the source output enable signal WSOE, the gate start signal WGSP, the pulse signal WCH, the initial latch enable signal WLA, the inverted and delayed signal WSBD of the source output enable signal WSOE, the first row representation signal WL1, the first frame representation signal WF1, a signal WF1L1 output by the multiplier 1121, the first mask signal W5, the first latch signal W1, the first enable signal W3 and the odd-numbered row of data WD1 are shown in
A working process of the logic and control sub-circuit 10 as shown in
At time t0:
the pulse signal WCH changes from a low level to a high level, the high level of the pulse signal WCH and a high level of the gate start signal WGSP are converted to a low level by the NAND gate 1111, and then converted to a high level by the first NOT gate 1112, so that the enable terminal of the first flip-flop 1113 is valid (that is, the enable terminal of the first flip-flop 1113 is triggered by a rising edge of a signal transmitted thereto).
The input terminal of the first flip-flop 1113 is connected to the first output terminal of the first flip-flop 1113, so that in this case, a level (i.e., a high level) output from the second output terminal of the first flip-flop 1113 is the same as a level of the first output terminal of the first flip-flop 1113 before time t0. The level output from the first output terminal of the first flip-flop 1113 is converted from an original high level to a low level at time t0.
The first output terminal of the first flip-flop 1113 outputs the first frame representation signal WF1, a low level of the first frame representation signal WF1 represents a first frame (i.e., an odd-numbered frame). The second output terminal of the first flip-flop 1113 outputs the second frame representation signal WF1B, a high level of the second frame representation signal WF1B also represents the first frame (i.e., the odd-numbered frame).
The pulse signal WCH changes from the low level to the high level, so that the enable terminal of the second flip-flop 1115 is valid (that is, the enable terminal of the second flip-flop 1115 is triggered by a rising edge of a signal transmitted thereto).
The input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that in this case, a level (i.e., a high level) output from the second output terminal of the second flip-flop 1115 is the same as a level of the first output terminal of the second flip-flop 1115 before time t0. The level output from the first output terminal of the second flip-flop 1115 is converted from an original high level to a low level at time t0.
The first output terminal of the second flip-flop 1115 outputs the first row representation signal WL1, and the low level of the first row representation signal WL1 represents a first row (i.e., an odd-numbered row). The second output terminal of the second flip-flop 1115 outputs the second row representation signal WL1B, and a high level of the second row representation signal WL1B represents the first row (i.e., the odd-numbered row).
The multiplier 1121 receives the first row representation signal WL1, the second row representation signal WL1B, the first frame representation signal WF1 and the second frame representation signal WF1B, and outputs a high level. That is, a level of WF1L1 changes to the high level at time t0.
The enable terminal of the third flip-flop 1122 is valid at a rising edge of a signal transmitted thereto. However, the inverted and delayed signal WSBD of the source output enable signal WSOE is at a high level at time t0, and there is no change from a low level to the high level. Therefore, the enable terminal of the third flip-flop 1122 is invalid, and the output terminal of the third flip-flop 1122 still outputs a low level. That is, the first mask signal W5 output from the output terminal of the third flip-flop 1122 is at the low level.
In this way, before a rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, a waveform of the first latch signal W1 obtained after the first mask signal W5 passes through the second NOT gate 121 and the initial latch enable signal WLA passes through the second AND gate 122 is the same as a waveform of the initial latch enable signal Wu. Therefore, when the first row of data arrives, the rising edge of the first latch signal W1 may control the latch sub-circuit 20 to latch the first row of data.
Similarly, before the rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, the first mask signal W5 is at the low level, so that the enable terminal of the signal generator 131 is invalid. The first enable signal W3 remains inverted with the source output enable signal WSOE. Therefore, the first enable signal W3 can control the output sub-circuit 30 to output data of the third row.
At time t1:
In this way, before a next rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, the first mask signal W5 remains at the high level all the time. The first latch signal W1 obtained after the first mask signal W5 passes through the second NOT gate 121 and the initial latch enable signal Wu passes through the second AND gate 122 remains at a low level all the time. Therefore, after a second row of data arrives, the latch sub-circuit 20 no longer latches the second row of data.
Similarly, before the next rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, the first mask signal W5 remains at a high level, so that the enable terminal of the signal generator 131 is valid. The first enable signal W3 no longer changes with a change of the source output enable signal WSOE. As a result, the source driving circuit 100 outputs the odd-numbered row of data all the time.
At time t2:
The first output terminal of the first flip-flop 1113 keeps outputting the low level, and the second output terminal of the first flip-flop 1113 keeps outputting the high level, so that the levels output from the two output terminals still represent the first frame (i.e., the odd-numbered frame).
The pulse signal WCH changes from the low level to the high level again, so that the enable terminal of the second flip-flop 1115 is valid again (that is, the enable terminal of the second flip-flop 1115 is triggered by the rising edge of the signal transmitted thereto).
The input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that in this case, the level (i.e., a low level) output from the second output terminal of the second flip-flop 1115 is the same as the level of the first output terminal of the second flip-flop 1115 before time t2. The level output from the first output terminal of the second flip-flop 1115 is converted from an original low level to a high level at time t2.
The first output terminal of the second flip-flop 1115 outputs the first row representation signal Wu, and the high level of the first row representation signal WL1 represents a second row (i.e., an even-numbered row). The second output terminal of the second flip-flop 1115 outputs the second row representation signal WL1B, and a low level of the second row representation signal WL1B represents the second row (i.e., the even-numbered row).
The multiplier 1121 receives the first row representation signal Wu, the second row representation signal WL1B, the first frame representation signal WF1 and the second frame representation signal WF1B, and outputs a low level. That is, the level of WF1L1 changes to the low level at time t2.
The enable terminal of the third flip-flop 1122 is valid at the rising edge of the signal transmitted thereto. However, the inverted and delayed signal WSBD of the source output enable signal WSOE is at the high level at time t2. Therefore, the output terminal of the third flip-flop 1122 still outputs the high level. That is, the first mask signal W5 output from the output terminal of the third flip-flop 1122 is at the high level.
In this way, before the rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, the first latch signal W1 obtained after the first mask signal W5 passes through the second NOT gate 121 and the initial latch enable signal WLA passes through the second AND gate 122 remains at the low level all the time. Therefore, after the second row of data arrives, there is no rising edge in the first latch signal W1, so that the latch sub-circuit 20 no longer latches the second row of data.
Similarly, before the rising edge of the inverted and delayed signal WSBD of the source output enable signal WSOE arrives, the first mask signal is at the high level, so that the enable terminal of the signal generator 131 is valid. The first enable signal W3 no longer changes with the change of the source output enable signal WSOE. Therefore, the source driving circuit 100 outputs the odd-numbered row of data all the time.
At time t3:
In this way, the waveform of the first latch signal W1 obtained after the first mask signal W5 passes through the second NOT gate 121 and the initial latch enable signal WLA passes through the second AND gate 122 is the same as the waveform of the initial latch enable signal WLA again. Therefore, when a third row of data arrives, the rising edge of the first latch signal W1 may control the latch sub-circuit 20 to latch the third row of data.
Similarly, the first mask signal W5 is at the low level, so that the enable terminal of the signal generator 131 is invalid. The first enable signal W3 remains inverted with the source output enable signal WSOE. Therefore, the first enable signal W3 can control the output sub-circuit 30 to output the third row of data.
At time t4:
However, the enable terminal of the second flip-flop 1115 is valid again (that is, the enable terminal of the second flip-flop 1115 is triggered by the rising edge of the signal transmitted thereto). The input terminal of the second flip-flop 1115 is connected to the first output terminal of the second flip-flop 1115, so that in this case, the level (i.e., the high level) output from the second output terminal of the second flip-flop 1115 is the same as the level of the first output terminal of the second flip-flop 1115 before time t4. The level output from the first output terminal of the second flip-flop 1115 is converted from an original high level to a low level at time t4.
The first output terminal of the second flip-flop 1115 outputs the first row representation signal WL1, and the low level of the first row representation signal WL1 represents a third row (i.e., an odd-numbered row). The second output terminal of the second flip-flop 1115 outputs the second row representation signal WL1B, and a high level of the second row representation signal WL1B represents the third row (i.e., the odd-numbered row).
The multiplier 1121 receives the first row representation signal WL1, the second row representation signal WL1B, the first frame representation signal WF1 and the second frame representation signal WF1B, and outputs a high level. That is, the level of WF1L1 changes to the high level at time t4.
The enable terminal of the third flip-flop 1122 is valid at the rising edge of the signal transmitted thereto. However, the inverted and delayed signal WSBD of the source output enable signal WSOE is at the high level at time t4. Therefore, the output terminal of the third flip-flop 1122 still outputs the low level. That is, the first mask signal W5 output from the output terminal of the third flip-flop 1122 is at the low level.
In this way, the waveform of the first latch signal W1 obtained after the first mask signal W5 passes through the second NOT gate 121 and the initial latch enable signal WLA passes through the second AND gate 122 is the same as the waveform of the initial latch enable signal WA. Therefore, when the third row of data arrives, the rising edge of the first latch signal W1 may control the latch sub-circuit 20 to latch the third row of data.
Similarly, the first mask signal W5 is at the low level, so that the enable terminal of the signal generator 131 is invalid. The first enable signal W3 remains inverted with the source output enable signal WSOE. Therefore, the first enable signal W3 can control the output sub-circuit 30 to output the third row of data.
Referring to the working process of the source driving circuit 100 at times t0 to t4, in the odd-numbered frame, and after time t4, the low level of the first frame representation signal WF1 is still output, and the high level of the second frame representation signal WF1B is still output, thereby representing the first frame (i.e., the odd-numbered frame).
The low level of the first row representation signal Wu is output under control of an odd-numbered rising edge of the pulse signal WCH, and the high level of the second row representation signal WL1B is output under the control of the odd-numbered rising edge of the pulse signal WCH, thereby representing the odd-numbered row under the control of the odd-numbered rising edge of the pulse signal WCH.
In addition, the high level of the first row representation signal WL1 is output under control of an even-numbered rising edge of the pulse signal WCH, and the low level of the second row representation signal WL1B is output under the control of the even-numbered rising edge of the pulse signal WCH, thereby representing the even-numbered row under the control of the even-numbered rising edge of the pulse signal WCH.
The multiplier 1121 also outputs the signal WF1L1 after receiving the first row representation signal WL1, the second row representation signal WL1B, the first frame representation signal WF1 and the second frame representation signal WF1B. The signal WF1L1 changes from the low level to the high level at a time of the odd-numbered rising edge of the pulse signal WCH. The signal WF1L1 changes from the high level to the low level at a time of the even-numbered rising edge of the pulse signal WCH.
A level of first mask signal W5, which is the same as the signal WF1L1, is output under control of the inverted and delayed signal WSBD of the source output enable signal WSOE, so that the first latch signal W1 controls the latch sub-circuit 20 to latch only the odd-numbered row of data in the odd-numbered frame, and the first enable signal W3 controls the output sub-circuit 30 to output only the odd-numbered row of data in the odd-numbered frame.
For example, in the even-numbered frame, timings of the source output enable signal WSOE, the gate start signal WGSP, the pulse signal WCH, the initial latch enable signal WLA, the inverted and delayed signal WSBD of the source output enable signal WSOE, the first row representation signal WL1, the first frame representation signal WF1, the signal WF1L1 output by the multiplier 1121, the second mask signal W6, the second latch signal W2, the second enable signal W4, and the even-numbered row of data WD2 are shown in
The working process of the logic and control sub-circuit 10 as shown in
It is worth noting that, in the even-numbered frame, when the pulse signal WCH changes from the low level to the high level for a first time (i.e., at the time of a first rising edge thereof), the gate start signal WGSP is at the high level again. As a result, the high level of the pulse signal WCH and the high level of the gate start signal WGSP are converted to the low level by the NAND gate 1111, and then converted to the high level by the first NOT gate 1112, so that the enable terminal of the first flip-flop 1113 is valid (that is, the enable terminal of the first flip-flop 1113 is triggered by the rising edge of the signal transmitted thereto).
The input terminal of the first flip-flop 1113 is connected to the first output terminal of the first flip-flop 1113, so that in this case, the level (i.e., the low level) output from the second output terminal of the first flip-flop 1113 is the same as the level of the first output terminal of the first flip-flop 1113 in the odd-numbered frame. The level output from the first output terminal of the first flip-flop 1113 is converted from a previous low level to the high level.
That is, the first frame representation signal WF1 output from the first output terminal of the first flip-flop 1113 is at the high level, and represents a second frame (i.e., an even-numbered frame). The second frame representation signal WF1B output from the second output terminal of the first flip-flop 1113 is at the low level, and also represents the second frame (i.e., the even-numbered frame). In addition, in the second frame (i.e., the even-numbered frame), levels of the first frame representation signal WF1 and the second frame representation signal WF1B no longer change.
In some embodiments, the first mode switching signal WOD1 may remain at a high level in both the odd-numbered frame and the even-numbered frame. In some other embodiments, the first mode switching signal WOD1 may remain at a low level in both the odd-numbered frame and the even-numbered frame.
In some embodiments, referring to
The latch sub-circuit 20 is further configured to latch the odd-numbered row of data WD1 and the even-numbered row of data WD2 in the data signal WD in each frame under control of the initial latch enable signal WLA.
The output sub-circuit 30 is further configured to output the odd-numbered row of data WD1 and the even-numbered row of data WD2 under control of the source output enable signal WSOE. The charging time of the sub-pixels in the odd-numbered row and the charging time of the sub-pixels in the even-numbered row are equal. That is, an output time of the odd-numbered row of data WD1 and an output time of the even-numbered row of data WD2 are equal.
In this way, the source driving circuit 100 may have two driving modes: in a first mode, the odd-numbered row of data is output in the first set duration in the odd-numbered frame, and the even-numbered row of data is output in the second set duration in the even-numbered frame; in a second mode, the odd-numbered row of data and the even-numbered row of data are output in each frame, and the odd-numbered row of data and the even-numbered row of data have the same output time. As a result, the source driving circuit 100 has variety in the driving method.
In some embodiments, as shown in
The level conversion and digital-to-analog conversion sub-circuit 40 is coupled to the latch sub-circuit 20 and the output sub-circuit 30. The level conversion and digital-to-analog conversion sub-circuit 40 is configured to: receive the odd-numbered row of data WD1 in the odd-numbered frame, and perform level conversion and digital-to-analog conversion on the odd-numbered row of data WD1; receive the even-numbered row of data WD2 in the even-numbered frame, and perform the level conversion and digital-to-analog conversion on the even-numbered row of data WD2. A circuit configuration of the level conversion and digital-to-analog conversion sub-circuit 40 is not specifically limited in the embodiments of the present disclosure.
For example, level conversion may amplify the odd-numbered row of data and the even-numbered row of data.
In some embodiments, as shown in
A circuit configuration of the output buffer 50 is not specifically limited in the embodiments of the present disclosure.
In some embodiments, as shown in
As shown in
in an odd-numbered frame:
in an even-numbered frame:
Beneficial effects that can be achieved by the source driving method provided in the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the source driving circuit, and details will not be repeated here.
In some embodiments, the first set duration T1 is twice the charging time of the sub-pixels in the even-numbered row in the odd-numbered frame.
In some other embodiments, the second set duration T2 is twice the charging time of the sub-pixels in the odd-numbered row in the even-numbered frame.
In yet some other embodiments, the first set duration T1 is twice the charging time of the sub-pixels in the even-numbered row in the odd-numbered frame, and the second set duration T2 is twice the charging time of the sub-pixels in the odd-numbered row in the even-numbered frame.
In some embodiments, as shown in
In S210, a first mask signal W5 is generated according to the gate start signal WGSP and the first mode switching signal WOD1.
For example, as shown in
S211, receiving a pulse signal WCH, and generating a pair of row representation signals (WL1, WL1B) and a pair of frame representation signals (WF1, WF1B) according to the pulse signal WCH, the gate start signal WGSP and the first mode switching signal WOD1; the pair of row representation signals (WL1, WL1B) including a first row representation signal WL1 and a second row representation signal WL1B that are mutually inverted, and the pair of frame representation signals (WF1, WF1B) including a first frame representation signal WF1 and a second frame representation signal WF1B that are mutually inverted; and
S212, generating the first mask signal W5 according to the pair of row representation signals (WL1, WL1B), the pair of frame representation signals (WF1, WF1B) and an inverted and delayed signal WSBD of the source output enable signal WSOE.
The first row representation signal WL1 is at a low level in a time of the odd-numbered row and at a high level in a time of the even-numbered row; the first frame representation signal WF1 is at a low level in a time of the odd-numbered frame and at a high level in a time of the even-numbered frame.
Alternatively, the first row representation signal WL1 is at the high level in the time of the odd-numbered row and at the low level in the time of the even-numbered row; the first frame representation signal WF1 is at the high level in the time of the odd-numbered frame and at the low level in the time of the even-numbered frame.
In S220, the first latch signal W1 is generated according to the first mask signal W5 and the initial latch enable signal WA.
In S230, the first enable signal W3 is generated according to the first mask signal W5 and the source output enable signal WSOE.
In some embodiments, as shown in
In S210′, a second mask signal W6 is generated according to the gate start signal WGSP and the first mode switching signal WOD1.
For example, as shown in
S211′, receiving the pulse signal WCH, and generating the pair of row representation signals (WL1, WL1B) and the pair of frame representation signals (WF1, WF1B) according to the pulse signal WCH, the gate start signal WGSP and the first mode switching signal WOD1; the pair of row representation signals (WL1, WL1B) including the first row representation signal Wu and the second row representation signal WL1B that are mutually inverted, and the pair of frame representation signals (WF1, WF1B) including the first frame representation signal WF1 and the second frame representation signal WF1B that are mutually inverted; and
S212′, generating the second mask signal W6 according to the pair of row representation signals (WL1, WL1B), the pair of frame representation signals (WF1, WF1B) and the inverted and delayed signal WSBD of the source output enable signal WSOE.
The first row representation signal Wu is at the low level in the time of the odd-numbered row and at the high level in the time of the even-numbered row; the first frame representation signal WF1 is at the low level in the time of the odd-numbered frame and at the high level in the time of the even-numbered frame. Alternatively, the first row representation signal WL1 is at the high level in the time of the odd-numbered row and at the low level in the time of the even-numbered row; the first frame representation signal WF1 is at the high level in the time of the odd-numbered frame and at the low level in the time of the even-numbered frame.
In S220′, the second latch signal W2 is generated according to the second mask signal W6 and the initial latch enable signal WLA.
In S230′, the second enable signal W4 is generated according to the second mask signal W6 and the source output enable signal WSOE.
As shown in
Some embodiments of the present disclosure provide a display driving method, which is applied to the display device 1000 described in any one of the embodiments. As shown in
in an odd-numbered frame:
in an even-numbered frame:
Beneficial effects that can be achieved by the display driving method provided in the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the source driving circuit, and details will not repeated here.
In some embodiments, the charging time of the sub-pixels in the even-numbered row is equal to half the first set duration T1 in the odd-numbered frame.
In some other embodiments, the charging time of the sub-pixels in the odd-numbered row is equal to half the second set duration T2 in the even-numbered frame.
In yet some other embodiments, the charging time of the sub-pixels in the even-numbered row is equal to half the first set duration T1 in the odd-numbered frame, and the charging time of the sub-pixels in the odd-numbered row is equal to half the second set duration T2 in the even-numbered frame.
In some examples, as shown in
The foregoing descriptions are merely specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements that a person skilled in the art could conceive of within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/125843 | 10/22/2021 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2023/065338 | 4/27/2023 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20230186823 | Zhang | Jun 2023 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20240221586 A1 | Jul 2024 | US |
