The invention relates generally to transmitter and, more particularly, to voltage mode transmitter having an H-bridge that uses source-followers.
Turning to
Some examples of conventional circuits are: U.S. Pat. No. 6,917,169; U.S. Pat. No. 5,689,144; U.S. Patent Pre-Grant Publ. No. 2008/0252372; and Krenzket et al., “A 36-V H-BRIDGE DRIVER INTERFACE IN A STANDARD 0.35-μm CMOS PROCESS,” IEEE Intl. Symposium on Circuits and Systems 2005, Vol. 4, May 23-26, 2005, pp. 3651-3554.
An embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a first supply rail; a second supply rail; an H-bridge having: a first node; a second node; a third node; a fourth node; a first switch that is coupled between the first and third nodes; a second switch that is coupled between the first and fourth nodes; a third switch that is coupled between the second and third nodes; and a fourth switch that is coupled between the second and fourth nodes; a first source-follower that is coupled to the first node of the H-bridge, that is coupled to the first supply rail, and that is configured to receive a first reference signal; and a second source-follower that is coupled to the second node of the H-bridge, that is coupled to the second supply rail, and that is configured to receive a second reference signal.
In accordance with an embodiment of the present invention, the first and second switches further comprise first and second PMOS transistors, wherein each of the first and second PMOS transistors are coupled to the first node at its source.
In accordance with an embodiment of the present invention, the third and fourth switches further comprise first and second NMOS transistors, wherein each of the first and second NMOS transistors are coupled to the second node at its source.
In accordance with an embodiment of the present invention, the first source-follower further comprises a third NMOS transistor that is coupled to the first node at its source and body, that is coupled to the first supply rail at its drain, and that is configured to receive the first reference signal at its gate.
In accordance with an embodiment of the present invention, the second source-follower further comprises a third PMOS transistor that is coupled to the second node at its source and body, that is coupled to the second supply rail at its drain, and that is configured to receive the second reference signal at its gate.
In accordance with an embodiment of the present invention, the third NMOS and third PMOS transistors are depletion mode transistors.
In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus comprises a first supply rail; a second supply rail; a transmitter having: a transmit circuit; an H-bridge having: a first node; a second node; a third node; a fourth node; a first switch that is coupled between the first and third nodes and that is controlled by the transmit circuit; a second switch that is coupled between the first and fourth nodes and that is controlled by the transmit circuit; a third switch that is coupled between the second and third nodes and that is controlled by the transmit circuit; and a fourth switch that is coupled between the second and fourth nodes and that is controlled by the transmit circuit; a first source-follower that is coupled to the first node of the H-bridge, that is coupled to the first supply rail, and that is configured to receive a first reference signal; and a second source-follower that is coupled to the second node of the H-bridge, that is coupled to the second supply rail, and that is configured to receive a second reference signal; an transmission channel that is coupled to the third and fourth nodes; and a receiver that is coupled to the interconnect.
In accordance with an embodiment of the present invention, the transmit circuit further comprises: an input circuit; and a write circuit that is coupled to the input circuit and the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors.
In accordance with an embodiment of the present invention, the transmission channel further comprises an interconnect.
In accordance with an embodiment of the present invention, the receiver further comprises a magnetic head.
In accordance with an embodiment of the present invention, the write circuit further comprises a driver that is coupled to the gates of the first and second PMOS transistors and the gates of the first and second NMOS transistors.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
Turning to
One example implementation of the system 200 can be seen in
The driver 206 (which can be seen in greater detail in
Moreover, by using source-followers (i.e., transistors Q7 and Q8), the common source impedance ZOUT looking back into the H-bridge 104 is also decreased. Looking back to driver 100, impedance ZOUT,100 is:
where ZSWITCH is the switch impedance (i.e., on-resistance of one of transistors Q1 to Q4), ZCS is current source impedance, VA is the Early voltage of transistor Q5 or Q6, and ID is the drain current of transistor Q5 or Q6. This means that for an Early voltage of about 10V and a drain current ID of about 50 mA, impedance ZOUT,100 is about 200Ω (which is very high). With driver 206, the impedance ZOUT,206 is
where ZSF is source-follower impedance, W/L is the aspect ratio of transistor Q7 or Q8, COX is the oxide unit capacitance of transistor Q7 or Q8, μ is the carrier mobility, and ID is the drain current of transistor Q7 or Q8. The impedance ZOUT,206 is comparative much smaller, being about 1-5Ω with a drain current ID of about 10 mA. This lower impedance can, therefore, move the resulting parasitic pole out to a higher frequency so as to permit higher frequency operation.
To further improve performance, transistors Q7 and Q8 can be depletion mode transistors. Depletion mode devices (i.e., depletion mode NMOS or PMOS transistors) have a negative threshold voltage VT. This allows the source-followers (i.e., transistors Q7 and Q8) to achieve a maximum output swing (which, theoretically, is a dynamic range from the voltage on rail VSS plus a drain-source voltage drop across transistor Q8 to the voltage on rail VDD minus a drain-source voltage drop across transistor Q7) without having to provide reference voltage REF1 and REF2 that exceed the voltages on rails VDD and VSS (which is usually accomplished with charge pumps).
Turning to
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.