Patent Application
20070299902
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numberals refer to similar elements.
Embodiments disclosed herein generally pertain to implementations of adder circuits using sparse tree architectures having dynamic and static complementary metal oxide semiconductor (CMOS) circuits.
The generated Ling PG carry terms are then merged using a sparse carry merge scheme to generate intermediate carry terms. In the depicted embodiment, the sparse carry tree 204 comprises five intermediate carry-merge levels (CM1 to CM5) comprising carry merge gates 306A-G to 314A-G, disposed as indicated the arrows generally depict P and G term connections between the CM gates. The gates are configured to generate carry bits for every 8th bit (C7, C15 . . . C55) of the 64 bit operands.
The depicted sparse carry tree 204 uses both domino and static gates to achieve good performance and reduced power consumption. Especially in critical paths, CM gates with no more than 2-high transistor stacks are used. As indicated in the figure, with this architecture, the critical path can be made to have a delay length of only 16 RC bits. Moreover, with this architecture, a reduction in wiring complexity can occur, which permits the use of wider/shielded wires on the few performance-critical inter-stage ‘group generate/propagate’ signals.
In some embodiments, CM levels CM1, CM3, and CM5 comprise domino circuits with 2-high dynamic (e.g., footless) NMOS-stacks (represented as 2N), while levels CM2 and CM4 incorporate static gates having 2-high PMOS stacks (represented as 2P). With this configuration, the carry-merge tree has a worst-case evaluation path of 2N-2P-2N-2P-2N in order to generate the carry signals.
(The term “PMOS transistor” refers to a P-type metal oxide semiconductor field effect transistor. Likewise, “NMOS transistor” refers to an N-type metal oxide semiconductor field effect transistor. It should be appreciated that whenever the terms: “transistor”, “MOS transistor”, “NMOS transistor”, or “PMOS transistor” are used, unless otherwise expressly indicated or dictated by the nature of their use, they are being used in an exemplary manner. They encompass the different varieties of MOS devices including devices with different VTs and oxide thicknesses to mention just a few. Moreover, unless specifically referred to as MOS or the like, the term transistor can include other suitable transistor types, e.g., junction-field-effect transistors, bipolar-junction transistors, and various types of three dimensional transistors, known today or not yet developed.)
The carry bits from the sparse carry tree 204 are provided to sum generation circuits 316, which are also coupled to the input operands (A, B), to generate their sum. In some embodiments, conditional sum generation circuits are used. In this embodiment, each 8-bit sum generator is a conditional sum generator that generates conditional sums for its input carry bit being both 0 and 1 while the sparse tree circuitry calculates the carry values for every eighth bit. With this scheme, the non-criticality of the sum-generator permits the usage, for example, of a ripple carry-merge scheme to generate the conditional carries.
In some embodiments, the 8-bit operand sections and associated conditional carries are XORed together to generate conditional sums in 8-bit sections. Once arriving from the sparse tree circuitry 204, the carry bits (C7, C15, . . . C55) then select the appropriate 8-bit conditional sums, e.g., using a 2:1 multiplexer to deliver the final 64-bit sum. In this way, logic traditionally implemented in complex main carry-tree, for example, using expensive parallel prefix logic can instead be implemented in the sparse-tree design using an energy-efficient architecture. Such an approach can result in smaller area, reduced energy consumption and lower leakage.
With reference to
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
