Patent Application
20130065542
This disclosure relates to spectral transform systems that may be used, for example, as a band-pass or band-stop filter in an electrical system and to methods related to the use and manufacture of such systems.
Certain types of regenerative feedback circuits have been used for decades to increase the amplification of a signal. An example of such a circuit is disclosed in U.S. Pat. No. 1,907,653 (Muth) entitled “Short Wave Receiver”, which uses a vacuum tube and a feedback inductor to create the feedback loop.
Certain embodiments relate to an apparatus comprising a front-end circuit, that may be implemented in a monolithic integrated circuit.
Certain embodiments relate to an apparatus comprising a front-end circuit that may be implemented exclusive of a ceramic-filter or a SAW filter.
Certain embodiments relate to an apparatus for processing an electrical signal comprising a front-end circuit consisting essentially of a first path having a signal input for receiving an unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path; a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay or phase shifting element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the front end circuit. In certain embodiments, at least the delay element, the second path signal scaling block, and the first path signal scaling block are located on the same monolithic integrated circuit as the fixed gain block.
Certain embodiments relate to a monolithic integrated circuit comprising an input for receiving an electrical signal; a first path having a signal input for receiving the unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; and a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path. In certain embodiments, the monolithic integrated circuit may be configured to communicate with a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the front end circuit.
Certain embodiments relate to a transceiver implemented on a monolithic integrated circuit comprising an input for receiving an electrical signal; a first path having a signal input for receiving the unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; and a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path. In certain embodiments, the monolithic integrated circuit may be configured to communicate with a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the front end circuit.
Certain embodiments relate to a semiconductor chipset comprising a first monolithic integrated circuit, comprising an input for receiving an unfiltered signal; a first path having a signal input for receiving the unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; and a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path. The chipset further comprises a second monolithic integrated circuit comprising a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the front end circuit.
Certain embodiments relate to a method for stabilizing a regenerative feedback circuit, the method comprising: providing a controller for controlling a regenerative feedback circuit comprising a fixed gain block; an input attenuation control; a loop gain control; and a loop delay. In certain embodiments, the controller may be connected to adjust the input attenuation control, the loop gain control and the loop delay based on the properties measured by a detector to continuously monitor and control the filtering and amplifying characteristics of the circuit.
Certain embodiments relate to a method of producing a lower cost electronic device comprising providing a front-end circuit comprising a regenerative feedback circuit comprising: a fixed gain block; an input attenuation control; a loop gain control; a loop delay; and a controller connected to adjust the input attenuation control, the loop gain control and the loop delay based on the properties measured by a detector to control the filtering and amplifying characteristics of the front end circuit. In certain embodiments at least the input attenuation control, the loop gain control and the loop delay are located on the same monolithic integrated circuit as the fixed gain block.
Certain embodiments relate to a method for producing a front-end circuit on a single monolithic integrated circuit comprising fabricating a monolithic integrated circuit for filtering and amplifying an unfiltered signal, the monolithic integrated circuit comprising an input for receiving an unfiltered signal; a first path having a signal input for receiving the unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; and a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path. In certain embodiments the monolithic integrated circuit may be configured to communicate with a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the front end circuit.
Certain embodiments relate to a method for manufacturing an electronic device comprising fabricating a monolithic integrated circuit for filtering and amplifying an unfiltered signal comprising an input for receiving an unfiltered signal; a first path having a signal input for receiving the unfiltered signal, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path between the signal input and the signal output, the second path having an adjustable delay element and an adjustable second path signal scaling block; and a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path. In certain embodiments the monolithic integrated circuit may be configured to communicate with a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to control the filtering and amplifying characteristics of the electronic device. In certain embodiments the method further comprises coupling the monolithic integrated circuit directly to an input.
Certain embodiments relate to a method for processing an incoming electrical signal to obtain a desired gain and selectivity at a desired frequency using a regenerative feedback circuit located on a monolithic integrated substrate. In certain embodiments the regenerative feedback circuit comprises a fixed gain block; an input attenuation control; a loop gain control; a loop delay or phase shift; and a controller connected to adjust the input attenuation control, the loop gain control and the loop delay based on the properties measured by a detector to control the filtering and amplifying characteristics. In certain embodiments, the method comprises setting the input attenuation control to a maximum so that no signal passes through the regenerative feedback circuit; adjusting the loop gain control and the delay to the approximate desired center frequency and bandpass using a lookup table; adjusting the loop gain control to the point where the output signal just begins to show an oscillation; adjusting the delay or phase shifter such that the center frequency is more accurate; increasing the loop gain control until the oscillation is extinguished, wherein the backoff is sufficient such that the excess noise in the passband of the BPF is negligible; decreasing the input attenuation control to allow a signal to enter the system where it is amplified through the regenerative feedback loop, and monitoring the bandwidth of the output signal generated by sweeping around the central frequency to measure the width of the bandwidth.
Certain embodiments relate to a mobile telephone comprising a transmit/receive switch; a subsampling analog-to-digital converter; and a front-end circuit coupled between the transmit/receive switch and the subsampling analog-to-digital converter, for filtering and amplifying an unfiltered signal. In certain embodiments, the front-end circuit consists essentially of a regenerative feedback circuit that may be implemented exclusive of a ceramic-filter or a SAW filter.
Certain embodiments relate to a mobile telephone comprising a transmit/receive switch; a subsampling analog-to-digital converter; and a front-end circuit coupled between the transmit/receive switch and the subsampling analog-to-digital converter, for filtering and amplifying an unfiltered signal. In certain embodiments the front-end circuit consists essentially of a regenerative feedback circuit that may be implemented in a monolithic integrated circuit.
Certain embodiments relate to a mobile telephone comprising a power amplifier; and a front-end circuit, for filtering out of band noise. In certain embodiments the front-end circuit consists essentially of a regenerative feedback circuit and the power amplifier and front-end circuit are implemented in a monolithic integrated circuit.
Certain embodiments relate to a mobile telephone comprising: a transmit/receive switch; a subsampling analog-to-digital converter; and a front-end circuit coupled between the transmit/receive switch and the subsampling analog-to-digital converter, for filtering and amplifying an unfiltered signal. In certain embodiments the front-end circuit consists essentially of a regenerative feedback circuit comprising a fixed gain block; an input attenuation control; a loop gain control; a loop delay; and a controller connected to adjust the input attenuation control, the loop gain control and the loop delay based on the properties measured by a detector to control the filtering and amplifying characteristics of the front end circuit. In certain embodiments at least the input attenuation control, the loop gain control and the loop delay are located on the same monolithic integrated circuit as the fixed gain block.
Certain embodiments relate to a mobile telephone (or base station) comprising a transmit/receive switch; a power amplifier; a subsampling analog-to-digital converter; and a transceiver circuit. In certain embodiments, the transceiver circuit comprises a front-end circuit consisting essentially of at least one a regenerative feedback circuit comprising a fixed gain block; an input attenuation control; a loop gain control; and a loop delay. In certain embodiments the mobile telephone also comprises a controller connected to adjust the input attenuation control, the loop gain control and the loop delay based on the properties measured by a detector to control the filtering and amplifying characteristics of the front end circuit. In certain embodiments at least the input attenuation control, the loop gain control and the loop delay are located on the same monolithic integrated circuit as the fixed gain block.
Certain embodiments relate to a monolithic integrated circuit comprising an input for receiving an unfiltered, unamplified signal; and an output for outputting a filtered and amplified version of the input signal. In certain embodiments, the monolithic integrated circuit exhibits a bandpass frequency response with a Q value greater than 500, where the center frequency of the bandpass filter can be adjusted to multiple frequencies within a predefined range exclusive of a local oscillator.
Certain embodiments relate to a Doppler radar, comprising an oscillator for producing a predefined frequency modulation; a transmitter antenna for transmitting the predefined frequency modulation; a receiver antenna for receiving a reflection of the transmitted predefined frequency modulation; a spectral transform system for isolating the frequency of the received reflection. In certain embodiments the spectral transform system comprises a first path having a signal input, a signal output, and an adjustable first path signal scaling block; a second path connected to the first path, the second path having an adjustable delay element and an adjustable second path signal scaling block; a fixed gain block located in the first path and connected between a second path input and a second path output connected to the first path; a detector connected to the signal output for detecting properties of an output signal; and a controller connected to adjust the delay or phase shifting element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to center the spectral transform system on the received reflection. In certain embodiments the radar further comprises a receiver processor for detecting the frequency of the received reflection. In certain embodiments at least the delay element, the second path signal scaling block, and the first path signal scaling block are located on the same monolithic integrated circuit as the fixed gain block.
In certain embodiments the apparatus may be a mobile telephone. In certain embodiments the apparatus may be a cellular base station. In certain embodiments the apparatus may be a GNSS receiver. In certain embodiments the apparatus may be a wireless device. In certain embodiments the apparatus may be a wireless sensor. In certain embodiments apparatus may be a monolithic integrated receiver circuit. In certain embodiments the apparatus may be a monolithic integrated transmitter circuit. In certain embodiments the apparatus may be a monolithic integrated transceiver circuit.
In certain embodiments, the apparatus may be a monolithic integrated circuit comprising a plurality of regenerative feedback circuits. In certain embodiments, such a monolithic integrated circuit may be configured for use in a cellular base station.
In certain embodiments the apparatus further comprises a transmit/receive switch, wherein the front-end circuit may be connected to the transmit/receive switch.
In certain embodiments at least one of the first path or the second path of the regenerative feedback circuit further comprising a resonator connected to the regenerative circuit.
In certain embodiments the apparatus further comprises a power amplifier connected to at least one of the output of the regenerative feedback circuit or within the first path of the regenerative feedback circuit for amplifying an electrical signal for transmission.
In certain embodiments the regenerative feedback circuit comprises a fixed gain block; an input attenuation control; a loop gain control; a loop delay or phase shift; and a controller connected to adjust the input attenuation control, the loop gain control and the loop delay or phase shift based on the properties measured by a detector to control the filtering and amplifying characteristics of the circuit. In certain embodiments at least the input attenuation control, the loop gain control and the loop delay or phase shift are located on the same monolithic integrated circuit as the fixed gain block.
In certain embodiments the electrical signal may be encoded with digital information.
In certain embodiments the filtering and amplifying characteristics comprise the gain of the front-end and the bandwidth and center frequency selected for filtering an incoming signal.
In certain embodiments the second path may be a feedback path.
In certain embodiments the apparatus comprises multiple first paths connected to corresponding feedback paths, the first paths being connected in parallel between the signal input and the signal output.
In certain embodiments one or more of the multiple first paths further comprise a feed-forward path connected to the first path upstream from the feedback path and an output connected to the first path downstream from the feedback path; and a first path delay or phase shifting element connected between the input of the feed-forward path and an output of the feedback loop, the first path delay or phase shifting element being adjustable and connected to the controller, the controller being connected to adjust the first path delay or phase shifting element to achieve the desired signal output.
In certain embodiments the signal output of the second path comprises a signal combiner.
In certain embodiments the second path may be a feed-forward path.
In certain embodiments the regenerative feedback circuit comprises multiple first paths connected to corresponding feed-forward paths, the first paths being connected in series between the signal input and the signal output.
In certain embodiments the second path comprises a switch for switching between a feedback path and a feed-forward path configuration.
In certain embodiments the controller may be a processor that may be programmed to maintain a desired output signal.
In certain embodiments the detector may be one of a power detector, a spectrum analyzer, or combination thereof.
In certain embodiments the detector detects the signal-to-noise ratio of the signal.
In certain embodiments the first path signal scaling block may be adjusted by the controller to normalize the output signal.
In certain embodiments the first path signal scaling block comprises a block that modifies a coupling coefficient.
In certain embodiments the first path gain block may be connected to the first path between a second path input and a second path output.
In certain embodiments the first path gain block may be a variable gain amplifier.
In certain embodiments the fixed gain block may be a low noise amplifier.
In certain embodiments the apparatus further comprises a signal limiter at an input of the low noise amplifier.
In certain embodiments the detector comprises a signal processor.
In certain embodiments the signal input may be received via a coaxial cable.
In certain embodiments the signal input may be received via an antenna.
In certain embodiments the second path may be a feedback path, and an output of the feedback path may be connected to the antenna.
In certain embodiments the apparatus further comprises an antenna coupling block.
In certain embodiments the second path may be a feedback path, and the receiver further comprises a feed-forward path having an input from the first path upstream from the feedback path and an output into the first path downstream from the feedback path; and an adjustable path delay or phase shifting element connected between the input of the feed-forward path and an output of the feedback path, the path delay or phase shifting element being controlled by the controller.
In certain embodiments the second path may be connected to the first path by at least one directional coupler.
In certain embodiments the second path signal scaling block may be a block that modifies the coupling coefficient between the first path and the second path.
In certain embodiments the apparatus further comprises a signal generator that generates a predefined frequency; a first first path having a second path that may be a feed-forward path that suppresses a frequency above the predefined frequency; a second first path having a second path that may be a feed-forward path that suppresses a frequency below the predefined frequency; and first and second first paths being connected in series to the signal generator.
In certain embodiments the second path signal scaling block may be a gain block.
In certain embodiments the apparatus further comprises an up-conversion and pre-distortion stage at the signal input; and a power amplifier connected between a first path input and a first path output.
In certain embodiments the apparatus further comprises a sub-sampling ADC connected upstream of the detector, and wherein the detector comprises a signal processor.
In certain embodiments the apparatus further comprises multiple second paths connected in parallel, the delay of each second path being spaced to remove multiple harmonics of the oscillator output.
In certain embodiments the input attenuation control consists of a 0-10 dB voltage controlled attenuator. In certain embodiments the input attenuation control may be one of a 0-100 dB, 0-50 dB, 0-30 dB, 0-20 dB, 10-30 dB or 20-40 dB voltage controlled attenuator.
In certain embodiments the loop gain control consists of a 0-10 dB voltage controlled attenuator. In certain embodiments the loop gain control may be one of a 0-100 dB, 0-50 dB, 0-30 dB, 0-20 dB, 10-30 dB or 20-40 dB voltage controlled attenuator.
In certain embodiments the fixed gain block may be a low noise amplifier with about a 30 dB gain, 1 dB low noise amplifier. In certain embodiments the low noise amplifier may have a gain of about 10 db, 15 dB, 20 dB, 25 dB, 35 dB, 40 dB, 45 dB, or 50 dB.
In certain embodiments the loop delay or phase shifter may be a voltage controlled phase shifter with about a 0-360 degree phase capability. In certain embodiments, the phase shifter may be implemented as two 180 degree phase shifters or three 120 degree phase shifters, or four 90 degree phase shifters.
In certain embodiments the controller comprises a lookup table comprising settings for the input attenuation control, the loop gain control and the loop delay or phase shift to achieve a desired signal output. In certain embodiments the settings in the lookup table are predetermined. In certain embodiments the settings in the lookup table are adjusted using adaptive updating methods.
In certain embodiments the controller obtains a desired gain and selectivity at a desired frequency of the input signal by setting the input attenuation control to a maximum so that no signal passes through the regenerative feedback circuit; adjusting the loop gain control and the delay or phase shifter to the approximate desired frequency and bandpass using a lookup table; adjusting the loop gain control to the point where the output signal just begins to show an oscillation; adjusting the delay or phase shifter such that the desired frequency is more accurate; increasing the loop gain control until the oscillation is extinguished, wherein the backoff is sufficient such that the excess noise in the passband of the BPF is negligible; decreasing the input attenuation control to allow a signal to enter the system where it is amplified through the regenerative feedback loop; and monitoring the bandwidth of the output signal generated by sweeping around the desired frequency to measure the width of the bandwidth.
Certain embodiments relate to a spectral transform system, comprising a first path having a signal input, a signal output, and an adjustable first path signal scaling block. A second path may be connected to the first path. The signal input may be an antenna. The second path may have an adjustable delay element and an adjustable second path signal scaling block. A detector may be connected to the signal output for detecting properties of an output signal. A controller may be connected to adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to achieve a desired output signal.
In certain embodiments, the second path may be a feedback path or a feed-forward path, and the second path may comprise a switch for switching between a feedback path and a feed-forward path configuration. The controller may be a processor that is programmed to maintain a desired output signal. The detector may be one of a power detector, a spectrum analyzer, or combination thereof. The first path signal scaling block may be adjusted by the controller to normalize the output signal.
In certain embodiments, the first path signal scaling block and the second path signal scaling block may each comprise a gain block or a block that modifies a coupling coefficient.
In certain embodiments, the first path signal scaling block may be a gain block, which may be connected upstream of the second path or to the first path between a second path input and a second path output, and may be a variable gain amplifier. The first path may comprise a low noise amplifier connected between a second path input and a second path output. There may be a signal limiter at an input of the low noise amplifier.
In certain embodiments, the detector may comprise a signal processor. The controller may comprise a lookup table comprising settings for the delay element, the second path signal scaling block, and the first path signal scaling block related to the desired signal output. The settings in the lookup table may be predetermined. The settings in the lookup table may be adjusted using adaptive updating methods.
In certain embodiments, the signal input may be an antenna. The second path may be a feedback path, and an output of the feedback path is connected to the antenna. There may be an antenna coupling block.
In certain embodiments, the second path may be a feedback path, and the spectral transform system may further comprise a feed-forward path having an input from the first path upstream from the feedback path and an output into the first path downstream from the feedback path, and an adjustable path delay element connected between the input of the feed-forward path and an output of the feedback path, the path delay element being controlled by the controller.
In certain embodiments, there may be multiple first paths connected to corresponding feedback paths connected in parallel between the signal input and the signal output. One or more of the multiple first paths may further comprise a feed-forward path having an input from the first path upstream from the feedback path and an output into the first path downstream from the feedback path; and a first path delay element connected between the input of the feed-forward path and an output of the feedback path. The first path delay element may be adjustable and connected to the controller, the controller being connected to adjust the first path delay element to achieve the desired signal output. The signal output may comprise a signal combiner.
In certain embodiments, there may be multiple first paths connected to corresponding feed-forward paths connected in series between the signal input and the signal output. There may be multiple second paths connected in parallel, the delay of each second path being spaced to remove multiple harmonics of the oscillator output.
In certain embodiments, the second path may be connected to the first path by at least one directional coupler. The second path signal scaling block may be a block that modifies the coupling coefficient between the first path and the second path. The spectral transform system may further comprise a signal generator that generates a central frequency, a first first path having a second path that is a feed-forward path that suppresses a frequency above the central frequency, a second first path having a second path that is a feed-forward path that suppresses a frequency below the central frequency, and the first and second first paths being connected in series to the signal generator.
In certain embodiments, there may be an up-conversion and pre-distortion stage at the signal input, and a power amplifier connected between a feedback path input and a feedback path output.
In certain embodiments, there may be a sub-sampling ADC connected upstream of the detector, and the detector may comprise a signal processor.
Certain embodiments relate to a Doppler radar, comprising an oscillator for producing a constant frequency, a transmitter antenna for transmitting the constant frequency, and a receiver antenna for receiving a reflection of the transmitted constant frequency. The constant frequency may be one of an electromagnetic or acoustic signal. There may be a spectral transform system for isolating the frequency of the received reflection. as described above. The controller may adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the properties detected by the detector to center the spectral transform system on the received reflection. A receiver processor may detect the frequency of the received reflection.
Certain embodiments relate to a method of transforming a frequency spectrum, comprising providing a system as described above; providing the controller with a target signal response having a target bandwidth, a target centre frequency, and a target gain; coupling an input signal to the signal input and detecting an output signal at the signal output; comparing the output signal to the desired signal response, and causing the controller to adjust the delay element, the second path signal scaling block, and the first path signal scaling block to provide the desired signal response.
In certain embodiments, the method may further comprise the step of calibrating the system by setting the input signal to zero, and adjusting the delay element and the second path signal scaling block to arrive at the desired pole or zero in the z-plane related to the target signal response.
In certain embodiments, the controller may comprise a lookup table for a set of desired signal responses. The controller may adjust the delay element, the second path signal scaling block, and the first path signal scaling block based on the lookup table prior to comparing the output signal to the desired signal response. The lookup table may be adjusted using adaptive updating methods.
These and other features will become more apparent from the following description in which reference is made to the appended drawings, the drawings are for the purpose of illustration only and are not intended to be in any way limiting, wherein:
a and 21b depict examples of antennas connected as sum blocks.
The device described below is a filter block that may operate as a band-pass or band-stop filter that is tunable in terms of center frequency and bandwidth. It is based on a regenerative feedback loop that is electronically controlled for fast agile control of the bandwidth and center frequency of the filter. The filter block is described below primarily in terms of an electronic circuit, for example, a filter block designed for circuits operating in the microwave range of frequencies. However, it will be clear that the filter block may be implemented for other types of systems, such as optical, mechanical vibration or acoustic systems, or other systems that are frequency-based, where analogous components would be used in place of any electrical components described with respect to the examples given below. Accordingly, the device may be more broadly described as a spectral transform system, as the goal is to transform the frequency content of an input signal to a desired output signal. As will be understood from the description below, this is generally done by tuning the device to a desired center frequency and bandwidth, either as a band-pass or band-stop filter. Multiple devices may be combined in various ways to provide the desired frequency response.
As described herein, the filter block circuit may be denoted as a Regenerative Feedback Circuit (RFC). As described above, many of the terminology used below relate to electronic circuitry, however it will be recognized that analogous components may exist in other systems, such as optical, mechanical vibration or acoustic systems.
Below is a description of several components and definitions of functional blocks used in the RFC.
In this document, D denotes a delay block as illustrated in
s(t)=exp(jωt)
where j≡√{square root over (−1)} then the output of the delay block is
s(t−D)=exp(jω(t−D))=exp(jωt)exp(−jωD))=s(t)exp(−jωD)
Based on this, the equivalent operation of the delay block 12 of delay D is a phase shift of phase is −ωD (provided that the input excitation is a pure tone of frequency ω) In this document, the delay parameter will be a control parameter of the RFC. However, it should be understood that this is equivalent to a phase shift operation where the phase shift varies linearly with frequency.
In this document, G denotes a gain block that scales the input signal by a scaling factor of G, and is identified by reference numeral 14 as shown in
The finite impulse response (FIR) filter block resulting in a single transmission zero is shown in
The frequency response of the FIR filter is given as
H(ω)=1+G exp(−jωD)
such that when G=1 and ωD=π, H(w)=0 resulting in a transmission zero.
The infinite impulse response (IIR) filter block resulting in a single transmission pole is shown in
The frequency response of the IIR filter is given as
with the pole occurring at ω which satisfies
1−G exp(−jωD)=0
Note that the IIR filter shown in
The fundamental operation of the controllable RFC, identified generally by reference numeral 10, is shown in
As the gain block 14 in the feedback path has a gain between 0 and 1, it operates as an attenuator and is therefore labeled as A. The transfer function of the overall RFC 10 from the input to the output in the frequency domain is then given as
The magnitude of the signal gain through the overall RFC 10 is given as
The feedback loop 22 will influence the passband characteristic of the RFC 10. If A=0 then the RFC 10 will have a flat frequency response of |H(ω)|=G. As A is increased from 0 the response will have periodic resonance frequencies at
ωD=0, ±2π, ±4π, . . .
As A approaches 1/G the resonance peaks will become narrower and the overall gain will become infinitely high. In a practical application, one of the resonance frequencies (usually the fundamental at ωD=2π) is coincident with the frequency of the desired signal at the input. The frequency can be controlled by setting the delay D and the bandwidth can be set by setting A.
Referring to
Referring to
Instead of using the RFC circuit 10 in
H(ω)=G(1+A exp(−jDω))
which has a frequency notch at the frequencies of ωD=±π, ±3π, . . . .
For the purposes of the discussions herein, ARFC, generally identified by reference numeral 100, is defined to imply an RFC that is reconfigured as shown in
RFCs and ARFCs can be combined in parallel and series to provide arbitrary filter transfer functions consisting of multiple poles and zeros resulting in MRFC and MARFC configurations. The theory of combining poles and zeros to obtain desired filter transfer functions is known in the art, and is described, for example, in J. Proakis, D. Manolakis, “Digital Signal Processing principles, algorithms and applications”, Prentice Hall 1996, as well as other texts and articles.
An example of a compound circuit having RFC 10 and 10′, which provides two poles is given in
The RFC and the ARFC as described above are preferably used for frequency selective filtering as required in a receiver processing of narrow bandwidth electronic signals corrupted by noise and interference. The signals could be sourced from an antenna as in a wireless receiver. However, they can be sourced from a generic block generating a narrow bandwidth signal to be isolated from accompanying noise and interference sources.
The RFC and ARFC can be used to in any application where selective frequency filtering of generic signals is required. Hence, while the embodiments described herein are for electronic signals, these signals could be of mechanical vibration, acoustic or optical origin also.
In certain embodiments, the circuit described in
The controller 32 may be an embedded digital processing circuit, a microcontroller, a FPGA, etc. as is known in the art. The A and D controls 12 and 14 are as described before, namely providing control of the position of the pole of the RFC 10. Ain 28 provides control of the overall throughput gain of the circuit in
The controller 32 can be implemented as a digital signal processing unit as shown in
In certain embodiments, such as that of
The RFC unit 10 in
In certain embodiments, the procedure to obtain the maximum gain, and hence the maximum selectivity at a particular frequency whether received through an antenna or directly may be as follows:
1. Start by setting the Attenuator 28, to maximum so that no signal 16 passes through the RFC.
2. Adjust D and A to the desired BPF center frequency location via a LUT, for example. This will be approximate as the components change with temperature, aging etc. Adjust A (reduce attenuation) to the point where the output just begins to show an oscillation. The frequency of the oscillation should correspond approximately to the desired center frequency of the BPF. Adjust D (increase delay will lower frequency, decrease delay will increase frequency) such that the center frequency is accurate. Then increase the attenuation of A until the oscillation is extinguished. The backoff should be sufficient such that the excess noise in the passband of the BPF is negligible. This also creates a suitable ‘safety margin’ against spurious oscillations. Slowly decrease the attenuation at 28 and allow weak signal 16 to enter the system where it is amplified through the RFC loop
3. Monitor the bandwidth of the output signal generated by sweeping a few kHz around the central frequency to measure the width of the bandwidth, do so in another simple algorithm that detects when the bandwidth starts to expand, stop the attenuator 28 and it is at this point that the sensitivity and selectivity of the weak signal is at its highest.
4. By modifying the level of the attenuation at 14, it is possible to change the bandwidth and hence the amplitude. While changing the phase at D and the attenuation at A one can change the bandwidth and frequency of the signal respectively. Also 28 can change the overall gain of the BPF (in conjunction with 14).
In certain embodiments, the iterative algorithm (IA) may start by increasing the voltage of the attenuator A slowly till it reaches a maximum, while the Phase Shifter D is set to 0 deg. This output amplitude is that of the noise generated from the LNA 25. When a maximum is reached D is increased or decreased till that noise amplitude reaches a new maximum. Then attenuator A is increased or decreased till that noise amplitude reaches a new maximum. This is then followed by the same procedure but using the Phase shifter D and so on until just short of oscillation occurring, this can be detected in various forms, and if the oscillation occurs, a previous step can be taken back. Once a maximum has been reached, the system is ready for use.
Basic Single Element Filter Unit with Antenna Feedback
The RFC 10 requires feedback to the input of the circuit, which may be accomplished with an antenna, as shown in
In order to provide the desired frequency response, Ain, A and D for each RFC 10 or ARFC 100 block are controlled. The method of controlling Ain, A and D to obtain the desired response will now be given. To simplify the explanation, Ain, A and D will refer to the controls of a single RFC. However, the control processing described is applicable for multiple RFC units operating in parallel or for ARFC units. It is therefore convenient to define FB, indicated by reference numeral 110, as the overall filter block which comprised an arbitrary set of RFCs and ARFCs with control inputs of Ain, A and D where each of Ain, A and D can be a vector of control inputs, where the actual design of FB 110 depends on the desired filter response. That is, if there are a total of M RFC and ARFC units then there are M individual controls of D required. In this case D is assumed to consist of M control parameter elements. The FB 110 is shown in
Control of Ain
Ain is determined by comparing Ptot to a given threshold denoted as λPtot. If Ptot>λPtot then Ain is decreased to reduce the input gain. If Ptot<λPtot then Ain is increased to increase the input gain. Conventional methods of applying an appropriate control of Ain are used.
Control of A and D
It is assumed that the delay and gain units 12 and 14 controlled by the D and A parameters respectively are well behaved components in a circuit sense. This implies that the parameters of D and A provide an approximate monotonic control of the delay and gain functions with no discontinuities. It also implies that the resulting values of the delay and gain as a function of the D and A control inputs can be predetermined and the response curves can be stored in a look up table in the controller block. Hence the D and A controls can be set based on the calibration information stored in the lookup table to set the transmission poles of the RFCs 10 or the transmission zeros of the ARFCs 100. This lookup table will be denoted as LUT_AD.
Consequently, the desired frequency response of the FB can be mapped into the required transmission poles and zeros of the RFC 10 and ARFC 100 units respectively. Using the calibration LUT_AD, these poles and zeros can be mapped into A and D parameters that are passed onto the FB 110. The calibration required to fill the LUT_AD can be determined by conventional means of using a standard network analyzer to determine the mapping between the transmission poles and zeros and the A and D values.
It is recognized that the values of the LUT_AD will not be exact due to circuit aging, change in temperature and so forth. However it will be assumed that the values will remain approximately correct over a given time span between calibrations. The small errors will have to be corrected for as the FB unit is operating. A possible set of run time calibration corrections is given below for the RFC 10.
For the RFC 10 the following steps may be taken:
For the ARFC the following steps may be taken:
A modification to this run time calibration can be to provide a frequency signal from a synthesizer source that is connected with the parameter controller block as shown in
For the ARFC calibration, it is necessary to use the scheme in
The FB 110 may be used as part of a superheterodyne receiver architecture or one that is directly sub-sampled. In either case, the baseband signal is digitized and used for further processing. Hence, there is no additional hardware required to implement a spectrum analyzer functionality at baseband. Presumably the baseband processor can accumulate N samples with a sampling rate of fsmp. The discrete Fourier Transform DFT of these N samples results in a measurement of the frequency spectrum with a frequency resolution of fsmp/N. For the application of the RFC tuning of D, the frequency corresponding to the peak can be fed back to the controller 32 shown in
A variant of the scheme in
For the FB 110, it is necessary to maximize Pf(fo) at a particular frequency fo by varying D as stated beforehand. Various methods can be used for this. One way is to compute the numerical gradient of Pf(fo) and then vary D appropriately until the gradient is zero corresponding to the maximum. Another way is to consider that the processor 116 of
For the FB based on the ARFC it is necessary to minimize Pf(fo) at a particular frequency fo which involves optimizing values of both A and D. As the solution based on the LUT_AD is assumed to be reasonably close to the actual optimum point, a gradient search would be the fastest approach. The process will be to sample the I(fo) and Q(fo) outputs separately at three operating points with different values of A and D. The objective is to determine the two dimensional gradient at the current operating point denoted by {A0,D0} and then apply a Newton Raphson (NR) iteration at that operating point to find the next iteration. Steps are as follows:
dI
—
dA=(I1−I0)/ΔA
dI
—
dD=(I2−I0)/ΔD
dQ
—
dA=(Q1−Q0)/ΔA
dQ
—
dD=(Q2−Q0)/ΔD
The optional factor α is a scaling that is set between 0 and 1. The functions I0(A, D) and Q0(A, D) are fairly smooth surfaces. Consequently, the NR method will quickly converge in a few iterations.
In some cases the manifold surface changes abruptly or there is an inflection point which causes the NR iteration to diverge instead of converge. This should not be a problem if the initial point {A0,D0} is sufficiently close. However, check both |I| and |Q| or I2+Q2 to ensure that they have decreased in value after each NR iteration.
It is also necessary to state a tolerance for the final I2+Q2 or set a fixed number of NR iterations.
Optionally, if I and Q are not available then the power detector of
The gradient search based on Ptot would consist of the following steps:
A0→A1 if G1<G0 and G1<G2
D0→D2 if G2<G0 and G2<G1
Initially ΔA and ΔD can be of moderate size. However, after several iterations, it will be determined that A0 and D0 are no longer changed in which case ΔA and ΔD are decreased by a factor of 2. This continues until ΔA and ΔD are on the order of the resolution of the DACs driving the A and D blocks.
Note that dynamic changes to A0 and D0 show up as an effective broadening of the passband or a phase/amplitude noise modulation of the passband signal with is undesirable. Hence there should be a facility for freezing the tracking such that the signal qualities can then be measured.
Next consider the FB based on the RFC for which it is necessary to maximize Pf(fo) at a particular frequency fo by varying A and D. As discussed before it is assumed that Ain is set by a separate loop such that Pf(fo) is close to the threshold set. While A and D are being optimized Ain has to be held at a constant level. Hence the steps are as follows:
Based on the optimization of the RFC based FB 110 as discussed in the previous sections, FB 110 may be used in different ways.
In a number of applications there is a requirement for a narrow bandwidth channelizer that can operate over a broad frequency range. The combination of the FB and a subharmonic sampling block 118 and subsequent processing provides for a means of implementing a broad bandwidth channelizer as shown in
The sampling rate of the subharmonic ADC is at fsmp which is assumed to be higher than the instantaneous bandwidth of the channelizer. As the subharmonic ADC 118 aliases the frequency components of mfsmp where m is an integer, it is necessary that the bandwidth of the FB 110 be smaller than fsmp. The processing consists of a DFT of N sequential samples such that the components of
can be isolated and undergo further processing.
The channelizer can be periodically calibrated based on a synthesizer output coupled through a switch into the FB as shown in
The main embodiment is shown in
The controller consists of two algorithms as defined in
There are a number of variations that could also be used. The components shown in
The power sensor (PS) 30a has more complex variability. One possibility is that the PS 30a is a simple wideband power detector based on a nonlinear component such as a diode. This will give the controller 32 a measurement of the power level of the output signal. The PS 30a can also be a narrow bandwidth sensor which is based on demodulation of the signal. This is shown in
Instead of a signal processing block 116, the RFC 10 may incorporate a controller 32 based on a pre-calibrated lookup table (LUT). Here the inputs {B, F, G} are mapped into the G,A,D parameter outputs based on a multi-dimensional digital LUT. The digital outputs of the LUT are converted to analog controls required for G,A,D via a set of DACs (Digital to Analog Convertors). The LUT is either filled with calibration values for the individual RFC at the time of manufacture, prior to every usage or can be adjusted based on adaptive updating methods. Such techniques are numerous and diverse, and are well known in the art. This embodiment may encompass all of the relevant, known algorithms and methods for filling, updating and maintaining such a LUT in the context of the embodiment shown in
Referring to
While a radio frequency application has been described here, the antenna SB implementation could be a sensor for optical signals or mechanical vibration with a commensurate feedback transducer. For instance the SB could be a microphone with an electrical signal output. The feedback could either be a mechanical transducer that feeds back to the microphone or it could be added as an electrical signal to the microphone. The latter would be closer to the circuit in
Referring to
Referring to
Referring to
Referring to
As mentioned previously, the RFC may be implemented using a directional coupler 140, which is shown in
Referring to
Also shown in
Referring to
Alternatively, the structure shown in
Consider the first path and constrain the electrical length to be one half wavelength such that N1=1. The electrical length is therefore π radians through this feedback loop. If the gain of the amplifier in the loop is −1 then the circuit with a single feedback path will oscillate at the frequency corresponding to the electrical length being π radians.
Consider the first path and constrain the electrical length to be one wavelength such that N1=2. The electrical length is therefore 2π radians through this feedback loop. If the gain of the amplifier in the loop is 1 then the circuit with a single feedback path will oscillate at the frequency corresponding to the electrical length being 2π radians.
An issue is that the active gain stage in the loop will generate some harmonic distortion. The p1 loop will have resonant frequencies at multiples of the intended oscillation frequency which will significantly increase the harmonic output of the oscillator.
Now consider a circuit with two parallel feedback loops. The first feedback loop has a constraint of N1=2 and a loop gain of 1. The second loop has a constraint N2=1 and a loop scaling of −1. The combination of these two paths is such that the frequency corresponding to an electrical length of 2π through p1 will also have a phase of 2π through p2 such that the oscillator will operate at this equivalent frequency but the same feedback network will not pass the second harmonic of this frequency. It can be shown that the combined feedback will have a null at all of the even order harmonics of this oscillation frequency.
Suppose p3 is added with N1=3, N2=2 and N3=1 then, with suitable gain coefficients of each of the pm branches, it is possible to suppress the second and third harmonic in addition to the 5th and 6th harmonic and so fourth.
In general if M feedback loops are used with Nm=M−m+1 then the harmonics of 0, 2, 3, . . . , M−1 will be suppressed. The Mth harmonic will be the first that will create an harmonic content issue.
Referring to
Alternatively, referring to
Alternatively, referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Adjusting the controls of the RFC provides a means of realizing a frequency filtering sub-circuit that may have the following properties:
Based on these properties, the RFC can be used in any microwave receiver application where the instantaneous signal bandwidth is small relative to the carrier frequency. An example of this is shown in
The RFC can be used to replace narrow bandwidth microwave bandpass filters. Highly selective bandpass filters at microwave frequencies are generally bulky and have a limited range of tuning. The RFC provides a physically small solution to this implementation problem with a tunable Q and center frequency.
The RFC can simplify the implementation of an image rejection mixer. A typical image rejection mixer can provide up to 20 dB of relative image band suppression while the RFC can provide up to 60 dB. Further, the typical bulky image rejection mixer is avoided.
The RFC can implement a highly selective highly agile microwave bandpass filter which is useful in numerous applications such as frequency hopping radar systems and communication receivers.
In the case of a GPS system, GPS receivers require low noise RF front ends with high selectivity to remove out of band interference signals. The RFC can provide suppression of up to 60 dB (e.g., 40 dB, 50 dB, 45 dB, 60 dB, etc.) of out of band signals. This simplifies the development of a standard heterodyne receiver as the linearity requirements of the down conversion stage can be relaxed since the potentially large out of band signals have been removed by the RFC. Also in the superheterodyne context, the RFC dispenses with the requirement for an image rejection mixer. The RFC can also be effectively used in a zero IF implementation of the GPS receiver. The typical issues with second order nonlinearities are reduced with the RFC implementation due to the high selectivity of the RFC. The same comments would be applicable for any generic GNSS receiver.
Terrestrial wireless receivers as those in typical cellular handsets are prone to interference from large signals in the vicinity of the desired passband signal. The RFC's high selectivity is effective in suppressing these out of band signals. This reduces the linearity requirements of the receiver down conversion and IF stages, potentially resulting in a less expensive and lower power consumption receiver implementation.
Typical frequency agile or frequency hopping radars are subject to unintentional as well as hostile jamming. As a result, highly frequency selective receiver front ends are required to suppress the interference signals. The RFC can be electronically tuned to perfectly track the instantaneous signal bandwidth of the frequency hopping radar signal with very high selectivity.
There is a potential application of the RFC for very low noise microwave amplifiers as required in more esoteric areas such as radio astronomy. The RFC could be implemented with the LNA for the realization of a tunable, highly frequency selective extremely low noise amplifier with a noise figure as low as 0.2 dB (e.g., 0.1 dB, 0.15 dB, 0.2 dB, 0.25 dB, 0.3 dB, 0.35 dB etc.) without the requirement of cryogenic cooling.
The fast electronic tunability of the RFC provides opportunities for adaptive receiver applications. Feedback from the output receiver processing can be conveniently linked back to the RFC to realize various forms of adaptive filter implementations.
The high selectivity of the RFC suggests that the intermediate frequency filtering used in a standard superheterodyne receiver is not required. A simplified architecture for a wireless receiver is then as shown in
The typical GNSS receiver (of which the GPS is a common example) consists of a superheterodyne structure where the bandwidth of the receiver is progressively narrowed as the signal passes through the receiver. In addition the filtering becomes more selective in terms of suppressing out of band interference signal components. A generic block diagram of this prior art implementation is shown in
An integration implementation issue with this type of receiver is the requirement of the two local oscillator blocks as well as the ceramic and SAW (surface acoustic wave) filters. It is generally necessary to implement these components off the main processing chip adding to the cost and size of the overall circuit. In addition off chip components reduces the reliability of the receiver.
The GPS receiver implementation based on the RFC is shown in
A multiband GNSS receiver simultaneously processes the signals from various GNSS satellites and potentially pseudo-lite sources. The circuit in
The typical wireless transceiver as found in a cellular telephone is based on a circuit structure as shown in
Superheterodyne (SH) receivers appear ubiquitously in cell phones, GPS receiver and wireless sensor devices. The entire SH receiver is tightly integrated on a mixed signal ASIC that is inexpensive to fabricate, robust and has performance close to the theoretical optimal bound. Monolithically integrated multiband SH receivers have also been created that have enabled highly complex multi-function transceivers currently developed by a multitude of handset manufactures around the globe.
However, the sheer volume of such receivers that are currently being manufactured for a variety of applications is staggering. As of 2007 there was already 1 mobile phone per every two inhabitants worldwide. With an average lifespan of 2 years this results in the current rate of several billion mobile devices per year being manufactured. In addition, GPS is experiencing a similar exponential growth rate in terms of the number of deployed receivers used by the general public and military. Recently, due to the near negligible cost of the RF receiver, there has been an explosive development in the area of wireless sensor and telemetry devices. Predictions are that the number of wireless sensors will soon dwarf the aggregate of mobile and GPS receivers currently deployed.
Such large volumes provides incentives for technology advancements cost reductions of the wireless receiver. Hence competing architectures to the SH are mounting. During the past decade the zero IF and near zero IF architectures have been extensively researched and engineered resulting in further cost reductions of the wireless receiver. The wireless receiver discussed herein (the RFC) provides for further potential cost reductions. In certain embodiments, the RFC eliminates several filtering components required in the other architectures that need to reside off-chip.
The integration of the RFC can be achieved monolithically on a mixed signal ASIC. A possible two chip implementation is shown in
Note that the mixed signal ASIC does not require any off-chip components except for the quartz crystal which is necessary for any wireless receiver to generate sufficiently stable timing signals. The ASIC has a single RF analog input and a set of digital IO lines. The connection from the PCON to the mixed signal ASIC is a set of PWM digital lines and are not analog.
This exemplary two chip receiver implementation is standard and that there is no additional hardware complexity resulting from the RFC based architecture. In fact the RFC implementation makes the ASIC simpler in that off-chip SAW and ceramic filters are not required.
Regarding the internal ASIC circuitry, the SH implementation requires a synthesizer for the RF LO and the IF LO. It also requires the downconversion mixers. Careful design is necessary in order to avoid LO frequency spurs in the desired passband. As well the two downconversion mixers are inherently nonlinear and are a source of intermodulation distortion which limits the instantaneous dynamic range of the receiver. The RFC on the other hand is linear and therefore the dynamic range is potentially larger.
The RFC may require a sub-sampling ADC which can sample the narrow bandwidth signal at the carrier frequency but the sampling rate only has to be approximately equal to the signal bandwidth. Hence the sampling rate is potentially no different than that of the SH solution. Therefore the DSP involved in demodulation of the desired signal may be the same for the RFC and the SH. However, the high carrier frequency at the ADC input implies that a fast Sample and Hold (S&H) processing block may be placed prior to the ADC. Such S&H devices are currently available for analog signals beyond 20 GHz. Hence sampling of wireless signals below 6 GHz is certainly feasible. However there may be a challenge in realizing a S&H circuit that is of sufficiently low power consumption for the wireless application. In the meantime there is an alternative solution that gets around the problem of a suitable low power S&H. The solution is is based on a RFC with a zero IF solution as shown in
Another possible solution which avoids the S&H of
In certain embodiments, the RFC implementation results in a simpler receiver ASIC that may avoid off chip filtering components. The operation of the RFC may be somewhat more complex than the traditional SH implementation as the RFC parameters may need to be continually updated to mitigate drift issues. However, the demodulation processing typically performed in wireless receivers generates the signal amplitude and signal SNR measurements that are sufficient observables for controlling the RFC and maintaining optimal tracking of the desired signal. Hence, in certain embodiments, no additional computationally intensive processing is required to support the RFC. In certain embodiments, the processing required in the PCON is relatively low speed and easily absorbed into the processing already performed in the microprocessor.
In certain embodiments, there may be a potential realization complexity of sub sampling ADC required. However, this issue may be reduced by the following:
As discussed previously, the RFC has application in the implementation of the transceiver of the cellular phone. In certain embodiments, the RFC can eliminate various components of the traditional phone that are not possible to include in the main transceiver integrated circuit such as the duplexor and the SAW filter. The RFC provides a narrow bandpass filter commensurate with the bandwidth of the desired RF cellular signal that is to be demodulated eliminating the need for further analog filtering (RF and IF filtering in a superheterodyne architecture, RF and baseband filtering in a zero IF architecture). The output of the RFC filter can be input directly into a subsampling ADC with a sampling rate equal to the bandwidth of the RFC filter. The output stream of discrete time samples of the ADC output in certain implementations is further processed with DSP (digital signal processing) and then the encoded voice/data signal can be extracted and demodulated for use in the application layer of the cell phone.
The prior art receiver design based on frequency translation requires an accurate synthesizer to generate the appropriate local oscillator (LO) signals. These LO's are derived from a fixed temperature compensated quartz crystal oscillator. The small frequency errors of the LO's are generally compensated for directly in the DSP processing such that the analog portion is fixed. In some earlier implementations, the frequency of the quartz crystal oscillator could be adjusted over a small range (+−50 ppm) based on feedback from the signal demodulation. This is based on the frequency error being recognizable in the demodulated signal output which provided input to a frequency locking loop that controlled the exact frequency of the quartz crystal oscillator with a varactor diode coupled with the crystal circuit.
In the RFC implementation, the parameters may include:
These are set such that the RFC can realize the required center frequency, bandwidth and throughput gain to optimally select the desired cellular signal band. Examples would be for CDMA IS2000 a bandwidth of 1.2 MHz to about 5 MHz is required centered at the carrier frequency. GSM which is about 200 kHz but with frequency hopping. To facilitate the notation the following three attributes of the RFC bandpass filter response can be defined:
Setting these parameters (for the cell phone signal demodulation) is generally difficult due to the high gain and high Q filter response required. (Q in this context refers to the ratio of the center frequency of the band pass filter to its bandwidth). For the IS2000 CDMA signal in a PCS band (F˜1900 MHz, B˜1 MHz), a Q of about 2000 is needed. Furthermore, the signal can be as small as −120 dBm which will require a gain of over 100 dB between the antenna and the ADC input. Furthermore this gain has to be tightly controlled to stay within the dynamic range of the ADC. For example if a 4 bit ADC is used then the amplitude control of G has to range over 70 dB with an accuracy of 1 dB.
A higher order ADC would relax this specification but this would significantly inflate the power consumption of the ADC operation as well as the expense of integrating this component.
A receiver based on the RFC architecture can provide the same signal selectivity and noise figure performance as a superheterodyne architecture. In certain embodiments, an advantage of the RFC (in the cell phone context) is a savings in terms of implementation. This is based on the possibility of implementing the RFC monolithically without the need of external parts as is required for prior art designs. This can map into significant savings in this high volume market.
An exemplary RFC circuit in the cellular phone context is shown in
Although the embodiments above describe an antenna coupled to a receiver (e.g., an RFC) as illustrated in
In some embodiments, the antenna may be a yagi antenna and the resulting configuration may be as shown in
In some embodiments, the antenna may be an active antenna.
The PCON comprises various processing blocks and algorithms to facilitate the functionality required for the cell phone application. Exemplary embodiments of these components and algorithms are described below.
Ideally, if the components of the regenerative loop are perfectly stable such that G, F, B maps exactly into Ain, A, D via an open loop calculation done by the PCON then no corrective feedback from the DSP would be required. In this case the setting of G, F, B can be done with a LUT where the addressing of the LUT entry is based on the F, B, G input. F and B come directly from the application layer. G will have to still come from the DSP block. Hence the procedure, which is illustrated in
As observed F and B are open loop parameters set by the application layer through the PCON and the G attribute is set iteratively based on a gain control loop. There are numerous variations for this gain control depending on the propagation environment. For example, an indoor environment may change much slower than an outdoor environment (e.g., driving on the freeway through an urban corridor type environment). The phone can track the signal fluctuations and determine how quickly it needs to respond.
In a frequency hopping application where F changes according to a known pseudo random sequence every few milliseconds, the LUT entry will be accurate and can be used open loop. Say a GSM signal is tracked by the receiver where F is continually hopped in this fashion. Then the LUT entry may need to be used open loop as there may not be any time for further adaptation. However, the LUT entries can optionally be adapted over a longer term by noting errors after each frequency hop. Minor incremental adjustments can be done to the table over the use of several minutes.
Also in the prior art is the use of a temperature sensor which can be integrated together with the LUT. The address of the LUT is then determined from the F, B, G attributes as well as the temperature output of the co-located sensor.
An additional output of the DSP which is generally computed as part of the normal physical layer functionality of the cell phone is the estimation of the signal to noise ratio (SNR) of the demodulated signal. This is used by the phone to determine if and when to handoff to the next base station. Typically the SNR estimates generated by the cell phone are transmitted back to the base station which facilitates these network based decisions.
It can therefore be assumed that such generated SNR measurements are available to the PCON without further processing required. In certain embodiments, an objective of the PCON is to optimize the SNR by dithering the parameters of Ain, A, D of the regenerative loop. In particular the center frequency and bandwidth of the regenerative loop are sensitive to A and D. Hence the objective is to optimize A and D for a given F and B corresponding to the desired signal by maximizing SNR. The optimized A and D values can then be used to refine the LUT.
A challenge with the monolithically integrated RFC implementation in the cell phone application is that of a robust cold start algorithm. This is where the RFC circuits are initially turned on and the LUT entries are not of sufficient accuracy to map B F G into the parameters Ain, A, D. The LUT is used to set up the initial guess, but a fast robust refinement is required to demodulate the desired signal. Here two modes may be possible which are described below. The first mode is direct but it may not be successful if the tolerances of the monolithic integration are not commensurate with the accuracy requirements of the RFC.
The optimization is convex in the neighborhood of the ideal setting of A D and Ain with SNR as the optimization objective and hence this fine convergence step is straight forward and can be implemented by several well known methods. The simplest method is to adjust one parameter at a time as follows: 1) Maximize SNR with A and D fixed and Ain variable. 2) Maximize SNR with A and Ain fixed and D variable. 3) Maximize SNR with Ain and D fixed and A variable. A faster method is to determine the gradient of SNR relative to the three variables of A, D and Ain. Then take a step along the maximum gradient direction and repeat. The partial derivatives required for this method are determined numerically by small dithering steps.
Another innovative feature is the estimation of the frequency of the RFC oscillation based on selecting two ADC sampling frequencies derivable from the crystal oscillator. Consider that the RFC oscillation frequency in the range of 100 MHz to 2 GHz. The sampling frequencies for the ADC are 2.017 MHz and 2.013 MHz selected for this example arbitrarily. Other pairs of frequencies are also possible. First the aliased frequencies that show up in the sampled output are
f
1=mod(fin,2.017)
f
2=mod(fin,2.013)
The processing computes the sets of possible input frequencies as
f
in,1
=f
1
+i2.0017
f
in,2
=f
2
+j2.0131
where i and j are integers. From these two sets we find frequencies that are common within 1 kHz. The 1 kHz range is due to the assumption of a 1 msec observation time of the ADC output samples.
The estimation of the SNR may be highly dependent on the structure of the modulation of the desired signal. One example is for IS2000 CDMA where the pilot signals are demodulated and a SNR is estimated based on the set of pilot signals used and the number of significant multipath components that are demodulated. Fortunately all of this processing is already implemented as part of the necessary CDMA signal demodulation with no additional processing components required to facilitate the SNR estimate as required for the RFC. One issue could be that the estimate of the SNR is generally averaged over a longer time constant than is necessary for the RFC cold start and tracking processes. However, the pilot signal estimates are available which are updated on the order of several milliseconds commensurate with the time constant associated with the fastest fluctuating multipath that the receiver is likely to experience.
These pilot signal estimates are easily combined to provide an appropriate metric suitably equivalent to the desired SNR metric.
Other modulation schemes contained in WiFi, WiMAX and 802.11 variants all have some form of embedded pilot signal from which the SNR can be appropriately estimated. GSM uses a segment of pilot within the transmitted signal burst. In cases where the wireless signal does not use pilot signals there are other means of estimating the SNR. Decision feedback can be used where the SNR is determined based on the variations of the signal relative to the expected (noise free) signal.
As shown in
As shown in
In some embodiments, the RFC may also be used to improve the performance of a resonator. A typical narrowband receiver with a resonator circuit is illustrated in
In some embodiments, the RFC may also be used in conjunction with bi-directional filters. An example of such a use is depicted in
In the circuit for
In some embodiments, the RFC may also be used in conjunction with oscillators (e.g., ultra stable oscillators). An example of such a use is depicted in
Accordingly, the RFC can be used in the above oscillator structure in which two feedback loops pass through a common resonator. As described above, one loop acts as a higher power pump oscillator with an amplitude limiting action where the frequency control is provided by the RFC. The other loop is a low power loop with the gain stage in the loop operating on small signal levels well within the linear range of the amplifier. Hence a highly linear output response is generated with this circuit.
In this patent document, the word “comprising” is used in its non-limiting sense to mean that items following the word are included, but items not specifically mentioned are not excluded. A reference to an element by the indefinite article “a” does not exclude the possibility that more than one of the element is present, unless the context clearly requires that there be one and only one of the elements.
The following claims are to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, and what can be obviously substituted. Those skilled in the art will appreciate that various adaptations and modifications of the described embodiments can be configured without departing from the scope of the claims. The illustrated embodiments have been set forth only as examples and should not be taken as limiting the invention. It is to be understood that, within the scope of the following claims, the invention may be practiced other than as specifically illustrated and described.
This application claims the benefit of priority from U.S. Provisional Application No. 61/282,463, filed Feb. 16, 2010, and U.S. Provisional Application No. 61/344,702, filed Sep. 16, 2010. The foregoing related applications, in their entirety, are incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US11/24963 | 2/16/2011 | WO | 00 | 11/27/2012 |
| Number | Date | Country | |
|---|---|---|---|
| 61282463 | Feb 2010 | US | |
| 61344702 | Sep 2010 | US |
