Patent Application
20150106666
Various embodiments of the present invention provide systems and methods for speculatively calculating bit error rate during decoding.
Various data processing systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In such systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. As information is stored and transmitted in the form of digital data, errors are introduced that, if not corrected, can corrupt the data and render the information unusable. The effectiveness of any transfer is impacted by any losses in data caused by various factors. Data can be encoded before transmission or storage, for example adding parity bits. The retrieved data can then be decoded to detect and correct errors.
Some embodiments of the present invention provide an apparatus for calculating a speculative bit error rate, comprising a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder.
This summary provides only a general outline of some embodiments according to the present invention. Many other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components.
Embodiments of the present invention are related to speculatively calculating bit error rate during decoding. The speculative bit error rate calculation disclosed herein is performed as data is iteratively decoded, based on the decoded data, also referred to herein as hard decisions, that are generated and updated as the data is decoded. With each decoding iteration, the decoded data is updated and can be changed as errors are detected and corrected. The speculative bit error rate is also updated during this process, using delta values or differences detected from one decoding iteration to the next. The bit error rate is thus made available immediately or soon after decoding converges on stable or correct values, or after the maximum number of decoding iterations have been performed and decoding is terminated. In this manner, the bit error rate is calculated without waiting for decoding to be completed and stored. In some embodiments, this saves a codeword or more of latency by calculating the bit error rate in the decoding stage rather than the output stage of the decoding pipeline.
Turning to
Speculative bit error rate calculation is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.
In some embodiments, the data decoding algorithm can be but is not limited to, a low density parity check decoding algorithm as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoding algorithms that may be used in relation to different embodiments of the present invention. A low density parity check code is defined by a sparse parity check matrix H of size m×n, where m<n. A codeword c of length n satisfies all the m parity check equations defined by H, i.e., cHT=0, where 0 is a zero vector. Decoder convergence is checked by determining whether the syndrome s=cHT is all zero, where the syndrome is a vector of length m, with each bit corresponding to a parity check. A zero bit in a syndrome means the check is satisfied, while a non-zero bit in the syndrome is an unsatisfied check (USC). By definition, a codeword has syndrome s=0. A non-codeword has a non-zero syndrome.
In some embodiments, the data decoding algorithm is a layered quasi-cyclic low density parity check decoding algorithm, in which the parity check matrix H is divided into layers, and the codeword is decoded layer by layer. In some of these embodiments, data can converge and decoding can be finished as a layer is decoded partway through a decoding iteration, without having to complete decoding of all layers in the parity check matrix H. Speculative bit error rate calculation can be completed in these embodiments as soon as data converges, also without having to complete decoding of all layers in the parity check matrix H.
Effectively, the speculative bit error rate calculation is performed while processing each of the layers in the decoder 114. The bit error rate is tabulated and retained layer by layer, iteration by iteration in the speculative bit error rate calculator 126. As each layer is decoded, the delta value is calculated and accumulated by layer, retaining the values so that the bit error rate can be speculatively accumulated. If the decoder converges, the total accumulated value based on the deltas will be used as the final bit error rate for the decoded data. By performing this delta accumulation, the speculative bit error rate calculator 126 can generate the total bit error rate at the decoding stage 104 rather than waiting until the final output stage 106 to calculate the bit error rate.
In embodiments in which the decoder 114 is a non-layer decoder, the deltas are calculated iteration by iteration as the decoding process progresses, without differentiating by layer. In some of these embodiments, convergence is not detected until the end of a decoding iteration, and the speculative bit error rate calculation is performed at the end of each decoding iteration.
Turning to
Data 202 to be decoded is received and stored in received data memory 204. In some embodiments, the data 202 to be decoded comprises data encoded using a low density parity check encoding algorithm. In some embodiments, the data to be decoded is obtained as soft decisions, also referred to as soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a bit or symbol has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. In some embodiments, the data to be decoded is obtained directly or indirectly from a data detector that applies a data detection algorithm to sampled data from an analog to digital converter. In some embodiments, the data detection algorithm can be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention.
The received data 206 is provided to data decoder 210, which applies a data decoding algorithm to received data 206 to yield decoded data 212. (Although the data decoder 210 is shown as part of the speculative bit error rate calculator 200, in various embodiments the data decoder 210 and speculative bit error rate calculator 200 can be separate elements or considered separate elements of an overall apparatus.) it can be either included In some embodiments, the decoder is a low density parity check decoding algorithm as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoding algorithms that may be used in relation to different embodiments of the present invention. The decoded data 212 is stored in a decoded data memory 214 before being provided at output 216 after convergence or termination of failed decoding.
An array of XOR gates 220, also referred to herein as a failed expectation detector, detects differences between the decoded data 212 and the received data 206, yielding bit error signal 222. In some embodiments, the decoder 210 is a quasi-cyclic low density parity check decoder, processing 128-bit wide circulant sub-matrices of the parity check matrix H. In some of these embodiments, the decoded data 212 is 128 bits wide, and the array of XOR gates 220 includes 128 XOR gates, each comparing one bit of the 128 bits of decoded data 212 with a corresponding bit of the received data 206. The bit error signal 222 then contains 128 bits in unary notation, each with a value of 1 when their corresponding bit of decoded data 212 and received data 206 are different. However, the decoded data 212 is not limited to a bit width of 128 bits. In non-layered embodiments, the decoded data 212 can correspond to other portions of a codeword, up to and including an entire codeword.
A per iteration bit error rate calculator 224 counts the number of failed expectations, based on the number of 1's in bit error signal 222, yielding a per layer bit error rate, also referred to herein as a failed expectation count 226. In some embodiments, the failed expectation count 226 is represented as a 7-bit binary number with a maximum value of 128, in the case in which all 128 bits of decoded data 212 differ from the corresponding 128 bits of received data 206. The bit error rate calculator 224 can include any suitable circuit for counting the number of 1's in bit error signal 222 or otherwise generating a failed expectation count 226. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of counting circuits that may be used in bit error rate calculator 224 in relation to different embodiments of the present invention.
A delta calculator 234 calculates the difference between the failed expectation count 226 calculated in the current decoding iteration and that calculated in the previous decoding iteration as stored in a bit error rate register 230. For the first decoding iteration, the bit error rate register 230 is initialized at zero. In embodiments with a layered decoder 210, the bit error rate register 230 is divided by layer, and is operable to store the previous iteration failed expectation count 226 for each layer.
In some embodiments, the delta calculator 234 is operable to subtract the failed expectation count 226 for the current iteration from the bit error rate calculator 224 from the failed expectation count 232 for the previous iteration from the bit error rate register 230, yielding delta value 236. The delta calculator 234 can contain any suitable circuit for calculating the difference between the failed expectation count 226 and previous iteration failed expectation count 232, such as, but not limited to, a subtraction circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of delta calculator circuits that may be used in relation to different embodiments of the present invention.
A total bit error rate accumulator 240 is initialized at zero at the beginning of a decoding operation, and is updated each time a delta value 236 is calculated. In some embodiments, the total bit error rate accumulator 240 is updated by subtracting the delta value 236 from the contents of the total bit error rate accumulator 240 and storing the result in the total bit error rate accumulator 240. In other embodiments, the total bit error rate accumulator 240 is updated by adding the delta value 236 from the contents of the total bit error rate accumulator 240 and storing the result in the total bit error rate accumulator 240, and then taking the absolute value of the contents of the total bit error rate accumulator 240 after decoding converges.
Once decoding converges, or when the maximum number of decoding iterations have been performed, the contents of the total bit error rate accumulator 240 are output as the final bit error rate 242.
As an example, assume that the data 202 to be decoded contains 8 erroneous bits. If in the first decoding iteration the decoded data 212 differs from the received data 206 by 5 bits, such as if 5 of the 8 erroneous bits were corrected during decoding, the bit error signal 222 will contain 5 bits with a value of 1. The failed expectation count 226 will be 5. The delta calculator 234 subtracts 5 (failed expectation count 226) from 0 (the initial value of the failed expectation count 232 stored in bit error rate register 230), yielding a delta value of −5. The delta value of −5 is subtracted from 0, the initial value in the total bit error rate accumulator 240, and the result is stored in the accumulator 240 for a total speculative bit error rate value of 5. The failed expectation count 226 of 5 is stored in bit error rate register 230 for the next decoding iteration.
If in the second decoding iteration the decoded data 212 differs from the received data 206 by 7 bits, such as if 2 more of the 8 erroneous bits were corrected during the second decoding iteration, the bit error signal 222 will contain 7 bits with a value of 1. The failed expectation count 226 will be 7. The delta calculator 234 subtracts 7 (failed expectation count 226) from 5 (the previous iteration failed expectation count 232), yielding a delta value of −2. The delta value of −2 is subtracted from 5, the value in the total bit error rate accumulator 240, and the result is stored in the accumulator 240 for a total speculative bit error rate value of 7. The failed expectation count 226 of 7 is stored in bit error rate register 230 for the next decoding iteration.
If in the third decoding iteration the decoded data 212 differs from the received data 206 by 6 bits, such as if one of the previously corrected bits fluctuates back to the incorrect value, the bit error signal 222 will contain 6 bits with a value of 1. The failed expectation count 226 will be 6. The delta calculator 234 subtracts 6 (failed expectation count 226) from 7 (the previous iteration failed expectation count 232), yielding a delta value of 1. The delta value of 1 is subtracted from 7, the value in the total bit error rate accumulator 240, and the result is stored in the accumulator 240 for a total speculative bit error rate value of 6. The failed expectation count 226 of 6 is stored in bit error rate register 230 for the next decoding iteration.
If in the fourth decoding iteration the decoded data 212 differs from the received data 206 by 8 bits, such as if all erroneous bits have been corrected, the bit error signal 222 will contain 8 bits with a value of 1. The failed expectation count 226 will be 8. The delta calculator 234 subtracts 8 (failed expectation count 226) from 6 (the previous iteration failed expectation count 232), yielding a delta value of −2. The delta value of −2 is subtracted from 6, the value in the total bit error rate accumulator 240, and the result is stored in the accumulator 240 for a total speculative bit error rate value of 8. If all data has converged in the decoder, the value of 8 in the accumulator 240 is output as the total bit error rate.
Turning to
Data 302 to be decoded is received and stored in received data memory 304. In some embodiments, the data 302 to be decoded comprises data encoded using a low density parity check encoding algorithm. In some embodiments, the data to be decoded is obtained as soft decisions, also referred to as soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a bit or symbol has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. In some embodiments, the data to be decoded is obtained directly or indirectly from a data detector that applies a data detection algorithm to sampled data from an analog to digital converter. In some embodiments, the data detection algorithm can be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention.
The received data 306 is provided to data decoder 310, which applies a data decoding algorithm to received data 306 to yield decoded data 312. In some embodiments, the decoder is a quasi-cyclic layered low density parity check decoding algorithm as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoding algorithms that may be used in relation to different embodiments of the present invention. The decoded data 312 is stored in a decoded data memory 314 before being provided at output 316 after convergence or termination of failed decoding.
A failed expectation detector for detecting a first type of error (expected 1, received 0) includes an array of inverters 348 and AND gates 344. AND gates 344 compare bits in decoded data 312 with inverted copies 346 of corresponding bits in received data 306, inverted in inverters 348, yielding type 1 bit error signal 350. A failed expectation detector for detecting a second type of error (expected 0, received 1) includes an array of inverters 354 and AND gates 352. AND gates 352 compare bits in decoded data 312 with inverted copies 356 of corresponding bits in received data 306, inverted in inverters 354, yielding type 2 bit error signal 356. In some embodiments, the decoder 310 is a quasi-cyclic low density parity check decoder, processing 128-bit wide circulant sub-matrices of the parity check matrix H. In some of these embodiments, the decoded data 312 is 128 bits wide, and the type 1 bit error signal 350 and type 2 bit error signal 356 are each 128 bits wide, with the type 1 bit error signal 350 containing a high bit for each instance of a type 1 (expected 1, received 0) error, and with the type 2 bit error signal 356 containing a high bit for each instance of a type 2 (expected 0, received 1) error.
A bit error rate calculator 360 counts the number of each type of error or failed expectation, based on the number of 1's in bit error signals 350 and 356, yielding per layer bit error rates for each type of error, also referred to herein as a failed expectation count 362. In some embodiments, the failed expectation count 362 is represented as a pair of 7-bit binary numbers each with a maximum value of 128, and where the combined count of both types of errors would have a maximum value of 128. The bit error rate calculator 360 can include any suitable circuit for counting the number of 1's in bit error signals 350 and 356 or otherwise generating a failed expectation count 362. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of counting circuits that may be used in bit error rate calculator 360 in relation to different embodiments of the present invention.
An array of bit error rate layer registers 364, 368, 372 is provided to store the failed expectation counts 362 for each layer. In some embodiments, one bit error rate layer register 364, 368, 372 is provided for each layer of the parity check matrix H, each containing a 7-bit count of both types of errors. The bit error rate layer registers 364, 368, 372 are initialized with a value of 0 for both types of errors at the beginning of a decoding operation.
A delta calculator 380 calculates the difference between the current layer failed expectation counts 362 calculated in the current decoding iteration and that calculated in the previous decoding iteration as stored in bit error rate layer registers 364, 368, 372. The previous iteration failed expectation counts 366, 370, 374 for the current layer are selected by multiplexer 376 and provided as current layer previous iteration failed expectation count 378 to the delta calculator 380.
The delta calculator 334 is operable to subtract the current layer current iteration failed expectation count 362 from the current layer previous iteration failed expectation count 378, yielding delta value 382. The delta value 382 contains a count of the difference in the number of each type of error between the current decoding iteration and the previous decoding iteration. The delta calculator 380 can contain any suitable circuit for calculating the difference between the counts 362, 378, such as, but not limited to, a subtraction circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of delta calculator circuits that may be used in relation to different embodiments of the present invention.
A total bit error rate accumulator 384 is initialized at zero at the beginning of a decoding operation, and is updated each time a delta value 382 is calculated. In some embodiments, the total bit error rate accumulator 384 is updated by subtracting the delta value 382 for each type of error from the contents of the total bit error rate accumulator 384 for that type of error and storing the result in the total bit error rate accumulator 384. In other embodiments, the total bit error rate accumulator 384 is updated by adding the delta value 382 for each type of error from the contents of the total bit error rate accumulator 384 for that type of error and storing the result in the total bit error rate accumulator 384, and then taking the absolute values of the contents of the total bit error rate accumulator 384 after decoding converges. The total bit error rate accumulator 384 thus contains a total count of the number of type 1 (expected 1, received 0) errors, and a total count of the number of type 2 (expected 0, received 1) errors. The total bit error rate for each type of error can be added before output, and can thus provide as output 386 both the total bit error rate for all types of errors, and the total bit error rate for each different type of error.
As an example, assume that the data 302 to be decoded contains 4 erroneous bits, 3 of type 1 (expected 1, received 0), and 1 of type 2 (expected 0, received 1). For simplicity, only errors in the first layer are considered in this example. If in the first decoding iteration the layer 1 decoded data 312 differs from the received data 306 by 2 bits for type 1 and 1 bit for type 2, such as if 2 of the type 1 errors and the single type 2 error were corrected during decoding, the type 1 bit error signal 350 will contain 2 bits with a value of 1 and the type 2 bit error signal 356 will contain 1 bit with a value of 1. The failed expectation count 362 will be 2 for type 1 and 1 for type 2. The delta calculator 380 subtracts 2 (the type 1 current layer current iteration failed expectation count 362) from 0 (the initial value of the type 1 current layer failed expectation count in layer register 364), yielding a type 1 delta value of −2. The delta value of −2 is subtracted from 0, the initial type 1 value in the total bit error rate accumulator 384, and the result is stored in the accumulator 384 for a total speculative type 1 bit error rate value of 2. The type 1 failed expectation count 362 of 2 is stored in layer register 364 for the next decoding iteration. The delta calculator 380 subtracts 1 (the type 2 current layer current iteration failed expectation count 362) from 0 (the initial value of the type 2 current layer failed expectation count in layer register 364), yielding a type 2 delta value of −1. The delta value of −1 is subtracted from 0, the initial type 2 value in the total bit error rate accumulator 384, and the result is stored in the accumulator 384 for a total speculative type 2 bit error rate value of 1. The type 2 failed expectation count 362 of 1 is stored in layer register 364 for the next decoding iteration. Again, the speculative bit error rate calculation for other layers in the first decoding iteration is omitted from consideration for simplicity.
If in the second decoding iteration the layer 1 decoded data 312 differs from the received data 306 by 3 bits for type 1 and 1 bit for type 2, such as if all errors were corrected during decoding, the type 1 bit error signal 350 will contain 3 bits with a value of 1 and the type 2 bit error signal 356 will contain 1 bit with a value of 1. The failed expectation count 362 will be 3 for type 1 and 1 for type 2. The delta calculator 380 subtracts 3 (the type 1 current layer current iteration failed expectation count 362) from 2 (the previous iteration type 1 count in layer register 364), yielding a type 1 delta value of −1. The delta value of −1 is subtracted from 2, the type 1 value in the total bit error rate accumulator 384, and the result is stored in the accumulator 384 for a total speculative type 1 bit error rate value of 3. The type 1 failed expectation count 362 of 3 is stored in layer register 364 for the next decoding iteration. The delta calculator 380 subtracts 1 (the type 2 current layer current iteration failed expectation count 362) from 1 (the previous iteration type 2 count in layer register 364), yielding a type 2 delta value of 0. The delta value of 0 is subtracted from 0, the previous type 2 value in the total bit error rate accumulator 384, and the result is stored in the accumulator 384, leaving an unchanged total speculative type 2 bit error rate value of 1. The type 2 failed expectation count 362 of 1 is stored in layer register 364 for the next decoding iteration.
In some embodiments, if all data has converged in the decoder, the type 1 value of 3 in the accumulator 384 is output as the total type 1 bit error rate, the type 2 value of 1 in the accumulator 384 is output as the total type 2 bit error rate, and the two are added and output to yield a total bit error rate of 4.
Turning to
Following flow diagram 400, data to be decoded is received. (Block 402) The data to be decoded is not limited to any particular format or source. In some embodiments, the data to be decoded comprises data encoded using a low density parity check encoding algorithm. In some embodiments, the data to be decoded is obtained as soft decisions, also referred to as soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a bit or symbol has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. In some embodiments, the data to be decoded is obtained directly or indirectly from a data detector that applies a data detection algorithm to sampled data from an analog to digital converter. In some embodiments, the data detection algorithm can be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention.
A total bit error rate accumulator and layer registers are initialized to zero at the beginning of the speculative bit error rate calculation and the decoding process. (Block 404) The current layer is decoded to yield hard decisions, also referred to herein as decoded data. (Block 406) The bit error rate for the current layer is calculated based on the received data and the hard decisions. (Block 410) In some embodiments, the bit error rate is calculated by detecting and counting the differences between the received data and the hard decisions. In some embodiments, the bit error rate calculation distinguishes between different types of errors, such as, but not limited to, an error in which a bit value of 0 was expected but a 1 was received, and an error in which a bit value of 1 was expected but a 0 was received. This is a speculative bit error rate calculation, because the data may not have converged at this point, and the hard decisions may not be the final, correct values.
A delta value for the layer is calculated based on the bit error rate just calculated and the stored bit error rate from the layer for the current layer. (Block 412) The stored bit error rate is either the initial value just calculated, if in the first decoding iteration, or the bit error rate calculated for the layer in the previous decoding iteration. In some embodiments, the delta value is calculated by subtracting the bit error rate just calculated from the bit error rate from the layer register, in other words, by subtracting the layer bit error rate from the current iteration from the layer bit error rate from the previous iteration. The total bit error rate accumulator is updated with the delta value. (Block 414) In some embodiments, this is accomplished by subtracting the delta value from the value in the accumulator and storing the result in the accumulator.
A determination is made as to whether the data has converged in the decoder. (Block 416) Notably, in a layer decoder, this can occur after decoding of any layer, making the decoded codeword and corresponding bit error rate available partway through a decoding iteration, without having to complete all the layers in the iteration. If the data has converged (or if the maximum number of iterations has been reached), the total bit error rate in the accumulator is reported. (Block 420) Otherwise, the decoding and speculative bit error rate calculation process continues. (Block 406) As hard decisions are changed during the decoding process, the total bit error rate value in the accumulator will change accordingly, updating the speculatively calculated bit error rate as the decoding progresses. This enables the correct bit error rate to be provided as soon as decoding has converged and the bit error rate delta update has been performed for the last layer that resulted in convergence.
Turning to
In a typical read operation, read/write head assembly 520 is accurately positioned by motor controller 512 over a desired data track on disk platter 516. Motor controller 512 both positions read/write head assembly 520 in relation to disk platter 516 and drives spindle motor 514 by moving read/write head assembly 520 to the proper data track on disk platter 516 under the direction of hard disk controller 510. Spindle motor 514 spins disk platter 516 at a determined spin rate (RPMs). Once read/write head assembly 520 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 516 are sensed by read/write head assembly 520 as disk platter 516 is rotated by spindle motor 514. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 516. This minute analog signal is transferred from read/write head assembly 520 to read channel circuit 502 via preamplifier 504. Preamplifier 504 is operable to amplify the minute analog signals accessed from disk platter 516. In turn, read channel circuit 502 digitizes and decodes the received analog signal to recreate the information originally written to disk platter 516. This data is provided as read data 522 to a receiving circuit. While processing the read data, read channel circuit 502 decodes the read data to detect and correct errors. A speculative bit error rate calculator speculatively calculates the bit error rate as the data is decoded, without having to wait for the decoding to complete. Such speculative bit error rate calculation can be implemented consistent with the disclosure above in relation to
It should be noted that storage system 500 can be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such storage system 500, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.
In addition, it should be noted that storage system 500 can be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter 516. This solid state memory may be used in parallel to disk platter 516 to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit 502. Alternatively, the solid state memory can be used as a cache where it offers faster access time than that offered by disk platter 516. In such a case, the solid state memory can be disposed between interface controller 506 and read channel circuit 502 where it operates as a pass through to disk platter 516 when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter 516 and a solid state memory.
Turning to
Turning to
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, embodiments of the present invention provide novel systems, devices, methods and arrangements for speculative bit error rate calculation during decoding. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of embodiments of the invention which are encompassed by the appended claims.
The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/889,527, entitled “Speculative Bit Error Rate Calculator”, and filed Oct. 10, 2013 by Hubris et al, the entirety of which is incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61889527 | Oct 2013 | US |
