Claims
- 1. A method of performing a conditional subtract instruction of a first number and a second number, said method comprising:
loading said first number in a first register; left-shifting said second number by M-bits to generate a shifted second number, wherein M represents a number of bits in said first number; shifting said first register to the left by one bit to generate a shifted register value; subtracting said shifted second number from said shifted register value to generate a temporary value; adding a 1 to said temporary value and storing a result of said adding in said first register if said temporary value is greater than or equal to zero; and shifting said first register to the left by one bit if said temporary value is less than zero.
- 2. The method of claim 1, wherein said first number and said second number respectively represent a dividend and a divisor of a division operation, and said left-shifting, said shifting said first register, said subtracting, said adding and said shifting are performed a plurality of times to perform said division operation.
- 3. The method of claim 2, wherein each of said divisor and said dividend comprises an N-bit number and an arithmetic logic unit (ALU) performing said subtracting operates using 2N bits, wherein N is a positive integer.
- 4. The method of claim 3, wherein said shifting said first register comprises storing said shifted register value in said first register.
- 5. The method of claim 3, wherein said first register comprises an accumulator.
- 6. The method of claim 2, wherein said divisor comprises an N-bit number, and an ALU operates using N-bits, wherein said first register comprises a second register and a third register, each containing N-bits, wherein said loading comprises loading said divisor in said third register and initializing said second register to zero, wherein said shifting comprises shifting the combined second register and third register by one bit position, wherein M=0, wherein said adding comprises adding a 1 to said third register after said shifting and wherein said shifted register value comprises value in said second register.
- 7. The method of claim 6, wherein said dividend also comprises an N-bit number.
- 8. The method of claim 6, wherein dividend comprises a 2N-bit number, said method further comprising:
performing in a first stage said division operation using higher N-bits of said dividend and said divisor to generate a higher bits of quotient and a first remainder, wherein said higher bits are obtained in said third register and said first remainder is obtained in said second register; performing in a second stage said division operation after storing lower N-bits of said quotient in said third register and leaving said first remainder in said second register; and performing said adding of claim 1 if the most significant bit of said second register is determined to equal 1 also.
- 9. The method of claim 8, wherein said second register comprises an accumulator.
- 10. A system comprising:
a memory storing an instruction representing an operation of a first number and a second number; and a processor coupled to said memory, said processor receiving said instruction and executing said instruction, said processor comprising:
means for loading said first number in a first register; means for left-shifting said second number by M-bits to generate a shifted second number, wherein M represents a number of bits in said first number; means for shifting said first register to the left by one bit to generate a shifted register value; means for subtracting said shifted second number from said shifted register value to generate a temporary value; means for adding a 1 to said temporary value and storing a result of said adding in said first register if said temporary value is greater than or equal to zero; and means for shifting said first register to the left by one bit if said temporary value is less than zero.
- 11. The invention of claim 10, wherein said system comprises a computer system, said memory comprises a random access memory, and said system further comprises at least one peripheral and a display controller.
- 12. The system of claim 11, wherein said first number and said second number respectively represent a dividend and a divisor of a division operation, an shifting by said means for left-shifting, shifting by said means for shifting, subtracting by said means, and adding by said means for adding are performed a plurality of times to perform said division operation.
- 13. The system of claim 12, wherein each of said divisor and said dividend comprises an N-bit number and said means for subtracting is comprised in an arithmetic logic unit (ALU) of 2N bits, wherein N is a positive integer.
- 14. The system of claim 13, wherein said means for shifting said first register storing said shifted register value in said first register.
- 15. The system of claim 13, wherein said first register comprises an accumulator.
- 16. The system of claim 12, wherein said divisor comprises an N-bit number, and an ALU operates using N-bits, wherein said first register comprises a second register and a third register, each containing N-bits, wherein said means for loading loads said divisor in said third register and initializes said second register to zero, wherein said means for shifting shifts the combined second register and third register by one bit position, wherein M=0, wherein said means for adding adds a 1 to said third register after said shifting and wherein said shifted register value comprises value in said second register.
- 17. The system of claim 16, wherein said dividend also comprises an N-bit number.
- 18. The system of claim 16, wherein dividend comprises a 2N-bit number, said system further comprising:
means for performing in a first stage said division operation using higher N-bits of said dividend and said divisor to generate a higher bits of quotient and a first remainder, wherein said higher bits are obtained in said third register and said first remainder is obtained in said second register; means for performing in a second stage said division operation after storing lower N-bits of said quotient in said third register and leaving said first remainder in said second register; and means for performing said adding of claim 10 if the most significant bit of said second register is determined to equal 1 also.
- 19. The system of claim 18, wherein said second register comprises an accumulator.
- 20. A circuit performing an instruction on a first number and a second number, said circuit comprising:
a first register receiving and storing said first number; a first shifter left-shifting said second number by M bits to generate a shifted second number, wherein M represents a number of bits in said first number; a second shifter shifting said first register to the left by one bit to generate a shifted register value; an arithmetic logic unit (ALU) subtracting said shifted second number from said shifted register value to generate a temporary value; and a control logic storing (said temporary value +1) in said first register if said temporary value is greater than or equal to zero, said control logic shifting said first register to the left by one bit if said temporary value is less than zero.
- 21. The circuit of claim 20, wherein said first number and said second number respectively represent a dividend and a divisor of a division operation, and shifting by said first shifter, shifting by said second shifter, subtracting by said ALU, and storing by said control logic are performed a plurality of times to perform said division operation.
- 22. The circuit of claim 21, wherein each of said divisor and said dividend comprises an N-bit number and said ALU performing said subtracting operates using 2N bits, wherein N is a positive integer.
- 23. The circuit of claim 22, further comprising:
an OR gate replacing a least significant bit of said temporary value with a 1 to generate an OR output comprising N-bits; and a multiplexor selecting either said shifted selected value or said OR output under the control of said control logic, wherein the selected value is stored in said first register.
- 24. The circuit of claim 22, wherein said first register comprises an accumulator.
- 25. The circuit of claim 21, wherein said divisor comprises an N-bit number, and said ALU operates using N-bits, wherein said first register comprises an accumulator and a P-register, each containing N-bits, wherein said divisor is loaded in said P-register and said accumulator is initialized to zero before beginning said division operation, wherein the combined accumulator and P-register are shifted by one bit position, wherein said ALU subtracts said shifted divisor from said accumulator such that M=0, wherein said control logic cause a 1 to be added to said P-register after said shifting and wherein said shifted register value comprises value in said accumulator.
- 26. The circuit of claim 25, wherein said dividend also comprises an N-bit number.
- 27. The circuit of claim 25, wherein dividend comprises a 2N-bit number and said circuit performs in a first stage said division operation using higher N-bits of said dividend and said divisor to generate a higher bits of quotient and a first remainder, wherein said higher bits are obtained in said P-register and said first remainder is obtained in said accumulator,
said circuit further performing in a second stage said division operation after storing lower N-bits of said quotient in said P-register and leaving said first remainder in said accumulator, wherein said control logic stores said temporary value in said first register and then adds a 1 to said first register if the most significant bit of said accumulator is determined to equal 1 also.
- 28. The circuit of claim 26, further comprising a second multiplexor for selecting either a 0 or a 1 as an output, wherein said output is provided as a carry-in bit to said P-register, said 1 being provided to add 1 and 0 being provided for a shift operation only.
- 29. A processor performing an instruction on a first number and a second number, said processor comprising:
an instruction fetch/decode unit fetching said instruction on a bus and examining said instruction; a circuit coupled to said instruction fetch/decode unit, said circuit executing said instruction, said circuit comprising:
a first register receiving and storing said first number; a first shifter left-shifting said second number by M bits to generate a shifted second number, wherein M represents a number of bits in said first number; a second shifter shifting said first register to the left by one bit to generate a shifted register value; an arithmetic logic unit (ALU) subtracting said shifted second number from said shifted register value to generate a temporary value; and a control logic storing (said temporary value+1) in said first register if said temporary value is greater than or equal to zero, said control logic shifting said first register to the left by one bit if said temporary value is less than zero.
- 30. The processor of claim 29, wherein said first number and said second number respectively represent a dividend and a divisor of a division operation, and shifting by said first shifter, shifting by said second shifter, subtracting by said ALU, and storing by said control logic are performed a plurality of times to perform said division operation.
- 31. The processor of claim 30, wherein each of said divisor and said dividend comprises an N-bit number and said ALU performing said subtracting operates using 2N bits, wherein N is a positive integer.
- 32. The processor of claim 31, further comprising:
an OR gate replacing a least significant bit of said temporary value with a 1 to generate an OR output comprising N-bits; and a multiplexor selecting either said shifted selected value or said OR output under the control of said control logic, wherein the selected value is stored in said first register.
- 33. The processor of claim 31, wherein said first register comprises an accumulator.
- 34. The processor of claim 30, wherein said divisor comprises an N-bit number, and said ALU operates using N-bits, wherein said first register comprises an accumulator and a P-register, each containing N-bits, wherein said divisor is loaded in said P-register and said accumulator is initialized to zero before beginning said division operation, wherein the combined accumulator and P-register are shifted by one bit position, wherein said ALU subtracts said shifted divisor from said accumulator such that M=0, wherein said control logic cause a 1 to be added to said P-register after said shifting and wherein said shifted register value comprises value in said accumulator.
- 35. The processor of claim 34, wherein said dividend also comprises an N-bit number.
- 36. The processor of claim 34, wherein dividend comprises a 2N-bit number and said circuit performs in a first stage said division operation using higher N-bits of said dividend and said divisor to generate a higher bits of quotient and a first remainder, wherein said higher bits are obtained in said P-register and said first remainder is obtained in said accumulator,
said circuit further performing in a second stage said division operation after storing lower N-bits of said quotient in said P-register and leaving said first remainder in said accumulator, wherein said control logic stores said temporary value in said first register and then adds a 1 to said first register if the most significant bit of said accumulator is determined to equal 1 also.
- 37. The processor of claim 35, further comprising a second multiplexor for selecting either a 0 or a 1 as an output, wherein said output is provided as a carry-in bit to said P-register, said 1 being provided to add 1 and 0 being provided for a shift operation only.
- 38. The invention of claim 37, wherein said processor comprises a central processing unit.
RELATED APPLICATION(S)
[0001] The present application is related to and claims priority from the co-pending U.S. Provisional Patent Application Serial No. 60/312,375, entitled, “Improving the Speed of Execution of a Conditional Subtract Instruction and Increasing the Range of Operands over Which the Instruction Would Be Performed Correctly”, filed on Aug. 16, 2001, and is incorporated in its entirety herewith.
Provisional Applications (1)
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Number |
Date |
Country |
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60312375 |
Aug 2001 |
US |