The invention relates to a display device, and particularly relates to a splicing display device.
Splicing display device is a commonly used technology for large-area display requirements, where multiple panels are combined in a splicing manner to achieve a large-area display effect. However, in a process of displaying images by using a conventional splicing display device, there are often obvious differences in display quality between images displayed on different panels. As a result, the splicing display effect is not good.
The invention is directed to a splicing display device, which is adapted to provide a good splicing display effect.
An embodiment of the invention provides a splicing display device including a control board, a first panel and a second panel. The control board includes an output terminal. The first panel includes a first gate driving unit, a first signal line, a first bypass line, and a second bypass line. The first panel is coupled to the output terminal. The second panel includes a second gate driving unit. The second panel is coupled to the first panel. The first panel and the second panel are disposed in a same column. The control board provides a first signal and a second signal to the first panel through the output terminal. The first signal is transmitted to the first gate driving unit through the first signal line, and is transmitted to the second panel through the first bypass line. The second signal is transmitted to the second gate driving unit through the second bypass line.
Based on the above description, the splicing display device of the disclosure may provide signals to the first panel and the second panel through the same control board, thereby reducing the difference in display quality.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Certain terms are used throughout the specification of the disclosure and the appended claims to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may probably use different names to refer to the same components. This specification is not intended to distinguish between components that have the same function but different names. In the following specification and claims, the terms “containing”, “including”, etc., are open terms, so that they should be interpreted as meaning of “including but not limited to . . . ”.
In some embodiments of the disclosure, terms related to bonding and connection, such as “connect”, “interconnect”, etc., unless specifically defined, may refer to that two structures are in direct contact, or that two structures are not in direct contact, and other structures are located between these two structures. The terms related to bonding and connection may also include situations that both of the two structures are movable or both of the two structures are fixed. In addition, the terms “electrical connection” and “coupling” include any direct and indirect electrical connection means.
The ordinal numbers used in the specification and claims, such as “first”, “second”, etc., are used to modify the components, and they do not imply or represent the, or these, components have any previous ordinal numbers, nor do they represent the order of a certain component and another component, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name. The same terms may not be used in the claims and the specification. Accordingly, a first component in the specification may be a second component in the claims. It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, reorganized, and mixed without departing from the spirit of the disclosure to complete other embodiments.
It should be noted that in the following embodiments, under the premise of not departing from the spirit of the disclosure, the features in several different embodiments may be replaced, reorganized, and mixed to complete other embodiments. As long as the features of the embodiments do not violate or conflict with the spirit of the invention, they may be mixed and matched arbitrarily.
A splicing display device of the disclosure may include a touch display device, a curved display device, or a non-rectangular display device, but the disclosure is not limited thereto. A plurality of panels spliced by the splicing display device may include, for example, panels of liquid crystal, light emitting diodes (LED), quantum dots (QD), fluorescence, phosphor, other suitable materials, or a combination of the above materials, but the disclosure is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (OLED), a mini LED, a micro LED, a quantum dot light emitting diode (QLED or QDLED), or other suitable materials, and the materials may be arranged and combined arbitrarily, but the disclosure is not limited thereto.
In the embodiment, the first panel 120 may also be configured with a first signal line (not shown), a first bypass line (not shown), and a second bypass line (not shown). The control board 110 may provide the first signal and the second signal to the first panel 120 through the output terminal 111. In the first panel 120, the first signal may be transmitted to the first gate driving unit 121 through the first signal line, and transmitted to the second panel 130 through the first bypass line. In the first panel 120, the second signal may be transmitted to the second panel 130 through the second bypass line. A signal line (not shown) may also be configured in the second panel 130 to transmit the second signal to the second gate driving unit 131. Therefore, the first panel 120 and the second panel 130 of the embodiment may receive the start pulse signal provided by the same control board 110, so that the first panel 120 and the second panel 130 may have consistent display quality, and may provide good splicing display effect. However, the arrangement of the aforementioned signal lines and bypass lines will be further described in the following multiple embodiments.
In the embodiment, the panels A1 to A3 are respectively coupled to the panels B1 to B3 through cables 221 to 223. The panels A1 to A3 may respectively transmit a plurality of start pulse signals and data signals used for driving the panels B1 to B3, C1 to C3, and D1 to D3 to the panels B1 to B3 through a plurality of bypass lines in the panels A1 to A3 and the cables 221 to 223. In this regard, the panels B1 to B3 may respectively perform display driving based on the corresponding start pulse signals and data signals.
In the embodiment, the panels B1 to B3 are respectively coupled to the panels C1 to C3 through cables 231 to 233. The panels B1 to B3 may respectively transmit a plurality of start pulse signals and data signals used for driving the panels C1 to C3, and D1 to D3 to the panels C1 to C3 through a plurality of bypass lines in the panels B1 to B3 and the cables 231 to 233. In this regard, the panels C1 to C3 may respectively perform display driving based on the corresponding start pulse signals and data signals.
In the embodiment, the panels C1 to C3 are respectively coupled to the panels D1 to D3 through cables 241 to 243. The panels C1 to C3 may respectively transmit a plurality of start pulse signals and data signals used for driving the panels D1 to D3 to the panels D1 to D3 through a plurality of bypass lines in the panels C1 to C3 and the cables 241 to 243. In this regard, the panels D1 to D3 may respectively perform display driving based on the corresponding start pulse signals and data signals.
In the embodiment, compared to the pins F12 to F14, the pin R11 is disposed to be closest to the pin F11. Compared to the pins F11, F13, and F14, the pin R12 is disposed to be closest to the pin F12. Compared to the pins F11, F12, and F14, the pin R13 is disposed to be closest to the pin F13. Compared to the pins F11 to F13, the pin R14 is disposed to be closest to the pin F14. It should be noted that “a certain pin is disposed to be closest to another pin” may refer to that the certain pin is closest to the another pin in space or on a reference plane. In addition, the number of the panels and pins in the figure of the disclosure is only an example, in fact, the number of the panels and pins is not limited thereto.
In the embodiment, the pins F11 to F14 of the panel A1 may respectively receive start pulse signals STV1 to STV4 from the cable 211, and the panel A1 further receives the data signal DA from the cable 211. The start pulse signals STV1 and STV2 may be the first signal and the second signal of the aforementioned embodiment. The pins F11 to F14 of the panel A1 are respectively coupled to the pins R11 to R14 through the bypass lines BP11 to BP14. The pin F11 of the panel A1 is further coupled to the multi-stage gate driving unit GD1. The multi-stage gate driving unit GD1 may include a plurality of gate driving units GD11 to GD1n, where n is a positive integer. In the embodiment, the pins F11 to F14 and the pins R11 to R14 are respectively arranged in sequence in a same direction, and are respectively disposed on a first side and a second side of the panel A1. As shown in
In the embodiment, the pins F11 to F14 respectively transfer the corresponding start pulse signals STV1 to STV4 to the corresponding pins R11 to R14 through the bypass lines BP11 to BP14. The gate driving unit GD11 is coupled to the pin F11 through the signal line OP11 to receive the start pulse signal STV1. The gate driving unit GD11 may generate a scan signal SC11 and an operation signal (for example, a lighting signal, not shown in the figure) according to the start pulse signal STV1. The gate driving unit GD11 may transmit the scan signal SC11 to a display pixel circuit of the panel A1, and the gate driving unit GD11 may transmit the scan signal SC11 and the operation signal to the gate driving unit GD12 of a next stage to drive the gate driving unit GD12 to generate a corresponding scan signal SC12 and an operation signal according to the scan signal SC11 and the operation signal provided by the gate driving unit GD11 of the previous stage, and successively provide the scan signal SC12 and the operation signal to the gate driving unit GD13 of the next stage. Deduced by analogy, the gate driving unit GD1n may receive the scan signal and the operation signal provided by the gate driving unit of the previous stage, and generate a corresponding scan signal SC1n. Therefore, the panel A1 may drive a plurality of display pixels of a pixel array in the panel A1 according to the plurality of scan signals SC11 to SC1n generated by the gate driving units GD11 to GD1n and the data signal DA, so that the panel A1 may display a corresponding image through the pixel array.
In the embodiment, the panel B1 may be spliced to one side of the panel A1 close to the pins R11 to R14. In the embodiment, the pins F21 to F24 and the pins R21 to R24 are respectively arranged in sequence in the same direction, and are respectively disposed on a first side and a second side of the panel B1, where the first side of the second panel is disposed to be closest to the second side of the first panel, and the first side and the second side of the second panel may be opposite sides. In the embodiment, compared to the pins R12 to R14, the pin F21 is disposed to be closest to the pin R11. Compared to the pins R11, R13, and R14, the pin F22 is disposed to be closest to the pin R12. Compared to the pins R11, R12, and R14, the pin F23 is disposed to be closest to the pin R13. Compared to the pins R11 to R13, the pin F24 is disposed to be closest to the pin R14. In the embodiment, compared to the pins F22 to F24, the pin R21 is disposed to be closest to the pin F21. Compared to the pins F21, F23, and F24, the pin R22 is disposed to be closest to the pin F22. Compared to the pins F21, F22, and F24, the pin R23 is disposed to be closest to the pin F23. Compared to the pins F21 to F23, the pin R24 is disposed to be closest to the pin F24.
In the embodiment, the pins F21 to F24 of the panel B1 may respectively receive the start pulse signals STV1 to STV4 from the cable 221, and the panel B1 further receives the data signal DA from the cable 221. It should be noted that the pin F21 is coupled to the pin R12. The pin F22 is coupled to the pin R13. The pin F23 is coupled to the pin R14. The pin F24 is coupled to the pin R11. Therefore, the pin F21 may receive the start pulse signal STV2. The pin F22 may receive the start pulse signal STV3. The pin F23 may receive the start pulse signal STV4. The pin F24 may receive the start pulse signal STV1. In the embodiment, the pins F21 to F24 of the panel B1 are respectively coupled to the pins R21 to R24 through the bypass lines BP21 to BP24. The pin F21 of the panel B1 is further coupled to the multi-stage gate driving unit GD2. Similar to the multi-stage gate driving unit GD1 of the panel A1, the multi-stage gate driving unit GD2 may also include a plurality of gate driving units. However, since the multi-level gate driving unit GD2 may be the same as the multi-level gate driving unit GD1, features and operation methods thereof are not repeated.
In the embodiment, the pins F21 to F24 transmit the start pulse signals STV1 to STV4 to the pins R21 to R24 through the bypass lines BP21 to BP24. The multi-stage gate driving unit GD2 may be coupled to the pin F21 through the signal line OP21 to receive the start pulse signal STV2. A plurality of gate driving units of the multi-stage gate driving unit GD2 may generate a plurality of scan signals SC2 and a plurality of operation signals (not shown) according to the start pulse signal STV2. Therefore, the panel B1 may drive a plurality of display pixels of a pixel array in the panel B1 according to the plurality of scan signals SC2 generated by the multi-stage gate driving unit GD2 and the data signal DA, so that the panel B1 may display a corresponding image through the pixel array.
In the embodiment, the panel C1 may be spliced to one side of the panel B1 close to the pins R21 to R24. In the embodiment, the pins F31 to F34 and the pins R31 to R34 are respectively arranged in sequence in the same direction, and are respectively disposed on a first side and a second side of the panel C1. In the embodiment, compared to the pins R22 to R24, the pin F31 is disposed to be closest to the pin R21. Compared to the pins R21, R23, and R24, the pin F32 is disposed to be closest to the pin R22. Compared to the pins R21, R22, and R24, the pin F33 is disposed to be closest to the pin R33. Compared to the pins R21 to R23, the pin F34 is disposed to be closest to the pin R24. In the embodiment, compared to the pins F32 to F34, the pin R31 is disposed to be closest to the pin F31. Compared to the pins F31, F33, and F34, the pin R32 is disposed to be closest to the pin F32. Compared to the pins F31, F32, and F34, the pin R33 is disposed to be closest to the pin F33. Compared to the pins F31 to F33, the pin R34 is disposed to be closest to the pin F34.
In the embodiment, the pins F31 to F34 of the panel C1 may respectively receive the start pulse signals STV1 to STV4 from the cable 231, and the panel C1 further receives the data signal DA from the cable 231. It should be noted that the pin F31 is coupled to the pin R22. The pin F32 is coupled to the pin R23. The pin F33 is coupled to the pin R24. The pin F34 is coupled to the pin R21. Therefore, the pin F31 may receive the start pulse signal STV3. The pin F32 may receive the start pulse signal STV4. The pin F33 may receive the start pulse signal STV1. The pin F34 may receive the start pulse signal STV2. In the embodiment, the pins F31 to F34 of the panel C1 are respectively coupled to the pins R31 to R34 through the bypass lines BP31 to BP34. The pin F31 of the panel C1 is further coupled to the multi-stage gate driving unit GD3. Similar to the multi-stage gate driving unit GD1 of the panel A1, the multi-stage gate driving unit GD3 may also include a plurality of gate driving units. However, since the multi-level gate driving unit GD3 may be the same as the multi-level gate driving unit GD1, features and operation methods thereof are not repeated.
In the embodiment, the pins F31 to F34 transmit the start pulse signals STV1 to STV4 to the pins R31 to R34 through the bypass lines BP31 to BP34. The multi-stage gate driving unit GD3 may be coupled to the pin F31 through the signal line OP31 to receive the start pulse signal STV3. A plurality of gate driving units of the multi-stage gate driving unit GD3 may generate a plurality of scan signals SC3 and a plurality of operation signals (not shown) according to the start pulse signal STV3. Therefore, the panel C1 may drive a plurality of display pixels of a pixel array in the panel C1 according to the plurality of scan signals SC3 generated by the multi-stage gate driving unit GD3 and the data signal DA, so that the panel C1 may display a corresponding image through the pixel array.
In the embodiment, the panel D1 may be spliced to one side of the panel C1 close to the pins R31 to R34. In the embodiment, the pins F41 to F44 and the pins R41 to R44 are respectively arranged in sequence in the same direction, and are respectively disposed on a first side and a second side of the panel D1. In the embodiment, compared to the pins R32 to R34, the pin F41 is disposed to be closest to the pin R31. Compared to the pins R31, R33, and R34, the pin F42 is disposed to be closest to the pin R32. Compared to the pins R31, R32, and R34, the pin F43 is disposed to be closest to the pin R33. Compared to the pins R31 to R33, the pin F44 is disposed to be closest to the pin R34. In the embodiment, compared to the pins F42 to F44, the pin R41 is disposed to be closest to the pin F41. Compared to the pins F41, F43, and F44, the pin R42 is disposed to be closest to the pin F42. Compared to the pins F41, F42, and F44, the pin R43 is disposed to be closest to the pin F43. Compared to the pins F41 to F43, the pin R44 is disposed to be closest to the pin F44.
In the embodiment, the pins F41 to F44 of the panel D1 may respectively receive the start pulse signals STV1 to STV4 from the cable 241, and the panel D1 further receives the data signal DA from the cable 241. It should be noted that the pin F41 is coupled to the pin R32. The pin F42 is coupled to the pin R33. The pin F43 is coupled to the pin R34. The pin F44 is coupled to the pin R31. Therefore, the pin F41 may receive the start pulse signal STV4. The pin F42 may receive the start pulse signal STV1. The pin F43 may receive the start pulse signal STV2. The pin F44 may receive the start pulse signal STV3. In the embodiment, the pins F41 to F44 of the panel D1 are respectively coupled to the pins R41 to R44 through the bypass lines BP41 to BP44. The pin F41 of the panel D1 is further coupled to the multi-stage gate driving unit GD4. The multi-stage gate driving unit GD4 may include a plurality of gate driving units. However, since the multi-level gate driving unit GD4 may be the same as the multi-level gate driving unit GD1, features and operation methods thereof are not repeated.
In the embodiment, the pins F41 to F44 transmit the start pulse signals STV1 to STV4 to the pins R41 to R44 through the bypass lines BP41 to BP44. Similar to the multi-stage gate driving unit GD1 of the panel A1, the multi-stage gate driving unit GD4 may be coupled to the pin F41 through the signal line OP41 to receive the start pulse signal STV4. A plurality of gate driving units of the multi-stage gate driving unit GD4 may generate a plurality of scan signals SC4 and a plurality of operation signals according to the start pulse signal STV4. Therefore, the panel D1 may drive a plurality of display pixels of a pixel array in the panel D1 according to the plurality of scan signals SC4 generated by the multi-stage gate driving unit GD4 and the data signal DA, so that the panel D1 may display a corresponding image through the pixel array.
The panels A1 to D1 of the embodiment may receive the start pulse signals STV1 to STV4 and the data signal DA output by the same control board 210 to perform display driving operations respectively. Therefore, the panels A1 to D1 of the embodiment may provide a splicing display effect with lower display difference. Moreover, the panels A1 to D1 of the embodiment may transmit the start pulse signals STV1 to STV4 and the data signal DA there between through the cables 221, 231, 241, so that the panels A1 to D1 do not need to be directly connected to the control board 210 through their respective cables to receive the corresponding start pulse signals and the data signal DA. In other words, a cable space among the multiple panels of the splicing display device 200 of the embodiment may be effectively saved through the above-mentioned coupling method.
In addition, in some other embodiments of the disclosure, the panel A1 may not include the bypass line BP11, the panel B1 may not include the bypass line BP21, the panel C1 may not include the bypass line BP31, and the panel D1 may not include the bypass line BP41. Namely, the panels A1 to D1 respectively use the start pulse signals STV1 to STV4 to perform display driving, and the panels A1 to D1 do not need to provide their corresponding start pulse signals STV1 to STV4 to other panels through the bypass lines BP11 to BP41.
It should be noted that the hardware features of the embodiment are roughly the same as those of
In the panel B1, the pin F21 is coupled to the pin R24 through the bypass line BP21′ to transmit the start pulse signal STV2. The pin F22 is coupled to the pin R21 through the bypass line BP22′ to transmit the start pulse signal STV3. The pin F23 is coupled to the pin R22 through the bypass line BP23′ to transmit the start pulse signal STV4. The pin F24 is coupled to the pin R23 through the bypass line BP24′ to transmit the start pulse signal STV1. In the embodiment, the pins R21 to R24 of the panel B1 are sequentially coupled to the pins F31 to F34 of the panel C1 through the cable 231 respectively.
In the panel C1, the pin F31 is coupled to the pin R34 through the bypass line BP31′ to transmit the start pulse signal STV3. The pin F32 is coupled to the pin R31 through the bypass line BP32′ to transmit the start pulse signal STV4. The pin F33 is coupled to the pin R32 through the bypass line BP33′ to transmit the start pulse signal STV1. The pin F34 is coupled to the pin R33 through the bypass line BP34′ to transmit the start pulse signal STV2. In the embodiment, the pins R31 to R34 of the panel C1 are sequentially coupled to the pins F41 to F44 of the panel D1 through the cable 241 respectively.
In the panel D1, the pin F41 is coupled to the pin R44 through the bypass line BP41′ to transmit the start pulse signal STV4. The pin F42 is coupled to the pin R41 through the bypass line BP42′ to transmit the start pulse signal STV1. The pin F43 is coupled to the pin R42 through the bypass line BP43′ to transmit the start pulse signal STV2. The pin F44 is coupled to the pin R43 through the bypass line BP44′ to transmit the start pulse signal STV3.
In other words, the panels A1 to D1 of the embodiment of
It should be noted that the hardware features of the panels A2 to D2 of the embodiment are the same or similar to those of the panels A1 to D1 of
In the embodiment, the pins R11 to R14 of the panel A2 may respectively receive the start pulse signals STV1 to STV4 from the cable, and the panel A2 also receives the data signal DA from the cable. The pins R11 to R14 of the panel A2 are respectively coupled to the pins F11 to F14 through the bypass lines BP11 to BP14. The pin F11 of the panel A2 is also coupled to the multi-stage gate driving unit GD1, i.e., in the panel A2, the start pulse signal STV1 is first received by the pin R11, and is then transmitted to the multi-stage gate driving unit GD1 through the pin F11. In the embodiment, the pins F21 to F24 of the panel B2 may respectively receive the start pulse signals STV2 to STV4 and STV1 from the cable, and the panel B2 also receives the data signal DA from the cable. The pins F21 to F24 of the panel B1 are respectively coupled to the pins R21 to R24 through the bypass lines BP21 to BP24. The pin F21 of the panel B2 is further coupled to the multi-stage gate driving unit GD2. The multi-stage gate driving unit GD2 may include a plurality of gate driving units GD21 to GD2n. In other words, the start pulse signals STV1 to STV4 and the data signal DA of the embodiment may be input through the cable between the panel A2 and the panel B2 to achieve a similar display driving function. In addition, the signal transmission manner of the panel C2 and the panel D2 of the embodiment is similar to that of the panel C1 and the panel D1 in the embodiment of
In addition, in other embodiments of the disclosure, the start pulse signals STV1 to STV4 and the data signal DA may also be separately transmitted from another plurality of wires and another plurality of pins on the panel A2 or the panel B2. Namely, the separate transmission lines of the signals are located in the panel, rather than being achieved by branching the cable. For example, the panel A2 may further include another plurality of pins to receive the start pulse signals STV1 to STV4 and the data signal DA. On one hand, the another plurality of wires are used to connect the pins R11 to R14 of the panel A2, and on the other hand, the panel B2 is coupled to the another plurality of pins of the panel A2 through the cable.
It should be noted that the hardware features of the panels A2 to D2 of the embodiment and the coupling method of the bypass lines BP11 to BP14, BP21 to BP24, BP31 to BP34, and BP41 to BP44 are similar to that of the panels A1 to D1 of
In the embodiment, the pins R11 to R14 of the panel A2 may respectively receive the start pulse signals STV1 to STV4 from the cable, and the panel A2 also receives the data signal DA from the cable. The pins R11 to R14 of the panel A2 are respectively coupled to the pins F12 to F14 and the pin F11 through the bypass lines BP11 to BP14 in the manner shown in
In addition, in some other embodiments of the disclosure, the start pulse signals STV1 to STV4 and the data signal DA may also be separately transmitted from another plurality of wires and another plurality of pins on the panel A2 or the panel B2. Namely, the separate transmission lines of the signals are located in the panel, rather than being achieved by branching the cable. For example, the panel A2 may further include another plurality of pins to receive the start pulse signals STV1 to STV4 and the data signal DA. On one hand, the another plurality of wires are used to connect the pins R11 to R14 of the panel A2, and on the other hand, the panel B2 is coupled to the another plurality of pins of the panel A2 through the cable.
In the embodiment, the panels A1, B2, and C3 are respectively coupled to the panels B1, C2, and B3 through cables 521, 522, and 533. The panels A1, B2, and C3 may respectively transmit the plurality of start pulse signals for driving the panels B1, C2, B3 and the data signal DA to the panels B1, C2, B3 through a plurality of bypass lines in the panels A1, B2, and C3 and the cables 521, 522, 533. In this regard, the panels B1, C2, and B3 may respectively perform display driving based on the corresponding start pulse signals and the data signal DA.
In the embodiment, the panels C1 and B3 are respectively coupled to the panels D1 and A3 through cables 541 and 532. The panels C1 and B3 may respectively transmit the plurality of start pulse signals for driving the panels D1 and A3 and the data signal DA to the panels D1 and A3 through a plurality of bypass lines in the panels C1 and B3 and the cables 541 and 532. In this regard, the panels D1 and A3 may respectively perform display driving based on the corresponding start pulse signals and the data signal DA.
It should be noted that
In the embodiment, the panels A1, A2, and B3 are respectively coupled to the panels B1, C2, and C3 through cables 521′, 522′, and 523′. The panels A1, A2, and B3 may respectively transmit the plurality of start pulse signals for driving the panels B1, C1 to C3, and D1 to D3 and the data signal DA to the panels B1, C2, C3 through a plurality of bypass lines in the panels A1, A2, and B3 and the cables 521′, 522′, and 523′. In this regard, the panels B1, C2, and C3 may respectively perform display driving based on the corresponding start pulse signals and the data signal DA.
In the embodiment, the panels B1, C2, and C3 are respectively coupled to the panels C1, D2, and D3 through cables 531′, 532′, and 533′. The panels B1, C2, and C3 may respectively transmit the plurality of start pulse signals for driving the panels C1, D1 to D3 and the data signal DA to the panels C1, D2, D3 through a plurality of bypass lines in the panels B1, C2, and C3 and the cables 531′, 532′, and 533′. In this regard, the panels C1, D2, and D3 may respectively perform display driving based on the corresponding start pulse signals and the data signal DA.
In the embodiment, the panel C1 is coupled to the panel D1 through a cable 541′. The panel C1 may transmit the plurality of start pulse signals for driving the panel D1 and the data signal DA to the panel D1 through a plurality of bypass lines in the panel C1 and the cable 541′. In this regard, the panel D1 may respectively perform display driving based on the corresponding start pulse signals and the data signal DA.
Therefore, the panel cable arrangement of the splicing display device 500′ of the embodiment may be arbitrarily adjusted according to different splicing requirements, thereby providing a variety of device appearances or splicing display effects. In addition, the disclosure may also have a cost-saving effect. Since each panel of the splicing display device 500′ has the similar signal transmission path inside, a variety of appearance changes of the splicing display device may also be achieved by using uniformly produced panels, without the need of producing different panels for special splicing appearances.
In summary, the splicing display device of the disclosure may provide multiple start pulse signals and the data signal through the same control board, so as to present splicing display images with small display brightness differences. In addition, the splicing display device of the disclosure may efficiently transmit multiple start pulse signals and the data signal to the adjacent panels through a special pin design of the panels, so as to effectively reduce an installation space of the cables. Moreover, since each panel of the splicing display device has the same or similar signal transmission path inside, a variety of appearance changes of the splicing display device may be achieved by using uniformly produced panels, without the need of producing different panels for special splicing appearances.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations provided they fall within the scope of the following claims and their equivalents.
Number | Date | Country | Kind |
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202110764179.8 | Jul 2021 | CN | national |
This application claims the priority benefit of U.S. Provisional Application No. 63/108,447, filed on Nov. 2, 2020 and China Application No. 202110764179.8, filed on Jul. 6, 2021. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
Number | Date | Country | |
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63108447 | Nov 2020 | US |