Patent Application
20120155273
This application is related to traffic routing of a processor.
In a processor composed of multiple processing units, each having several cores, or compute units, there are links of varying bandwidth between the cores and memory caches which permit traffic transfer. Traffic congestion on any of these links degrades performance of the processor. Diversion of traffic routing to alleviate congestion may result in additional hops to reach the destination, resulting in increased latency for a single transfer.
A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.
In this application, a processor may include a plurality of nodes, with each node having a plurality of computing units. A multi-chip processor is configured to include at least two processors with means to link the nodes to other nodes, and to memory caches.
As shown, processor 110 includes computing units 105, 106 and 107, which are connected to a system request queue (SRQ) 113 used as a command queue for the computing units 105, 106, 107. A crossbar (Xbar) switch 112 interfaces between links L1, L2, L3 and L4 and the SQR 113. A routing table 111 and a control register 114 are each configured to control the crossbar interface 112 and the traffic routing over the links L1, L2, L3 and L4. While four links L1, L2, L3 and L4 are depicted in
In order to enable the victim requests and responses to be routed according to the split routing scheme along the high bandwidth links, a special mode bit cHTVicDistMode is set in the control register 114 (e.g., a coherent link traffic distribution register). For example, the compute unit 105, 106, 107 may set a value of 1 for the mode bit cHTVicDistMode when a link pair traffic distribution is enabled, such as processor node pair 110 and 140. Alternatively, the mode bit cHTVicDistMode may be set to 1 to indicate that the split traffic scheme is enabled without having enabled the pair traffic distribution. In addition, the following settings may be made by the compute unit 105, 106, 107 to the control register 114 to enable and define parameters for the split routing scheme. A distribution node identification bit in element DistNode [5:0] is set for each of the processor nodes involved with the distribution (e.g., for this 5-bit element with binary value range of 0 to 31, a value 0 may be assigned to processor node 110, and a value 3 may be assigned to processor node 140). A destination link element DstLnk [7:0] is specified for a single link. For example, for this 8-bit element, bit 0 may be assigned to link 251, bit 1 may be assigned to link 253, bit 2 may be assigned to link 255, and setting the destination link to link 251 would be achieved by setting bit 0 to value 1. Using this enablement setting scheme for processor node 110 by way of example, when a victim packet is detected and heading toward the distribution node identified by the bit DistNode, such as processor node 140, the victim packet is routed to the destination link that is specified by the bit DstLnk (high bandwidth link 251) instead of the destination link as defined in the routing table 111 (low bandwidth link 255). Additional refinement to the split traffic routing scheme can be achieved by providing indicators as to whether the split routing scheme should handle a victim request or a victim response or both. To indicate that a victim request is enabled for the split routing scheme, a coherent request distribution enable bit cHTReqDistEn is set to 1. If it is desired to control only the associated victim response, or to control the victim response additionally to the victim request using the split traffic routing, a coherent response distribution enable bit cHTRspDistEn is set to 1.
In a variation to the above described embodiment, the routing table 111 may be configured with the parameters of the split traffic routing scheme such that the split traffic routing is enabled to be executed directly according to the routing indicated in the routing table 111, instead of the control register 114.
The victim distribution mode for a processor node in the configuration illustrated in
Table 1 shows an example of a utilization table comparing link utilization based on implementation of the above configurations 200 and 400, having read:write ratios that are a function of the workload. As shown, when routing is evenly distributed across high bandwidth links and low bandwidth links (i.e. configuration 200), the high bandwidth link utilization is 50% which corresponds to the 2:1 link size ratio. Using the split routing scheme of configuration 400, the high bandwidth and low bandwidth links can be more evenly utilized.
Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. The apparatus described herein may be manufactured by using a computer program, software, or firmware incorporated in a computer-readable storage medium for execution by a general purpose computer or a processor. Examples of computer-readable storage mediums include a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs).
Embodiments of the present invention may be represented as instructions and data stored in a computer-readable storage medium. For example, aspects of the present invention may be implemented using Verilog, which is a hardware description language (HDL). When processed, Verilog data instructions may generate other intermediary data (e.g., netlists, GDS data, or the like) that may be used to perform a manufacturing process implemented in a semiconductor fabrication facility. The manufacturing process may be adapted to manufacture semiconductor devices (e.g., processors) that embody various aspects of the present invention.
Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions (such instructions capable of being stored on a computer readable media). The results of such processing may be maskworks that are then used in a semiconductor manufacturing process to manufacture a processor which implements aspects of the present invention.
