Spur and quantization noise cancellation for PLLS with non-linear phase detection

Abstract

A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Description

BACKGROUND

Field of the Invention

This application relates to quantization noise cancellation and spur cancellation in a phase-locked loop.

Description of the Related Art

Today's high data rate wire-line and wireless communication systems require a clock source with a low rms jitter performance. Such applications typically use fractional-N phased-lock loops (PLLs) since fractional-N PLLs enable very high frequency resolution. However, by their very nature fractional-N PLLs also have to deal with the large quantization noise resulting from the implementation of the fractional feedback divider value. Furthermore, in order to reduce the noise contribution from the charge pump and the blocks following the phase detector, a high gain sampling phase detector is often used in such PLLs.

SUMMARY OF EMBODIMENTS OF THE INVENTION

In order to better cancel quantization noise, an embodiment provides a method of operating a phase-locked loop (PLL) that includes generating a polynomial indicative of noise to be canceled, the noise including quantization noise and frequency translated quantization noise. The quantization noise is associated with a first delta sigma modulator controlling a feedback divider in the PLL. Generating the polynomial includes combining a signal indicative of a spur and a residue term indicative of the quantization noise, the spur being present in a reference clock signal being supplied to a phase and frequency detector of the PLL. The method further includes cancelling the quantization noise and the frequency translated quantization noise in an analog error signal in the PLL based on the polynomial.

In another embodiment a method is provided that includes generating a polynomial for use in canceling quantization noise in a PLL analog error signal indicative of a phase difference between a reference clock signal and a feedback signal. The quantization noise is associated with a delta sigma modulator controlling a feedback divider in the PLL that supplies the feedback signal. The polynomial is further used in canceling frequency translated quantization noise present, in part, due to a spur in the reference clock signal that is being supplied to an input of a phase and frequency detector of the PLL. The method further includes canceling the quantization noise and frequency translated quantization noise based on the polynomial that is generated.

In another embodiment a phase-locked loop (PLL) is provided that includes an oscillator and a time to voltage converter. The time to voltage converter has a phase and frequency detector (PFD) that receives a feedback signal and a reference clock signal and the time to voltage converter supplies a voltage error signal indicative of a phase difference between the reference clock signal and the feedback signal. A feedback divider is coupled to an output of the oscillator and configured to supply the feedback signal. A spur cancellation circuit is configured to receive a dither signal, a residue signal indicative of quantization noise associated with a first delta sigma modulator controlling the feedback divider and to receive a spur signal indicative of a spur that is present in the reference clock signal. The spur cancellation circuit is configured to generate a cancellation polynomial indicative of noise to be canceled, the noise to be canceled including quantization noise and frequency translated quantization noise.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1A illustrates a high level block diagram of an embodiment of a PLL 100 with a high gain time to voltage converter.

FIG. 1B illustrates a high level block diagram of an RC charging circuit of the time-to-voltage converter.

FIG. 2 illustrates non-linearity associated with a high gain time-to-voltage converter.

FIG. 3 illustrates two noise sources that combine in a high gain time-to-voltage converter.

FIG. 4 illustrates a crystal oscillator and buffer circuit that generates a reference clock having a frequency that is twice the frequency of the signal supplied by the crystal oscillator.

FIG. 5A illustrates that a DC time error supplied to a type II PLL results in the feedback pulse moving to the right.

FIG. 5B illustrates a duty cycle error on even and odd pulses that results in a discrete time square wave error term to appear at the phase detector input.

FIG. 6A illustrates the quantization noise power spectral density.

FIG. 6B illustrates the power spectral density in the presence of second order non-linearity in the time to voltage converter and a period error in the reference clock signal.

FIG. 7 illustrates how the frequency translated quantization noise affects PLL performance.

FIG. 8 illustrates an embodiment that addresses the frequency-translated quantization noise caused by a spur (a duty cycle error) present in the reference clock signal.

FIG. 9 illustrates the adaptation loop used to update the coefficients h₁-h₅ of the polynomial used to cancel the quantization noise and frequency translated quantization noise.

FIG. 10 illustrates the use of the Gauss Seidel Method in the adaptation loop.

FIG. 11 illustrates the covariance matrix C_ex used in the adaptation loop.

FIG. 12 illustrates an alternative embodiment to generate a cancellation signal that cancels the quantization noise and frequency translated quantization noise.

FIG. 13 illustrates another alternative embodiment to generate a cancellation signal that cancels the quantization noise and frequency translated quantization noise.

FIG. 14 illustrates how the cancellation affects PLL performance by reducing quantization noise.

The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION

FIG. 1A illustrates a high level block diagram of an embodiment of a PLL 100. PLL 100 includes a high gain RC based time-to-voltage converter 101 that supplies a differential voltage 103 to an analog to digital converter (ADC) 105. The time-to-voltage converter 101 (also referred to herein as a phase detector) converts the phase difference between the reference clock signal (REF) 107 and the feedback signal (FB) 109 to the voltage 103. In simple terms, phase detection gain is considered to be high if a steep slope generator, with slopes greater than a few GV/s, is used as part of the phase detector. Conventional phase detectors do not use a slope generator and generate a current/voltage pulse whose width is proportional to the time difference of the two inputs of the phase detector. Consequently, these phase detectors have low gain, (½π) in typical applications. High gain is realized by the slopes generated while charging/discharging a capacitor through a resistor. The ADC 105 supplies a digital value corresponding to the phase difference to digital loop filter 111, which in turn controls the digitally controlled oscillator (DCO) 115. The feedback divider 117 supplies the feedback clock signal 109. Delta sigma modulator (DSM) 119 controls the feedback divider 117 to achieve a fractional-N divider. Significant quantization noise, corresponding to residue 121, is associated with the DSM 119.

High gain sampling phase detectors such as the time-to-voltage converter 101 in FIG. 1A, have a significant non-linearity associated with them. In the presence of an additive spur at the input of the phase detector in reference clock signal 107, these non-linearities cause the mixing of quantization noise with the spur which degrades the system performance. In FIG. 1A, T is the time constant of RC charging circuit in the RC time to voltage converter. In the embodiment illustrated in FIG. 1A, τ ln(0.5)=275 ps and corresponds to the time delay after which the voltage from RC charging (rising curve 116 in time-to-voltage converter 101) equals the voltage from RC discharging curve (falling curve 118 in time-voltage converter 101). FIG. 1B illustrates an example of an RC charging circuit. The charge pulse is based on the phase difference between the REF clock signal 107 and the FB clock signal 109. The discharge pulse discharges the capacitor every measurement cycle. Additional details of an embodiment of a high gain time-to-voltage converter can be found in U.S. Pat. No. 9,762,250, entitled “Cancellation of Spurious Tones Within a Phase-Locked Loop with a Time-to-Digital Converter”, naming Michael H. Perrot as inventor, issued Sep. 12, 2017, which patent is incorporated herein by reference in its entirety. Other embodiments use different approaches, e.g., current sources, to achieve the steep slope generator of a high gain phase detector. Since the PLL integrates the difference between the RC charging and RC discharging voltages to set the VCO control voltage, the loop should settle to an operating point where the RC charging voltage equals the RC discharging voltage. In other words, the loop should settle to the point of intersection of the two curves in 101. The slope of the curves at this operating point sets the gain of the phase detector and affects the noise performance as well of the PLL. As shown for the high gain phase detector of FIG. 1A, the slope=Vdd/τ=2.5 GV/s.

FIG. 2 illustrates the non-linearity associated with the high gain time-to-voltage converter 101 shown in FIG. 1A. FIG. 2 shows the positive (p) and negative (n) voltage values associated with various values of phase differences between the feedback clock signal and the reference clock signal. FIG. 2 illustrates that there is more differential voltage at 201 to represent the time difference Δt to the left of to than the differential voltage 203 representing the time difference Δt to the right of time to. Thus, the magnitude of the voltage is different according to whether the time difference is positive or negative. Such a difference in magnitude indicates a strong even order distortion.

FIG. 3 illustrates two noise sources that combine with a high gain time-to-voltage converter. The output of the time-to-voltage converter is shown in the top graph 301 for various phase difference values. The output of the time-to-voltage converter includes quantization noise (q) shown at 303. The quantization noise 303 is combined with the spur (s) shown at 305. The spur comes from a period error of the reference clock signal. In an embodiment, the reference clock signal is generated in a crystal oscillator and buffer circuit 400 such as shown in FIG. 4. The crystal oscillator 401 provides a signal that is converted to a square wave in the sine to square waver converter 403. A 2× clock multiplier 405 follows the sine to square wave converter 403. The threshold of the sine-to-square wave converter is corrected through the feedback loop that includes the duty cycle correction circuit 407. The 2X clock multiplier 405 doubles the frequency of the fix signal 409 supplied by the sine to square wave converter 403 and provides the f_2x signal 410. The f_2x signal 410 corresponds to the reference clock signal 107 shown in FIG. 1A. The crystal oscillator and buffer circuit 400 are described in greater detail in U.S. patent applications. Ser. No. 16/670,874, entitled “Noise Canceling Technique for a Sine to Square Wave Converter”, naming Aslamali R. Rafi as first inventor, filed Oct. 31, 2019, which application is incorporated herein by reference in its entirety.

The f_2x signal 410 contains a period error as explained further herein. Such a period error would be readily canceled by a linear phase detector. However, with a non-linear phase detector such as shown in FIG. 1A, the period error results in a spur on the output of the PLL if the spur is not otherwise addressed. FIG. 5A illustrates that a DC time error 501 supplied to a type II PLL results in the feedback pulse moving to the right as shown at 503. However, as shown in FIG. 5B, the duty cycle error on even and odd pulses shown at 521, 523, 525 in the f_2x clock signal results in a discrete time square wave (±t_err/2) error term to appear at the phase detector input. As shown at 527 the period error results in the time error alternating between (t_err/2) and (−t_err/2).

FIG. 6A illustrates the quantization noise power spectral density absent the presence of second order non linearity. As can be seen, the noise at the f_2x frequency is near zero. However, in the presence of second order non-linearity in the time to voltage converter, the quantization noise q and the spur s from the period error combine as (q+s)²=q²+s²+2 qs. FIG. 6B shows that the presence of second order non-linearity results in an extra term with the quantization noise being frequency translated to the frequency f_2x.

The frequency translated quantization noise negatively affects the PLLs performance. Referring to FIG. 7, line 701 shows the level of acceptable noise PLL performance in an embodiment and line 703 shows the elevated noise and sub-reference spur 705 resulting in degraded phase noise performance when a spur mixes with quantization noise in the phase detector.

Embodiments described herein enable high-gain low-noise phase detection even in the presence of a spur at the reference clock signal input allowing realization of high performance ultra-low jitter PLLs that achieve performance comparable to that of a high Q bulk acoustic wave (BAW) based resonator used as a voltage controlled oscillator (VCO) while using a conventional LC oscillator as the VCO using digital techniques.

FIG. 8 illustrates an embodiment that addresses the frequency-translated quantization noise caused by an additive spur in the reference clock signal. PLL 800 includes an RC time-to-voltage converter 801 that supplies a voltage 803 to an analog to digital converter (ADC) 805 through summer 806 and low pass filter 808. The time to voltage converter 801 includes a phase and frequency detector (PFD) and RC charging circuit (not shown separately in FIG. 8). The voltage 803 is an analog error signal representing the phase difference between reference clock (REF) 807 and the feedback clock (FB) 809. The low pass filter (LPF) 808 is a consequence of transferring the sampled voltage of RC phase detector into the ADC input. That is accomplished as charge transfer from the sampling capacitor of RC phase detector 801 (also referred to herein as a time-to-voltage converter) into an integrating capacitor at the input of ADC 805. That charge transfer results in a discrete time low pass filter, whose effect is cancelled out in the digital domain by the action of the inverse filter 812. The ADC 805 supplies a digital error signal corresponding to the phase difference to the inverse low pass filter 812. Summing circuit 806 receives a cancellation signal from a capacitor digital to analog converter (DAC) 823, to add or subtract a cancellation voltage to cancel the quantization noise (including the frequency translated quantization noise) and the spur. An embodiment of a capacitor DAC is described in U.S. Pat. No. 9,762,250, entitled “Cancellation of Spurious Tones Within a Phase-Locked Loop with a Time-to-Digital Converter”, naming Michael H. Perrot as inventor, issued Sep. 12, 2017. In other embodiments, a different type of DAC is used to add or subtract charge to cancel the quantization noise. A second summing circuit 814 adjusts the error signal 841 being supplied to digital loop filter 811 based on the residue from delta sigma modulator 831 as explained further herein. The digital loop filter 811 controls the DCO 815 to adjust the output of the DCO to match the reference clock signal. The PLL 800 includes a fractional N feedback divider including a multi-modulus feedback divider 817 under control of delta sigma modulator 819. DSM 819 receives a fractional divide value N.f and controls the multi-modulus feedback divider 817. Significant quantization noise is associated with the DSM 819.

In an embedment the delta sigma modulator 819 is a conventional second order DSM and provides a residue sequence 821 that corresponds to the delta sigma quantization noise to be cancelled. A dither sequence (not shown in FIG. 8) is used by the delta sigma modulator to improve scrambling of the quantization noise. In an embodiment, the dither sequence is removed from the residue signal before determining a cancellation polynomial representing the noise to be canceled.

The accumulated dither signal 823 is subtracted from the integrated residue signal 824 (residue_ph) in summer 825 and the subtraction result x₁ is supplied to the coefficient block h₁. The residue 821 of the delta sigma modulator is a “frequency” residue. That is because the output of the delta sigma modulator controls the instantaneous division value of feedback divider or in other words the frequency of the divided down signal. However, at the phase detector input, the phase is determined by the sum of all the previous feedback divider values. That inherent integration implies that if the quantization noise is canceled at the phase detector output, “phase” residue should be used instead of “frequency” residue. Thus, the frequency residue is integrated to provide the phase residue (residue_ph). Note that the summers shown in FIG. 8 and the other figures herein may be additive or subtractive. The spur 827 in the form of a scaled square wave is supplied to a coefficient block h₅ and h₅x₅ is added to the result h₁x₁ in summer 825. The output x_1c of the summer 825 is combined with other terms to form a polynomial, which corresponds to the noise to be canceled and a cancellation value based on the polynomial is supplied to delta sigma modulator 831. The output of the delta sigma modulator 831 is used to control the capacitor DAC 832, which adds or subtracts voltage from the analog error signal (phase difference between REF clock 807 and FB clock 809) to cancel both the spur and quantization noise, including frequency translated components thereof.

Note that the embodiment of FIG. 8 is trying to replicate what happens in the analog phase detector through digital signal processing. The non-linearity of the time-to-voltage converter resulting in the frequency translation is mimicked digitally through the “square” term x₂ and the “cube” term x₃ of the polynomial. The linear term x_1c addresses non-frequency translated quantization and spur error. The output x_1c of summer 825 is supplied to divider block 828, which divides x_1c by the coefficient h1. Thus, x₁c/h₁ is squared and cubed and multiplied by coefficients h₂ and h₃ to form the square and cube terms respectively of the polynomial. Thus, frequency translated quantization noise appears in x₂ and x₃. Frequency translated quantization noise as well as non frequency translated quantization noise are accounted for in the polynomial supplied to the delta sigma modulator 831.

One reason for utilizing the delta sigma modulator 831 is to achieve a reasonable number, e.g., 4-6 bits for the capacitor DAC to make the capacitor DAC implementation practical. However, use of the delta sigma modulator 831 results in residual quantization noise error that also needs to be corrected. The error of the capacitor DAC cancellation can be estimated from the residue 833 of the delta sigma modulator 831 using a first order difference in block 835 and an appropriate scaling factor h₄. The residue error is subtracted from the digital error signal (phase difference) in summer 814 before being supplied to digital loop filter 811. For ease of illustration, the high level digital signal processing block diagram shown in FIG. 8 omits delay blocks that may be required to properly align signals.

The parameters of the analog time-to-voltage converter are a function of semiconductor process and temperature, whereas, digital signal processing is not. Therefore, an adaptive algorithm is used to find the coefficients, h₁-h₅, so that the digital estimate of the gain and non-linearity of the time-to-voltage converter is as close to the analog gain and non-linearity as permissible. FIG. 9 illustrates an embodiment of an adaptation loop used to update the coefficients h₁-h₅. C_xx is the covariance matrix of the signals x₁, x₂, x₃, x₄ and x₅ (shown in FIG. 8) and C_ex is cross-correlation vector of the error ē with x₁-x₅, where the error e is shown at 841 in FIG. 8. The product of the inverse of C_xx and C_ex generated in 901 provides an estimate Δh of the deviation of the weights h from the optimum solution

$\left(\stackrel{\_}{h_{opt}}\right),$ and thus

$\Delta \overline{h}=\left(\overline{h}-\stackrel{\_}{h_{opt}}\right).$ With analog cancellation, the non linear phase error y is not available for determining the cross correlation matrix C_ex. Instead, y is distributed and is present as input to the summers 806 and 814 in FIG. 8. So, in FIG. 9 the summer 902 whose input is y is actually distributed in two places in the embodiment of FIG. 8: namely, 806 and 814. The non linear phase error y is a linear combination of x₁, x₂, x₃, x₄, and x₅, where

$\overline{y}=\alpha \stackrel{\_}{x_1}+\beta \stackrel{\_}{x_2}+\gamma \stackrel{\_}{x_3}+\delta \stackrel{\_}{x_4}+\varepsilon \stackrel{\_}{x_5}.$ Instead of y, the error ē is used to determine the deviations of h from

$\left(\stackrel{\_}{h_{opt}}\right).$ The error

$\overline{e}=\left(h_1-\alpha \right)\stackrel{\_}{x_1}+\left(h_2-\beta \right)\stackrel{\_}{x_2}+\left(h_3-\gamma \right)\stackrel{\_}{x_3}+\left(h_4-\delta \right)\stackrel{\_}{x_4}+\left(h_5-\varepsilon \right)\stackrel{\_}{x_5},$ is minimized when

$\overline{h}=\left(\stackrel{\_}{h_{opt}}\right),$ where

$\stackrel{\_}{h_{opt}}$ is a vector whose elements are α, β, γ, δ and ∈. The deviation of h from

$\stackrel{\_}{h_{opt}}$ is estimated by the product of the inverse of C_xx and C_ex generated in box 901. The adaptation loop acts upon this deviation of h, from

$\stackrel{\_}{h_{opt}}$ and drives this deviation to zero. That is accomplished by integrating this deviation through the accumulators 905 in FIG. 9 and letting the accumulator outputs control the h weights. The gain term K in the adaptation loop is used to trade-off noise and bandwidth of the adaptation loop. The output of the accumulators will converge to the desired coefficient values h₁-h₅ leading to zero correlation between x₁-x₅ and the error signal ē. Thus, the convergence results in the product of C_xx⁻¹ and C_ex going to zero. The accumulated values in accumulator 905 will then maintain the correct h₁-h₅ values to effectively cancel the noise terms including the frequency translated noise. With environmental changes such as changes in voltage or temperature, non-zero correlation will again occur and the coefficient values h₁-h₅ will be adjusted by the adaptation loop until zero correlation returns.

In an embodiment, the product of the inverse of the covariance matrix (C_xx⁻¹) with C_ex is found iteratively through use of the Gauss Seidel algorithm. FIG. 10 illustrates solving for (Δh), which is the deviation of h from

$\stackrel{\_}{h_{opt}}.$ The weights (Δh) are determined by C_xx⁻¹C_ex and the matrix inversion is carried out iteratively using the Gauss Seidel Method. The steps include (1) scale C_xx and C_ex such that C_xx has unity diagonal; (2) split C_xx into a unity diagonal I, a lower matrix L, and an upper matrix U as shown in FIG. 10, and (3) iterate on equation 1001. Other embodiments use an alternative algorithm to do matrix inversion, e.g., Jacobi or Gauss Elimination.

FIG. 11 illustrates the cross correlation matrix C_ex. Note that since the spur signal s is a square wave, computations shown at 1101 and 1103 involve only shifting and adding and not multiplication, simplifying possible implementations.

FIG. 12 illustrates an alternative implementation to generate a control signal for the capacitor DAC that accounts for frequency translated quantization noise as well as non frequency translated quantization noise in the polynomial supplied to the delta sigma modulator 831. In the embodiment of FIG. 12, the coefficient block h₁ moves to the right side of summer 825 as compared to FIG. 8. The summer 825 in FIG. 12 sums the signal x₁ (residue less dither) and the spur signal (x₅) multiplied by h₅ to scale the spur square wave to generate the summer 825 output x_1c. The square term x₂ and the cube term x₃ are formed by squaring and cubing the summer output x_1c. Note that the implementation shown in FIG. 12 eliminates the need for the (1/h₁) block 828 used in the implementation shown in FIG. 8. Note that h5 converges to different values in the embodiments of FIGS. 8 and 12. That is expected because the gain from h5 to the cancellation point is also different in the two solutions. The value of converged h5 in one case will be h1 times the converged value of h5 in the other.

Another embodiment shown in FIG. 13 combines the quantization error (the residue signal 821) and the spur 827 to generate a polynomial for use in generating the cancellation signal. Note that the polynomial generated in FIG. 13 includes additional coefficients (h₁-h₇) as compared to the embodiment of FIG. 8, which has four (h₁-h₄) instead of seven coefficients. That results in the covariance matrix increasing from a 5×5 to a 7×7 requiring additional operations. In the embodiment of FIG. 13, frequency translated versions of q, q² and q³ are generated and adaptively cancelled through coefficients h₅, h₆ and h₇. Coefficients h₁, h₂ and h₃ are used to adaptively cancel the non frequency translated quantization noise q, q², and q³. For applications that have power and/or space considerations, the solutions described in FIGS. 8 and 12 provide advantages as compared to the solution in FIG. 13.

Referring to FIG. 14, showing results of modeling of the cancellation approaches described herein. The model assumes non-linearity up to 5^th order in the RC time to voltage converter and correction until 3^rd order. Curve 1401 represents the level of acceptable PLL performance, and after cancellation the frequency translated quantization noise is suppressed to levels indicated by 1403, which are quite low when compared to the acceptable mask of phase noise. As compared to FIG. 7, the noise cancellation can be seen to be successful at lowering elevated noise resulting from the spur on the reference clock input signal and a high gain time to voltage converter.

Thus, various aspects of a high resolution low noise PLL that effectively cancels quantization noise and frequency translated quantization noise have been described. The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method of operating a phase-locked loop (PLL) comprising: generating a polynomial indicative of noise to be canceled, the noise including quantization noise and frequency translated quantization noise, the quantization noise associated with a first delta sigma modulator controlling a feedback divider in the PLL;wherein generating the polynomial includes combining a signal indicative of a spur and a residue term indicative of the quantization noise, the spur being present in a reference clock signal being supplied to a phase and frequency detector of the PLL; andcancelling the quantization noise and the frequency translated quantization noise in an analog error signal in the PLL based on the polynomial.

2. The method as recited in claim 1 further comprising: supplying a cancellation value corresponding to the polynomial to a second delta sigma modulator;generating a cancellation control signal in the second delta sigma modulator based on the cancellation value; andcontrolling a digital to analog converter with the cancellation control signal to add or subtract a cancellation voltage to or from the analog error signal to thereby cancel the quantization noise and the frequency translated quantization noise, the analog error signal indicative of a phase difference between a feedback signal from the feedback divider and the reference clock signal.

3. The method as recited in claim 2 further comprising: taking a first order difference of a second residue from the second delta sigma modulator, the second residue corresponding to second quantization noise;multiplying the first order difference by a scale factor as part of generating a second cancellation signal; andcancelling error caused by the second quantization noise.

4. The method, as recited in claim 1, further comprising: supplying a square wave as the signal indicative of the spur;forming a linear term, a square term, and a cube term of the polynomial, the linear term, the square term, and the cube term incorporating a spur term that is the signal indicative of the spur;updating coefficients of the linear term, the square term, and the cube term adaptively; anddetermining a cancellation value based on the polynomial.

5. The method, as recited in claim 4, wherein the square wave is a ±1 square wave corresponding to a period error of the reference clock signal.

6. The method as recited in claim 4 wherein forming the polynomial further comprises: subtracting a dither term from the residue term to form a first result;multiplying the first result by a first coefficient and generating a first multiplication result;multiplying the spur term by a another coefficient and generating a second multiplication result;summing the first multiplication result and the second multiplication result and forming the linear term of the polynomial;supplying the linear term to a summing circuit;dividing the linear term by the first coefficient to generate a division result, squaring the division result to generate a squared division result, and multiplying the squared division result by a second coefficient to generate the square term of the polynomial;supplying the square term to the summing circuit;cubing the division result to generate cubed division result, and multiplying the cubed division result by a third coefficient to generate the cube term of the polynomial; andsupplying the cube term to the summing circuit.

7. The method as recited in claim 4 wherein forming the polynomial further comprises: subtracting a dither term from the residue term to form a first result ;multiplying the spur term by a fifth coefficient and generating a first multiplication result;summing the first multiplication result and the first result to form a first sum;multiplying the first sum by a first coefficient to form the linear term of the polynomial;supplying the linear term to a summing circuit;squaring the first sum to generate a first squared term, and multiplying the first squared term by a second coefficient to generate the square term of the polynomial;supplying the square term to the summing circuit;cubing the first sum to generate a first cubed term, and multiplying the first cube term by a third coefficient to generate the cube term of the polynomial; andsupplying the cube term to the summing circuit.

8. A method of operating a phase-locked loop (PLL) comprising: generating a polynomial for use in canceling quantization noise present in a PLL analog error signal indicative of a phase difference between a reference clock signal and a feedback signal, the quantization noise associated with a delta sigma modulator controlling a feedback divider in the PLL that supplies the feedback signal, and the polynomial for use in canceling frequency translated quantization noise present, in part, due to a spur in the reference clock signal that is being supplied to an input of a phase and frequency detector of the PLL; andcanceling the quantization noise and frequency translated quantization noise based on the polynomial that is generated.

9. The method as recited in claim 8 wherein the frequency translated quantization noise is caused, at least in part, by second order non-linearity associated with generating the PLL analog error signal.

10. The method as recited in claim 8 further comprising: supplying a cancellation value corresponding to the polynomial to a second delta sigma modulator;the second delta sigma modulator generating a cancellation control signal based on the cancellation value; andcontrolling a digital to analog converter (DAC) with the cancellation control signal to generate a cancellation voltage; andadding or subtracting the cancellation voltage from the PLL analog error signal.

11. The method as recited in claim 8 further comprising: generating the polynomial using a spur signal representative of the spur in the reference clock signal, a residue signal associated with a residue of the delta sigma modulator, and adaptive coefficients of the polynomial.

12. A phase-locked loop (PLL) comprising: an oscillator;a time-to-voltage converter including a phase and frequency detector (PFD) coupled to receive a feedback signal and a reference clock signal, the-time-to-voltage converter configured to supply an analog error signal indicative of a phase difference between the reference clock signal and the feedback signal;a feedback divider coupled to an output of the oscillator and configured to supply the feedback signal;a spur cancellation circuit configured to receive a dither signal, a residue signal indicative of quantization noise associated with a first delta sigma modulator controlling the feedback divider and to receive a spur signal indicative of a spur that is present in the reference clock signal; andwherein the spur cancellation circuit is configured to generate a cancellation polynomial indicative of noise to be canceled, the noise to be canceled including quantization noise and frequency translated quantization noise.

13. The PLL as recited in claim 12 wherein the frequency translated quantization noise is caused, at least in part, by second order non-linearity associated with the time-to-voltage converter.

14. The PLL as recited in claim 12 further comprising: a digital to analog converter (DAC) coupled to the analog error signal supplied by the time-to-voltage converter;a second delta sigma modulator coupled to receive a cancellation value based on the cancellation polynomial and to supply a control signal to the DAC; andwherein the DAC is responsive to the control signal to add or subtract a cancellation voltage from the analog error signal.

15. The PLL as recited in claim 14 further comprising: a first order difference circuit to generate a first order difference of a second residue from the second delta sigma modulator, the second residue corresponding to second quantization noise; anda multiplier circuit to multiply the first order difference by a scale factor to generate a second cancellation signal to cancel error in a signal that represents the phase difference that is caused by the second quantization noise.

16. The PLL as recited in claim 12 wherein the spur signal is a square wave signal.

17. The PLL as recited in claim 16 wherein the spur cancellation circuit is configured to generate a linear term, a square term, and a cube term of the cancellation polynomial, the linear term, the square term, and the cube term incorporating the square wave signal.

18. The PLL as recited in claim 17 wherein respective coefficients associated with the linear term, the square term, and the cube term are updated adaptively.

19. The PLL as recited in claim 17 wherein the spur cancellation circuit further comprises: a first summing circuit coupled to subtract a dither signal from the residue signal to form a first result;a first multiplier circuit to multiply the first result by a first coefficient and generate a first multiplication result;a second multiplier circuit to multiply the spur signal by another coefficient and generate a second multiplication result;a second summing circuit to sum the first multiplication result and the second multiplication result and form a linear term of the cancellation polynomial;a third summing circuit coupled to the second summing circuit to receive the linear term;a divide circuit to divide the linear term by the first coefficient to generate a division result;a square circuit to square the division result to generate a squared division result;a third multiplier circuit to multiply the squared division result by a second coefficient to generate the square term of the cancellation polynomial and supply the square term to the third summing circuit;a cube circuit to cube the division result to generate a cubed division result; anda third multiplier circuit to multiply the cubed division result by a third coefficient to generate the cube term of the cancellation polynomial and supply the cube term to the third summing circuit.

20. The PLL as recited in claim 12 wherein the spur cancellation circuit further comprises: a first summing circuit coupled to subtract a dither term from the residue signal to form a first result;a first multiplier circuit to multiply the spur signal by a fifth coefficient and generating a first multiplication result;a second summing circuit to sum the first multiplication result and the first result to form a first sum;a second multiplier to multiply the first sum by a first coefficient to form a linear term of the cancellation polynomial;a third summing circuit coupled to receive the linear term;a squaring circuit to square the first sum to generate a first squared term;a third multiplier to multiply the first squared term by a second coefficient to generate a square term of the cancellation polynomial and supply the square term to the third summing circuit;a cube circuit to cube the first sum to generate a first cubed term; anda fourth multiplier to multiply the first cube term by a third coefficient to generate a cube term of the cancellation polynomial and to supply the cube term to the third summing circuit.