Claims
- 1. A linear power amplifier comprising:
a first loop including an input signal; a second loop in communication with the first loop including an error signal and an output signal; a spurious detection receiver having inputs for receiving the error signal, and the output signal, and first and second outputs; and a spurious detection correlator having first and second inputs coupled to the first and second outputs of the spurious detection receiver and outputs for controlling the gain and phase of the second loop.
- 2. A linear power amplifier as in claim 1 in which the spurious detection correlator further comprises an additional output for controlling the delay of the second loop.
- 3. A linear power amplifier as in claim 1 in which the spurious detection correlator further comprises an additional output for controlling a predistorter block in the first loop.
- 4. A linear power amplifier as in claim 1 in which the spurious detection receiver comprises a first receiver circuit for receiving the error signal, an RF switch for receiving the output signal, and a second receiver circuit coupled to an output of the RF switch.
- 5. A linear power amplifier as in claim 4 in which the first and second receiver each comprise:
a mixer having a first input for receiving an RF signal, a second input for receiving a local oscillator signal, and an output; a narrowband IF filter having an input coupled to the output of the mixer, and an output; an IF amplifier having an input coupled to the output of the narrowband IF filter, and an output; and an analog-to-digital converter having an analog input coupled to the output of the IF amplifier, and an output for providing a digital output signal.
- 6. A linear power amplifier as in claim 4 in which the spurious detection receiver further comprises a local oscillator having first and second outputs respectively coupled to the first and second receivers.
- 7. A linear power amplifier as in claim 1 in which the spurious detection correlator comprises:
a digital signal processor having first and second inputs forming the first and second inputs of the spurious detection correlator, and an output; and a digital-to-analog converter having a digital input coupled to the output of the digital signal processor, and first and second outputs forming the outputs of the spurious detection correlator.
- 8. A linear power amplifier as in claim 7 in which the digital-to-analog converter further comprises an additional output for providing delay information.
- 9. A linear power amplifier as in claim 7 in which the spurious detection correlator further comprises an additional digital-to-analog converter coupled to the digital signal processor for providing predistorter control information.
- 10. A linear power amplifier as in claim 7 in which the digital signal processor further comprises an additional output for providing local oscillator control information.
- 11. A linear power amplifier as in claim 7 in which the digital signal processor further comprises an additional output for providing RF switching information.
- 12. A linear power amplifier as in claim 7 in which the digital signal processor comprises:
a first multiplier for combining a first IF signal and a second IF signal; a second multiplier for combining a phase shifted version of the first IF signal and the second IF signal; and means for combining output signals from the first and second multipliers to provide gain and phase control information.
- 13. A linear power amplifier as in claim 12 in which the digital signal processor further comprises:
a first signal splitter for providing two sources of the first IF signal; and a second signal splitter for providing two sources of the second IF signal.
- 14. A linear power amplifier as in claim 12 in which the digital signal processor further provides a quadrature phase shifter for providing the phase shifted version of the first IF signal.
- 15. A linear power amplifier as in claim 12 in which the digital signal processor is further comprises:
a first low pass filter for filtering a first multiplier output signal; and a second low pass filter for filtering a second multiplier output signal.
- 16. A linear power amplifier as in claim 12 in which the digital signal processor further comprises means for combining output signals from the first and second multipliers to provide delay control information.
- 17. A linear power amplifier as in claim 1 in which the first loop comprises a main amplifier.
- 18. A linear power amplifier as in claim 1 in which the first loop comprises a predistorter.
- 19. A linear power amplifier as in claim 1 in which the second loop comprises an error amplifier.
- 20. A linear power amplifier as in claim 1 in which the second loop comprises gain, phase, and delay control blocks.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part and claims the benefit of U.S. patent application Ser. No. 10/052,801, filed Oct. 29, 2001, the contents of which are hereby incorporated by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10052801 |
Oct 2001 |
US |
Child |
10442608 |
May 2003 |
US |