Patent Application
20130058155
The present application claims priority from French Application for Patent No. 1157796 filed Sep. 2, 2011, the disclosure of which is hereby incorporated by reference.
The present disclosure relates to microelectronics, and more specifically to the forming of SRAM-type memories, formed on substrates of a semiconductor material, and especially of silicon type. The present disclosure more specifically relates to memory cells having a read access circuit separate from the write access circuit and thus enabling to optimize their write performance.
Generally, electronic memories are formed of a set of elementary cells, designed to contain binary data. Such cells are arranged in an array, in a given number of lines and columns. Each SRAM contains a “data” bit, the bits being themselves organized in “words”, the external read and write circuits taking part in the definition of this organization. The number of words per line is designated as “mux”, as a reference to data multiplexing.
Conventionally, memory cells are formed by an assembly of different transistors, typically insulated-gate field-effect transistors (MOSFET).
Conventionally, and as illustrated in
Gates 7, 8, 17, 18 of these two transistors are interconnected and connected to midpoint 19, 9 of the other inverter.
The two inverters 2, 12 are controlled by the connection of gates 7, 8, 17, 18 of their transistors to opposite signals originating from bit lines 20, 21. This control is performed via transistors 22, 23 having their gate 25, 26 controlled by a word line 29, which is powered when the cell belongs to the word where the writing must be performed.
All six transistors 5, 15, 6, 16, 25, 26 thus brought together define a so-called “6T” cell having a conventional design.
Given the increase in electronic circuit operating frequencies, and in particular in memory access frequencies, the performance of memory cells needs to be optimized. At the same time, in certain self-contained devices, powered by a limited power source and delivering a voltage which decreases as power is being consumed, there also is a need for memories having as stable a state as possible, despite a decrease in the power supply voltage. Further, given the decrease in electronic component sizes, it is also desirable to do away with the constraints associated with the sizing of the different elements forming a memory, while remaining compatible, as much as possible, with the above-mentioned needs. Finally, to minimize manufacturing costs, it is desirable to limit the number of manufacturing steps by using steps common to all the other devices used in the circuit for the SRAM cell.
To achieve these objects, the present invention provides a SRAM having an optimized write margin (meant as being the capacity to see the bistable state modified), write time, and minimum data retention voltage, independently from the constraints associated with the reading and this, without adding specific manufacturing steps.
Typically, the independence from reading-related constraints may be ensured by the creation of a high-impedance read circuit connected to one, to the other, or to both mid-points of the inverters.
Thus, an aspect of the present invention provides a SRAM, comprising a plurality of 6T-type memory cells, based on six insulated gate field-effect transistors, each cell comprising two inverters connected in antiparallel and two different write and read access circuits, said write circuits comprising two access transistors, each connected to a bit line dedicated to the writing and to a common node of the different inverters, and having their gates connected to a word line, each inverter comprising a transistor of connection to the high level and a transistor of connection to the low level, wherein the gate width of the transistor of connection to the low level is strictly smaller than the gate width of the write access transistors, and the gate width of the transistors of connection to the high level is greater than or equal to the gate width of the transistors of connection to the low level.
According to an embodiment the ratio of the gate width of the transistors of connection to the low level (WPD), divided by the gate width of the write access transistors (WPG) multiplied by the ratio of the gate length of the write access transistors (LPG), divided by the gate width of the transistors of connection to the low level (LPD) of the memory cell is smaller than 0.7.
This ratio, called “beta ratio” of the memory cell hereinafter, combines the width and length features of write access transistors and of transistors of connection to the low level. It is then possible to compensate for a disadvantageous ratio on the gate widths with an adapted ratio on the gate lengths, and conversely, to obtain the desired value by providing a good read stability and a write time to the memory cell.
According to an embodiment, the ratio of the gate width of the transistors of connection to the low level to the gate width of the write access transistors ranges between 0.3 and 0.7, and preferably between 0.3 and 0.5.
According to another embodiment, the ratio of the gate width of the transistors of connection to the high level to the gate width of the transistors of connection to the low level ranges between 1 and 2. In a first case depending on the technology used, this ratio may range between 1 and 1.6, preferably between 1.1 and 1.5, or even close to 1.3. In another case corresponding to another technological choice, this ratio may range between 1.4 and 2, preferably between 1.5 and 1.9, or even close to 1.7.
The implementation and other features and advantages of the present invention will be discussed in detail in the following non-limiting description of a specific embodiment in connection with the accompanying drawings, wherein:
The examples given hereafter are provided as a non-limiting illustration only. The different dimensions and proportions are only given to provide a better understanding of the present invention, and may have been exaggerated and differ from reality to ease the understanding of the present invention.
The layout illustrated in
In the form illustrated in
Central sector 102 of the 6T cell comprises an active area 114 which forms the source and the drain of the other transistor of the inverter, that is, the transistor of connection to the high state, also called “pull-up” transistor 5. Active area 114, which forms a PMOS-type transistor, comprises two different regions. A first region 115 is located in front of the pull-down transistor, and receives gate 117. Region 115 has a width WPU.
A second region 116 is located in front of the pass-gate transistor. It forms an active area 116 of smaller width, to keep a sufficient distance from the active area of the pass-gate transistor, and enable the implantation of shallow insulating trenches (STI, for Shallow Trench Isolation) of proper dimensions.
The other active areas 210, 212, 214 present in the 6T cell are arranged symmetrically with respect to central point 104, to form the other inverter and its access transistor.
The pull-down and pass-gate transistors present in sectors 101 and 103 are formed with the transistor type (N or P) providing the best electric conductivity, to maximize the charge transfer efficiency through the pass-gate transistor. The pull-up transistor is formed with the complementary type (respectively P or N) so that transistors 5 and 6 on the one hand, and transistors 15 and 16 on the other hand, form inverters. Conventionally, the transistors (pass-gate, pull-down) of sectors 101 and 103 are of type N and those of sector 102 (pull-up) are of type P. The transistors types indicated in
It should be noted that the general layout of the memory cell would not be modified on the assumption that, for reasons of electric conductivity, the pass-gate and pull-down transistors are of type P and the pull-up transistors are of type N. Only the connections to the high (Vdd) and low (Gnd) points should be inverted.
At the upper level, the silicon substrate receives gate structures laid on the active areas. Such gate structures may be for example formed by a stacking of oxide and of polysilicon.
Gate structure 120 is laid on active area 110, to form gate 25 of pass-gate transistor 22, extends all the way to cell limit 105, and receives at this level a contact pillar 121, enabling the connection to write bit line BLW. Active areas 112, 114 of the pull-down and pull-up transistors share another gate structure 125, which thus covers these two areas.
Active area 110 of the pass-gate transistor also comprises a contact pillar 127 located at cell limit 106 and intended to be connected to write word line WLW. Active area 112 of pull-down transistor 6 comprises at cell limit 107 a contact pillar 128 conventionally intended to be connected to the low potential node (or GND). In their contact regions, active areas 110, 112 of pass-gate transistor 22 and of pull-down transistor 6 comprises a common pillar 129 astride the two areas 112, 110.
Pull-up transistor 5 comprises at cell limit 107 a contact pillar 131 conventionally connected to the high potential node (or VDD). Narrower region 116 of the pull-up transistor also comprises a larger contact pillar 133, which is partly in contact with active area 116 and partly in contact with layer 225 forming the common gate structure of the pull-up and pull-down transistors of the other cell inverter.
Contact pillar 133 is connected, at a higher metallization level, to pillar 129 forming the common node of pull-down transistor 6 and pass-gate transistor 22, via a metal track 135.
The junctions of active areas 110 and 112 between the gates of the pass-gate and pull-down transistors as well as those of their symmetrical areas 210 and 212, define two internal nodes (IN). The injection of current in the memory cell from the bit line into the internal node is a function of the widths of the active areas as well as of the gate widths of the pass-gate and pull-down transistors. The ratio of voltage VIN between the internal node and the drain of the pull-down transistor to voltage VBL between the source of the pass-gate transistor connected to the bit line and the internal node defines analytic equation:
where RPG is the resistance of the contact between the gate of the pass-gate transistor and active area 110, and RPD is the resistance of the contact between the gate of the pull-down transistor and active area 112. Such resistances are a function of width WPG and WPD of active areas 110 and 112, of a parameter called α′ hereinafter, and of the gate widths of pass-gate transistor LPG and pull-down transistor LPD. The ratio of the two resistances can be expressed as follows:
Reference is made herein to ratio
as the “beta ratio”, while the second term [1+α′(LPG−LPD)2] is called the “gamma” factor. The “beta ratio” is a usual indicator for assessing the performance of SRAM cells.
The Applicants provide a structure enabling to keep the properties of stability of the memory cell while optimizing the memory cell write time by selecting unusual pass-gate, pull-down, and pull-up gate widths, which may even result in “beta ratios” that can be smaller than 1 and on the order of 0.5.
As illustrated in
Similarly, width WPU of the pull-up transistor cannot decrease below a given limit depending on the “technological node”, for reasons linked to the repeatability of the dopant implantation process to form active areas. This limit is on the order of some hundred nanometers for the so-called “65 nm” technological node.
It is also possible to design SRAM cells having different dimensional constraints relative to widths WPG and WPD of active areas 110 and 112, but in which the gate widths of the pass-gate and pull-down transistors are selected to obtain a “beta ratio” smaller than 0.7. In such a configuration, the value of the “beta ratio” is adjusted by means of an adapted sizing of widths LPG and LPD of the gates of the pass-gate and pull-down transistors.
According to a specific embodiment, ratio a between these two widths (WPD/WPG) is thus smaller than 1, and close to 0.3.
Such a sizing of widths WPG and WPD of active areas 110 and 112 makes the memory cell very unstable. The provided advantage is that it can be written into rapidly when the pass-gate transistors are in the on state. However, it is also necessary to make the memory cell very stable when it retains information, that is, when the pass-gate transistors are in the off state.
For this purpose, the ratio of width WPU of the pull-up transistor to width WPD of the pull-down transistor is selected so that current Ion is as close as possible in the two transistors.
Thereby, on the one hand, the bistable state switching time is decreased, which results in a decrease of the time necessary for the writing, or write time. On the other hand, the stability in case of a lowering of the power supply voltage, which criterion is generally called “retention noise margin”, is increased.
For this purpose, width WPU of the pull-up transistor is selected to be greater than or equal to width WPD of the pull-down transistor, with a ratio between these two widths which is selected according to the conductivity of the transistor types, conventionally linked to the nature and to the concentration of the dopants which are used for these two transistors, as well as to the mobility of the charge carriers and to other physical parameters.
In practice, the selection of the transistor type, and thus of the conductivity ratio, may be imposed by the design of the transistors of the logic gates of the other circuits associated with the memory, which are preferably formed during common steps.
In other words, according to the technological choices made for the components comprising the memory, the optimal ratio between WPU and WPD can be optimized. On the assumption of the use of a minimum number of manufacturing steps implying the use of a single family of transistors (for example, “Low-VT”), a value on the order of 1.7±0.3 will be considered as optimal in a technology of “32 nm CMOS Low Power (LP)” type. Still as an example and on the assumption of the use of a single family of transistors, a value on the order of 1.3±0.3 will be considered as optimal in a technology of “32 nm CMOS High Performance (HP)” type implementing stress effects.
For the sizing of the different active areas, account will also be taken of the fact that the pull-up transistor must not come too close to the pass-gate transistor, and that a distance D between the two corresponding active areas which is sufficient for the implantation of the insulating trenches must be kept.
As an example, in the context of a memory formed according to the 32-nanometer technological node, height HT of a 6T cell is on the order of 250 nanometers, for a width WT on the order of 900 nanometers. Half the width difference ½.(WPG−WPD) between the pass-gate transistor and the pull-down transistor is on the order of a few tens of nanometers, and typically from 70 to 80 nanometers. Distance D separating the nodes closest to active areas 110, 114 of the pass-gate and pull-up transistors is of the same order. Of course, such distances and other dimensions are not limiting, they correspond to a given technology, and may of course be declined according to the used technological node and to other external constraints.
As appears from the foregoing, the memory cell thus formed has the combined advantage of improving the write capacity of the cell, which translates as a decrease in the time required for the writing, and of increasing the write margin. Similarly, the bistable structure formed by the two inverters associated in the 6T cell has a better stability in case of a lowering of the power supply voltage, which criterion is generally called “retention noise margin”.
Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1157796 | Sep 2011 | FR | national |
