This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2012-0036509 filed on Apr. 9, 2012, the subject matter of which is hereby incorporated by reference.
Embodiments of the inventive concept relate to solid state drive(s) (SSD), and more particularly, to SSD having a redundant array of independent disks (RAID) architecture.
Hard disk drive(s) (HDD) have historically been used as a data storage mechanism(s) in many different type of electronic devices. Recently, however, HDD have been replaced by SSD. Unlike HDD, SSD have no moving mechanical parts, but instead are implemented with a plurality of nonvolatile memory devices (e.g., flash memory devices).
SSD enjoy many advantages over HDD. For example, due to the absence of moving mechanical parts, SSD do not generate heat and noise like HDD. In addition, SSD generally provide faster access rates, higher data storage density, and increased stability.
More recently, SSD have been provide with a redundant array of independent disks (RAID) architecture to further increase operating speed and stability. SSD having a RAID architecture usually include a plurality of flash memory devices, and input data is distributed over the plurality of flash memory devices. SSD having a RAID architecture is able to increase operating speed by accessing the plurality of flash memory devices in parallel (or simultaneously). In addition, SSD having a RAID architecture are able to store parity data along with input data. Therefore, although physical errors occur during the writing of data to and/or reading of data from the plurality of flash memory devices, SSD having a RAID architecture are able to recover errant (or “damaged”) data using the co-stored parity data. As such, SSD having a RAID architecture offer increased data reliability or stability.
Unfortunately, different physical pages of the various flash memory devices operate with different error rates. Therefore, the data recovery rate of a particular SSD having a RAID architecture will vary in accordance with the physical pages of the plurality of flash memory devices. As such, stability of a SSD having a RAID architecture will often be determined by the lowest (worst) data recovery rate among a plurality of data recovery rates respectively associated with different physical pages of the plurality of flash memory devices.
Certain embodiments of the inventive concept provide a solid state drive (SSD) having a RAID architecture with increased overall data recovery rates. Other embodiments of the inventive concept provide an electronic device including this type of SSD.
According to certain embodiments of the inventive concept, a solid state drive (SSD) is provided that includes; 1st through Nth non-volatile memory devices each including a memory cell array, the memory cell array including a plurality of physical pages, and a redundant array of independent disks (RAID) controller configured to perform a parity operation on 1st through (N−1)th physical page data to generate Nth physical page data, determine a physical page group including 1st through Nth physical pages respectively selected from the 1st through Nth non-volatile memory devices, such that at least two of the 1st through Nth physical pages have different bit error rates, and store the 1st through Nth physical page data in the 1st through Nth physical pages, respectively.
According to certain embodiments of the inventive concept, a solid state drive (SSD) is provided that includes; 1st through Nth non-volatile memory devices, each including a memory cell array, each memory cell array including a plurality of physical pages, and each of the plurality of physical pages including first level through Mth level logical pages, where N and M are each integers greater than one, and a redundant array of independent disks (RAID) controller configured to perform a parity operation on 1st through (N−1)th logical page data to generate Nth logical page data, determine a physical page group including 1st through Nth physical pages respectively selected from the 1st through Nth non-volatile memory devices, determine a logical page group including 1st through Nth logical pages respectively selected from the 1st through Nth physical pages, such that at least two of the 1st through Nth logical pages are of different levels, and store the 1st through Nth logical page data in the 1st through Nth logical pages, respectively.
According to certain embodiments of the inventive concept, a method of programming a solid state drive (SSD) is provided that includes; generating 1st through the (N−1)th physical page data by buffering data received from a host, generating an Nth physical page data by performing the parity operation on the 1st through the (N−1)th physical page data, determining a physical page group to include the 1st through Nth physical pages, such that at least two of the 1st through Nth physical pages have different bit error rates, and storing the 1st through Nth physical page data in 1st through Nth physical pages of a memory cell array, respectively.
Illustrative, non-limiting embodiments of the inventive concept (hereafter, collectively and individually, “example embodiments”) will be described hereafter with reference to the accompanying drawings.
Various example embodiments will be described more fully with reference to the accompanying drawings. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present inventive concept to those skilled in the art. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements and features.
It will be understood that, although the terms first (1st), second (2nd), etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present inventive concept. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As further background to the subject inventive concept, published U.S. patent application Ser. Nos. 13/236,249 and 13/236,176 are hereby incorporated by reference. A more complete understanding of bit error rate (BER) imbalance in a flash memory device may be had by review of these documents, for example.
Referring to
The SSD 1000 may be connected to a host, such as a laptop computer, a personal computer, a mobile device, a digital camera, etc., to be used as a storage device.
Each of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n includes a memory cell array including a plurality of physical pages.
Due to variations in the manufacturing process(es) used to fabricate each one of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n, the plurality of physical pages included in each constituent memory cell array may have different bit error rates (BERs). Differences between bit error rates (BERs) of the plurality of physical pages will be described in some additional detail hereafter with reference to
Each one of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n is capable of performing program operations, read operations, and erase operations under control of the RAID controller 1200.
The RAID controller 1200 is respectively coupled to the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n via 1st through Nth channels CH1, CH2, . . . , CHn.
The RAID controller 1200 may be used to buffer “input data” received from a host in units of a defined physical page in order to generate 1st through (N−1)th physical page data PPDi_1˜PPDi_(n−1). Here, the variable “i” is a positive integer. The RAID controller 1200 may also be used to perform a parity operation on the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1) to generate Nth physical page data PPDi_n, which is a parity data for the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). In the illustrated example, the 1st through Nth physical page data PPDi_1˜PPDi_n constitute a “parity group”. In its operation the RAID controller 1200 serially generates parity groups.
The RAID controller 1200 may also be used to generate (or determine) a “physical page group” including 1st through Nth physical pages. The 1st through Nth physical pages are respectively selected from the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n, such that at least two of the 1st through Nth physical pages have different bit error rates.
The RAID controller 1200 stores the 1st through Nth physical page data PPDi_1˜PPDi_n, included in a parity group in the 1st through Nth physical pages included in the physical page group, respectively. For example, the RAID controller 1200 may store the 1st physical page data PPDi_1 in the 1st physical page selected from the 1st non-volatile memory device 1100-1, store the 2nd physical page data PPDi_2 in the 2nd physical page selected from the 2nd non-volatile memory device 1100-2, and store the Nth physical page data PPDi_n in the Nth physical page selected from the Nth non-volatile memory device 1100-n.
The 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n included in the SSD 1000 of
Referring to
The 3D flash memory cell array 1110 may be formed on a substrate in a three-dimensional structure (or vertical structure). In a flash memory cell array having a two-dimensional structure (or horizontal structure), memory cells are formed in a planar arrangement parallel to a substrate. However, in the 3D flash memory cell array 1110, a plurality of planar arrangements of memory cells may be formed (or stacked) perpendicular to the substrate. The 3D flash memory cell array 1110 may include a plurality of physical pages coupled to a plurality of word lines WLs formed in order on the substrate such that respective “heights” defined by the plurality of word lines WLs in the memory cell array.
The 3D flash memory cell array 1110 may include a plurality of memory blocks BLK1, BLK2, . . . , BLKz, wherein the variable “z” is a positive integer. Each of the plurality of memory blocks BLK1, BLK2, . . . , BLKz may include a plurality of physical pages. Each of the plurality of physical pages may include a plurality of memory cells. The 3D flash memory cell array 1110 may perform a program operation and a read operation by a unit of a physical page and perform an erase operation by a unit of a memory block.
The data input/output (I/O) circuit 1120 may be connected to the 3D flash memory cell array 1110 through a plurality of bit lines BLs. The data I/O circuit 1120 may receive data (DATA) from the RAID controller 1200 and output data (DATA) read from the 3D flash memory cell array 1110 to the RAID controller 1200.
The address decoder 1130 may be connected to the 3D flash memory cell array 1110 through the plurality of word lines WLs, a string selection line SSL, and a ground selection line GSL. The address decoder 1130 may receive an address ADDR from the RAID controller 1200 and select a word line.
The control logic 1140 may control the program operation, the read operation, and the erase operation of the flash memory device 1100 by controlling the data I/O circuit 1120 and the address decoder 1130 based on a control signal CMD received from the RAID controller 1200. For example, during a program operation, the control logic 1140 may control the address decoder 1130 to allow a program voltage to be provided to a selected word line, and control the data I/O circuit 1120 to allow data to be programmed in memory cells connected to the selected word line.
Each of the plurality of memory blocks BLK1, BLK2, . . . , BLKz included in the 3D flash memory cell array 1110 of
Referring to
When the gate electrode layer and the insulation layer are vertically patterned, a V-shaped pillar may be formed. The pillar may penetrate the gate electrode layer and the insulation layer to be connected to the substrate. The outer portion “O” of the pillar may be configured with a channel semiconductor, and the inner portion “I” of the pillar may be configured with an insulation material such as silicon oxide.
Referring still to
Referring collectively to
When vertical patterning is performed to form the pillar, the width of the pillar may be reduced as it approaches the bottom portion of the pillar (i.e., Wt>Wb). Accordingly, the pillar will have a V-shaped cylinder defined by an inclination angle θ. Due to the width difference between an upper portion of the pillar and a lower portion of the pillar, the circumference of the pillar will vary with the inclination angle θ and height above the substrate. As illustrated in
Further, the respective circumferences “P1” and “P2” of the pillar crossing the lower and upper planes may be expressed by the equations: [P1=2πa] and [P2=2πc=2π(a+b)=2πa+2πh(tan θ)=P1+2πh(tan θ)].
Hence, as shown above, the circumference of the pillar will vary with the height from the substrate. Accordingly, when the gate electrode layer is formed to have the same thickness, a facing area of the gate electrode layer may vary with the height. Here, the facing area may signify an area of the gate electrode layer facing the outer portion “O” of the pillar.
The gate electrode layer may be used as a gate electrode of a cell transistor, and the outer portion “O” of the pillar may be used as a channel region of the cell transistor. In this case, the circumference P1 or P2 of the pillar and the thickness “h” of the gate electrode layer may determine the aspect ratio (W/L) of the cell transistor. A drain current “Id” of a MOS transistor may be in proportion to the channel width “W” and may be in inverse proportion to the channel length “L”, as given by the equation: Id=α(W/L)(Vg−Vt)Vd, where “a” is a proportionality constant, “Vg” is a gate voltage, “Vd” is a drain voltage, and “Vt” is a threshold voltage.
Accordingly, cell transistors formed at different heights may have different current characteristics. That is, when the thickness of the gate electrode layer is equal, the current characteristics of the cell transistor may vary according to the height. For this reason, although an equal program or read voltage is applied to the word lines WL1 to WL8, the channel current may vary according to the height of the word line. This means that the threshold voltage of the cell transistor will vary with height, and height may be defined as a function of word line disposition. Further, if the threshold voltage of cell transistors changes as a function of location within the 3D memory cell array, the bit error rate (BER) of respective physical pages will also vary according to word line.
Referring again to
Referring to
The string selection transistor SST may be connected to string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the bit lines BL1 to BL3, and the ground selection transistor GST may be connected to the common source line CSL.
Referring again to
Referring to
Memory cells included in the same plane and coupled to a word line of the same height may constitute a physical page.
The program order among the planes may vary. For example, the program operation may be sequentially performed from the 1st plane PLANEa to the 3rd plane PLANEc. In each plane, the program operation may be sequentially performed from a physical page coupled to the 1st word line WL1 to a physical page coupled to the 8th word line WL8. Alternatively, the program operation may be sequentially performed from a physical page coupled to the 8th word line WL8 to a physical page coupled to the 1st word line WL1. As illustrated in
Referring again to
The host interface 1250 may exchange data with the host. The host interface 1250 may provide an interface with the SSD 1000 according to a protocol of the host. The host interface 1250 may communicate with the host via (e.g.,) a universal serial bus (USB), a small computer system interface (SCSI), a PCI express, ATA, a parallel ATA (PATA), a serial ATA (SATA), or a serial attached SCSI (SAS). Moreover, the host interface 1250 may perform disk emulation whereby the host may recognize the SSD 1000 as a legacy hard disk drive (HDD).
The memory interface 1260 may be used to respectively exchange data with the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n via the 1st through Nth channels CH1, CH2, . . . , CHn.
The buffer memory 1220 may be used to temporarily store data to be programmed or data to be provided to the host. For example, the buffer memory 1220 may buffer data, received from the host on a physical page basis (i.e., according to the defined physical page as a data transfer unit) to thereby generate the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). The buffer memory 1220 may repeatedly be used to buffer data corresponding to (N−1) physical pages and outputting the buffered data as the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1), where “i” represents each of the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1) as output from the buffer memory 1220.
The parity generation unit 1230 may be used to generate the Nth physical page data PPDi_n by performing the parity operation on the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). Using this approach, the Nth physical page data PPDi_n will be parity data for the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). The 1st through Nth physical page data PPDi_1˜PPDi_n may constitute a “parity group”. In certain embodiments, a parity operation may be accomplished using one or more logic operations such as the exclusive OR (XOR) operation. Assuming the use of an XOR operation, the parity generation unit 1230 may generate the Nth physical page data PPDi_n by performing an exclusive OR (XOR) operation on the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1).
The 1st through Nth physical page buffers 1240-1, 1240-2, . . . , 1240-n may store the 1st through Nth physical page data PPDi_1˜PPDi_n, which are included in the same parity group, respectively. For example, as illustrated in
The control unit 1210 may be used to determine the physical page group including the 1st through Nth physical pages. The 1st through Nth physical pages are selected from the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n, respectively, such that at least two of the 1st through Nth physical pages have different bit error rates (BERs).
As described above with reference to
In certain example embodiments, the control unit 1210 may be used to select a 1st word line having a 1st height in the 3D memory cell array and a 2nd word line having a 2nd height in the 3D memory cell array different from the 1st height from among the plurality of word lines. Further, the control unit 1210 may be used to select one of a physical page coupled to the 1st word line and a physical page coupled to the 2nd word line from each of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n to define the physical page group. In this case, at least one of the 1st through Nth physical pages included in the physical page group will be coupled to the 1st word line having the 1st height and remainder of the 1st through Nth physical pages included in the physical page group may be coupled to the 2nd word line having the 2nd height.
The control unit 1210 may be used to control the memory interface 1260 to store the 1st through Nth physical page data PPDi_1˜PPDi_n, which are stored in the 1st through Nth physical page buffers 1240-1, 1240-2, . . . , 1240-n, respectively, in the 1st through Nth physical pages, respectively, included in the physical page group.
As described above, the RAID controller 1200 may be used to receive “write data” (i.e., input data to be written to the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n) from the host, generate a parity data “associated with” (i.e., derived from the write data using one or more conventional parity data generating techniques) the write data, and then store the write data together with the parity data in a dispersed manner “across” the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n.
Therefore, although certain errors occur on some of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n such that some of the data stored in the 1st through Nth physical page data PPDi_1˜PPDi_n is damaged, the RAID controller 1200 may nonetheless recover the damaged data by performing the parity operation on undamaged data included in the parity group.
However, in circumstances where more than a given threshold number of data among the 1st through Nth physical page data PPDi_1˜PPDi_n included in a parity group are damaged, the RAID controller 1200 may not be able to recover the damaged data using the parity operation. Herein, the term “threshold number” will be understood by those skilled in the art as being determined according to the particular parity operation being used.
The data recovery rate of a SSD may be determined by the number of times the SSD 1000 is not able to recover damaged data. Therefore, if the 1st through Nth physical page data PPDi_1˜PPDi_n included in a parity group are stored in physical pages all of which have a high bit error rate (BER), the data recovery rate of a SSD may decrease.
As described above, the physical pages included in the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n may have different bit error rates (BERs) according to the word lines WLs to which the physical pages are coupled. Therefore, if the 1st through Nth physical page data PPDi_1˜PPDi_n included in the same parity group are stored in physical pages coupled to a word line having a given height, the data recovery rate imbalance may exist between parity groups, such that the number of times the SSD 1000 is not able to recover damaged data is increased.
However, SSD according to certain example embodiments of the inventive concept may operate in such a manner that a physical page group including the 1st through Nth physical pages is defined, such that at least two (2) of the 1st through Nth physical pages included in the physical page group are respectively coupled to two (2) word lines having different heights in the 3D memory cell array. Further, SSD according to certain example embodiments of the inventive concept may store the 1st through Nth physical page data PPDi_1˜PPDi_n included in the parity group in the 1st through Nth physical pages included in the physical page group, respectively. Therefore, the data recovery rate imbalance between parity groups may be reduced, and the number of times SSD according to certain example embodiments of the inventive concept may not be able to recover damaged data may also be reduced. As such, SSD according to certain example embodiments of the inventive concept will increase overall stability.
It is assumed in
Hereinafter, operation of the SSD 1000 will be described with reference to
The buffer memory 1220 may buffer data, which are received from the host, by a unit of a physical page and generate the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). The parity generation unit 1230 may generate the Nth physical page data PPDi_n by performing the parity operation on the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). The 1st through Nth physical page data PPDi_1˜PPDi_n may constitute a parity group. The 1st through Nth physical page buffers 1240-1, 1240-2, . . . , 1240-n may store the 1st through Nth physical page data PPDi_1˜PPDi_n, which are included in the parity group, respectively.
The control unit 1210 may determine the physical page group including the 1st through Nth physical pages. The 1st through Nth physical pages may be selected from the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n, respectively, such that at least two of the 1st through Nth physical pages have different bit error rates (BERs). For example, the control unit 1210 may determine a plurality of the physical page groups by selecting one physical page in an order from a physical page coupled to a lowest word line in the 3D memory cell array to a physical page coupled to a highest word line in the 3D memory cell array from at least one of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n and selecting one physical page in an order from a physical page coupled to the highest word line in the 3D memory cell array to a physical page coupled to the lowest word line in the 3D memory cell array from a remainder of the 1st through Nth non-volatile memory devices 1100-1, 1100-2, . . . , 1100-n.
As illustrated in
In this case, the control unit 1210 may determine a 1st physical page group PPG1 by selecting a physical page coupled to a 1st word line WL1 from the 1st, the 2nd and the 3rd non-volatile memory devices 1100-1, 1100-2 and 1100-3 and selecting a physical page coupled to an 8th word line WL8 from the 4th non-volatile memory device 1100-4, and then store the 1st through 4th physical page data PPD1—1˜PPD1—4, which are included in a 1st parity group (PARITY GROUP 1) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1.
Then, the control unit 1210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st, the 2nd and the 3rd non-volatile memory devices 1100-1, 1100-2 and 1100-3 and selecting a physical page coupled to a 7th word line WL7 from the 4th non-volatile memory device 1100-4, and then store the 1st through 4th physical page data PPD2—1˜PPD2—4, which are included in a 2nd parity group (PARITY GROUP 2) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2.
In a similar way, the control unit 1210 may determine an 8th physical page group PPG8 by selecting a physical page coupled to the 8th word line WL8 from the 1st, the 2nd and the 3rd non-volatile memory devices 1100-1, 1100-2 and 1100-3 and selecting a physical page coupled to the 1st word line WL1 from the 4th non-volatile memory device 1100-4, and then store the 1st through 4th physical page data PPD8—1˜PPD8—4, which are included in an 8th parity group (PARITY GROUP 8) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
In other example embodiments, as illustrated in
In this case, the control unit 1210 may determine the 1st physical page group PPG1 by selecting a physical page coupled to the 1st word line WL1 from the 1st and the 2nd non-volatile memory devices 1100-1 and 1100-2 and selecting a physical page coupled to the 8th word line WL8 from the 3rd and the 4th non-volatile memory devices 1100-3 and 1100-4, and then store the 1st through 4th physical page data PPD1—1˜PPD1—4, which are included in the 1st parity group (PARITY GROUP 1) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1. After that, the control unit 1210 may determine the 2nd physical page group PPG2 by selecting a physical page coupled to the 2nd word line WL2 from the 1st and the 2nd non-volatile memory devices 1100-1 and 1100-2 and selecting a physical page coupled to the 7th word line WL7 from the 3rd and the 4th non-volatile memory devices 1100-3 and 1100-4, and then store the 1st through 4th physical page data PPD2—1˜PPD2—4, which are included in the 2nd parity group (PARITY GROUP 2) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2.
In similar manner, the control unit 1210 may determine the 8th physical page group PPG8 by selecting a physical page coupled to the 8th word line WL8 from the 1st and the 2nd non-volatile memory devices 1100-1 and 1100-2 and selecting a physical page coupled to the 1st word line WL1 from the 3rd and the 4th non-volatile memory devices 1100-3 and 1100-4, and then store the 1st through 4th physical page data PPD8—1˜PPD8—4, which are included in the 8th parity group (PARITY GROUP 8) and stored in the 1st through 4th physical page buffers 1240-1, 1240-2, 1240-3 and 1240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
As described above, SSD according to the embodiments of the inventive concept may determine a physical page group including the 1st through Nth physical pages, such that at least two of the 1st through Nth physical pages included in the physical page group are coupled to word lines having different heights in the 3D memory cell array, and then store the 1st through Nth physical page data PPDi_1˜PPDi_n included in a given parity group in the 1st through Nth physical pages included in the physical page group, respectively. As a result, the data recovery rate imbalance between parity groups is decreased, and the number of times the SSD 1000 may not be able to recover damaged data is also decreased. In other words, SSD according to the embodiments of the inventive concept will operate with increased overall stability over analogous conventional SSD.
Referring to
The method of programming data in a SSD described above with reference to
As illustrated in
Referring to
The SSD 2000 may be connected to a host, such as a laptop computer, a personal computer, a mobile device, a digital camera, etc., to be used as a storage device.
Each of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n includes a memory cell array that have a plurality of physical pages.
Single bit data or multi bit data, i.e., data of two or more bits, may be stored in one memory cell. A memory cell storing single bit data is called as a single-level cell (SLC) and a memory cell storing multi bit data is called as a multi-level cell (MLC) or a multi bit cell.
The memory cell array included in each of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n includes multi-level cells storing M-bit data, where “M” is an integer greater one. Therefore, each of the plurality of physical pages included in the memory cell array includes M logical pages. Hereinafter, the M logical pages included in a physical page will be called as 1st level through Mth level logical pages. The 1st level logical page represents a group of data that are stored in a least significant bit (LSB) of the multi-level cells included in one physical page. Similarly, the Mth level logical page represents a group of data that are stored in a most significant bit (MSB) of the multi-level cells included in one physical page.
According to a manufacturing process, the 1st level through the Mth level logical pages included in a physical page may have different bit error rates (BERs) from each other. The differences between bit error rates (BERs) of the 1st level through the Mth level logical pages will be described later with reference to
As before, the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n are able to perform program operations, read operations, and erase operations under control of the RAID controller 2200.
The RAID controller 2200 is respectively coupled to the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n via 1st through Nth channels CH1, CH2, . . . , CHn.
The RAID controller 2200 buffers data, which are received from a host, by a unit of a logical page and generates 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The RAID controller 2200 performs a parity operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1) to generate Nth logical page data LPDi_n, which is a parity data for the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. The RAID controller 2200 repeatedly generates a plurality of the parity groups, and i represents a serial number of the parity groups.
The RAID controller 2200 determines a physical page group including 1st through Nth physical pages. The 1st through Nth physical pages are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively.
The RAID controller 2200 determines a logical page group including 1st through Nth logical pages. The 1st through Nth logical pages are selected from the 1st through Nth physical pages, respectively, such that at least two of the 1st through Nth logical pages are of different levels. In some example embodiments, each of the 1st through Nth logical pages included in the same logical page group may be one of two different levels.
The RAID controller 2200 stores the 1st through Nth logical page data LPDi_1˜LPDi_n, which are included in the parity group, in the 1st through Nth logical pages, respectively, included in the logical page group. For example, the RAID controller 2200 may store the 1st logical page data LPDi_1 in the 1st logical page selected from the 1st physical page included in the 1st non-volatile memory device 2100-1, store the 2nd logical page data LPDi_2 in the 2nd logical page selected from the 2nd physical page included in the 2nd non-volatile memory device 2100-2, and store the Nth logical page data LPDi_n in the Nth logical page selected from the Nth physical page included in the Nth non-volatile memory device 2100-n.
The 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n included in the SSD 2000 of
Referring to
The two-dimensional (2D) flash memory cell array 2110 may be formed on a substrate in a two-dimensional (or horizontal) structure. In a flash memory cell array having a 2D or horizontal structure, memory cells may be formed in a direction parallel to a substrate. The 2D flash memory cell array 2110 may include a plurality of physical pages coupled to a plurality of word lines WLs formed in order on the substrate such that heights of the plurality of word lines are the same.
The 2D flash memory cell array 2110 may include a plurality of memory blocks BLK1, BLK2, . . . , BLKz. Here, z is a positive integer. Each of the plurality of memory blocks BLK1, BLK2, . . . , BLKz may include a plurality of physical pages 2111. Each of the plurality of physical pages 2111 may include a plurality of multi-level cells. Each of the plurality of multi-level cells may store M-bit data. The 2D flash memory cell array 2110 may perform a program operation and a read operation by a unit of a physical page and perform an erase operation by a unit of a memory block.
The data I/O circuit 2120 may be connected to the 2D flash memory cell array 2110 through a plurality of bit lines BLs. The data I/O circuit 2120 may receive data (DATA) from the RAID controller 2200 and output data (DATA) read from the 2D flash memory cell array 2110 to the RAID controller 2200.
The address decoder 2130 may be connected to the 2D flash memory cell array 2110 through the plurality of word lines WLs, a string selection line SSL, and a ground selection line GSL. The address decoder 2130 may receive an address ADDR from the RAID controller 2200 and select a word line.
The control logic 2140 may control the program operation, the read operation, and the erase operation of the flash memory device 2100 by controlling the data I/O circuit 2120 and the address decoder 2130 based on a control signal CMD received from the RAID controller 2200. For example, in the program operation, the control logic 2140 may control the address decoder 2130 to allow a program voltage to be provided to a selected word line, and control the data I/O circuit 2120 to allow data to be programmed in memory cells connected to the selected word line.
Each of the plurality of memory blocks BLK1, BLK2, . . . , BLKz included in the 2D flash memory cell array 2110 of
Referring to
The string selection transistor SST may be connected to the string selection line SSL, the plurality of multi-level cells MC1 to MC64 may be connected to the plurality of word lines WL1 to WL64, and the ground selection transistor GST may be connected to the ground selection line GSL. The string selection transistor SST may be connected to bit lines BL1 to BL2048 and the ground selection transistor GST may be connected to a common source line CSL.
A plurality of multi-level cells may be connected to one word line (e.g., WLk, wherein “k” is a positive integer less than or equal to 64 in the particular example). A set of the multi-level cells connected to one word line is defined as a “physical page”.
The multi-level cells MC1 to MC64 included in the 2D flash memory cell array 2110 may store M-bit data.
The single-level cell (SLC) may have an erase state and a program state according to a threshold voltage. On the other hand, the multi-level cell (MLC) may have an erase state and a plurality of program states according to threshold voltages.
Since the 2D flash memory cell array 2110 includes multi-level cells storing M-bit data, each of the plurality of physical pages included in the 2D flash memory cell array 2110 may include M logical pages, that is, the 1st level through the Mth level logical pages. For example, when the 2D flash memory cell array 2110 includes multi-level cells storing two bits, one physical page included in the 2D flash memory cell array 2110 may have two logical pages. When the 2D flash memory cell array 2110 includes multi-level cells storing three bits, one physical page included in the 2D flash memory cell array 2110 may have three logical pages. When the 2D flash memory cell array 2110 includes multi-level cells storing four bits, one physical page included in the 2D flash memory cell array 2110 may have four logical pages. Here, the 1st level logical page represents a group of data that are stored in a least significant bit (LSB) of the multi-level cells included in one physical page. Similarly, the Mth level logical page represents a group of data that are stored in a most significant bit (MSB) of the multi-level cells included in one physical page.
When 2-bit data is to be stored, the MLC will have four states. In this case, referring to
Data read from the 2D flash memory cell array 2110 may exhibit different bit error rate (BER) according to the “levels” of the logical pages in a physical page. As the level of a logical page increases, a bit error rate (BER) may increase by a factor of two (2). For example, if a number of fail bits is identical in each reading level, the bit error rate (BER) of the 1st level logical page PAGE1 (or LSB) may be 1 and the bit error rate (BER) of the 2nd level logical page PAGE2 (or MSB) may be 2.
When 4-bit data is to be stored, the MLC will have sixteen (16) states. In this case, referring to
Data read from the 2D flash memory cell array 2110 may exhibit different bit error rate (BER) according to the level of constituent logical pages. As a level of a logical page increases, its bit error rate (BER) may increase by a factor of two. For example, if the number of fail bits is identical in each reading level, the bit error rate (BER) of the 1st level logical page PAGE1 may be 1, the bit error rate (BER) of the 2nd level logical page PAGE2 may be 2, the bit error rate (BER) of the 3rd level logical page PAGE3 may be 4, and the bit error rate (BER) of the 4th level logical page PAGE4 may be 8. If M-bit data is stored in one MLC, the bit error rate (BER) for each of N logical pages may be 1:2:2̂2: . . . :2̂(M−1).
Referring again to
The host interface 2250 may be used to exchange data with the host. The host interface 2250 may provide an interface with the SSD 2000 according to one or more protocol(s) recognized by the host. For example, the host interface 2250 may communicate with the host via a universal serial bus (USB), a small computer system interface (SCSI), a PCI express, ATA, a parallel ATA (PATA), a serial ATA (SATA), and a serial attached SCSI (SAS). Moreover, the host interface 2250 may perform disk emulation whereby the host is able to recognize the SSD 2000 as a legacy hard disk drive (HDD).
The memory interface 2260 may be used to respectively exchange data with the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n via the 1st through Nth channels CH1, CH2, . . . , CHn.
The buffer memory 2220 may be used to temporarily store data to be programmed or data to be provided to the host. For example, the buffer memory 2220 may buffer data, which are received from the host, by a unit of a logical page and generate the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The buffer memory 2220 may repeatedly perform buffering data corresponding to (N−1) logical pages and outputting the buffered data as the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). Here, the variable “i” represents a serial number of the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1) output by the buffer memory 2220.
The parity generation unit 2230 may be used to generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The Nth logical page data LPDi_n may be a parity data for the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. In some example embodiments, the parity operation may be an exclusive OR (XOR) operation. In this case, the parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing an exclusive OR (XOR) operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1).
The 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n may store the 1st through Nth logical page data LPDi_1˜LPDi_n, which are included in the same parity group, respectively, M times in consecutive order. That is, the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n may receive the 1st through Nth logical page data LPDi_1˜LPDi_n, respectively, M times and store the 1st through Nth logical page data LPDi_1˜LPDi_n, respectively, M times in the received order.
Each of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n may include 1st through Mth logical page buffers. In this case, as illustrated in
The level mix unit 2270 may select at least one of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n and change an order of the M logical page data stored in each of the selected physical page buffers. In some example embodiments, the level mix unit 2270 may reverse the order of the M logical page data stored in each of the selected physical page buffers.
In some example embodiments, as illustrated in
In other example embodiments, as illustrated in
The control unit 2210 may determine the physical page group including the 1st through Nth physical pages. The 1st through Nth physical pages may be selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively. The control unit 2210 may control the memory interface 2260 to store the M logical page data, which are stored in the 1st through Mth logical pages LPB1, LPB2, LPB3 and LPB4 of each of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n, in the 1st level through the Mth level logical pages included in each of the 1st through Nth physical pages, respectively. For example, the control unit 2210 may store the M logical page data, which are stored in the 1st through Mth logical pages LPB1, LPB2, LPB3 and LPB4 of the Jth physical page buffers 2240-j, in the 1st level through the Mth level logical pages included in the Jth physical page that is selected from the Jth non-volatile memory device 2100-j, respectively. Here, “J” is a positive integer less than or equal to “N”.
As described above, the RAID controller 2200 receives write data from the host, generates parity data from the write data, and stores the write data together with the parity data in a dispersed manner across the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n. Therefore, although certain errors occur on some of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n such that some of the 1st through Nth logical page data LPDi_1˜LPDi_n included in a parity group are damaged, the RAID controller 2200 may recover the damaged data by performing the parity operation on undamaged data included in the parity group.
However, when more than a threshold number of data among the 1st through Nth logical page data LPDi_1˜LPDi_n included in a parity group are damaged, the RAID controller 2200 may not be able to recover the damaged data using the parity operation. As before, the threshold number of data will be determined by the particular the parity operation being used.
Data recovery rate of a SSD may be determined by the number of times the SSD 2000 is not able to recover damaged data. Therefore, if the 1st through Nth logical page data LPDi_1˜LPDi_n included in a parity group are stored in logical pages all of which have a high bit error rate (BER), the data recovery rate of a SSD may decrease.
As described above, the logical pages included in a physical page of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n may have different bit error rates (BERs) according to levels of logical pages in a physical page. Therefore, if the 1st through Nth logical page data LPDi_1˜LPDi_n included in the same parity group are stored in logical pages of the same level, the data recovery rate imbalance may exist between parity groups, such that the number of times the SSD 2000 is not able to recover damaged data may increase.
However, according to the SSD 2000, the level mix unit 2270 may select at least one of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n and reverse an order of the M logical page data stored in each of the selected physical page buffers before the control unit 2210 stores the M logical page data, which are stored in the 1st through Mth logical pages LPB1, LPB2, LPB3 and LPB4 of each of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n, in the 1st level through the Mth level logical pages included in each of the 1st through Nth physical pages, respectively. Therefore, the 1st through Nth logical page data LPDi_1˜LPDi_n included in the same parity group may be stored in a dispersed manner across the logical pages having a relatively high bit error rate (BER) and the logical pages having a relatively low bit error rate (BER). As a result, the data recovery rate imbalance between parity groups is decreased, and the number of times the SSD 2000 may not be able to recover damaged data is also decreased. As such, the SSD 2000 provides increased overall stability.
As described above, the 2D flash memory cell array 2110 included in each of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n may include a plurality of physical pages coupled to a plurality of word lines WLs formed in order on the substrate such that the height of the plurality of word lines is the same.
In some example embodiments, the control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that the 1st through Nth physical pages are coupled to a word line of the same order.
It is illustrated in
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data, which are received from the host, by a unit of a logical page and generate the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in one of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that the 1st through Nth physical pages are coupled to a word line of the same order.
For example, as illustrated in
As described above with reference to
And then, the control unit 2210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st through 4th non-volatile memory devices 2100-1, 2100-2, 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD5—1˜LPD5—4, LPD6—1˜LPD6—4, LPD7—1˜LPD7—4 and LPD8—1˜LPD8—4, which are included in 5th through 8th parity groups PARITY GROUP 5, PARITY GROUP 6, PARITY GROUP 7 and PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2. In this way, the control unit 2210 may determine a 64th physical page group PPG64 by selecting a physical page coupled to a 64th word line WL64 from the 1st through 4th non-volatile memory devices 2100-1, 2100-2, 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD253—1˜LPD253—4, LPD254—1˜LPD254—4, LPD255—1˜LPD255—4 and LPD256—1˜LPD256—4, which are included in 253rd through 256th parity groups PARITY GROUP 253, PARITY GROUP 254, PARITY GROUP 255 and PARITY GROUP 256 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 64th physical page group PPG64.
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data, which are received from the host, by a unit of a logical page and generate the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in two of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that the 1st through Nth physical pages are coupled to a word line of the same order.
For example, as illustrated in
As described above with reference to
And then, the control unit 2210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st through 4th non-volatile memory devices 2100-1, 2100-2, 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD5—1˜LPD5—4, LPD6—1˜LPD6—4, LPD7—1˜LPD7—4 and LPD8—1˜LPD8—4, which are included in 5th through 8th parity groups PARITY GROUP 5, PARITY GROUP 6, PARITY GROUP 7 and PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2. In this way, the control unit 2210 may determine a 64th physical page group PPG64 by selecting a physical page coupled to a 64th word line WL64 from the 1st through 4th non-volatile memory devices 2100-1, 2100-2, 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD253—1˜LPD253—4, LPD254—1˜LPD254—4, LPD255—1˜LPD255—4 and LPD256—1˜LPD256—4, which are included in 253rd through 256th parity groups PARITY GROUP 253, PARITY GROUP 254, PARITY GROUP 255 and PARITY GROUP 256 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 64th physical page group PPG64.
In the 2D flash memory cell array 2110, a physical page coupled to the 1st word line WL1 may have a relatively high bit error rate (BER) than physical pages coupled to other word lines. In other example embodiments, the control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that at least two of the 1st through Nth physical pages are coupled to word lines of different orders. In this case, bit error rate (BER) imbalance between physical pages coupled to different word lines may be reduced.
For example, the control unit 2210 may determine a plurality of the physical page groups by selecting one physical page in an order from a physical page coupled to the 1st word line WL1 to a physical page coupled to the last word line WL64 from at least one of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, and selecting a physical page coupled to the last word line WL64 at 1st and then selecting one physical page in an order from a physical page coupled to the 1st word line WL1 to a physical page coupled to the 2nd last word line WL63 from rest of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n.
It is illustrated in
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data, which are received from the host, by a unit of a logical page and generate the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through the (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in one of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that at least two of the 1st through Nth physical pages are coupled to word lines of different orders.
For example, as illustrated in
And then, the control unit 2210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st through the 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting a physical page coupled to a 1st word line WL1 from the 4th non-volatile memory devices 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD5—1˜LPD5—4, LPD6—1˜LPD6—4, LPD7—1˜LPD7—4 and LPD8—1˜LPD8—4, which are included in 5th through 8th parity groups PARITY GROUP 5, PARITY GROUP 6, PARITY GROUP 7 and PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2.
As described above with reference to
In similar manner, the control unit 2210 may determine 3rd through 63rd physical page groups PPG3 to PPG63 by selecting one physical page in an order from a physical page coupled to a 3rd word line WL3 to a physical page coupled to a 63rd word line WL63 from the 1st through 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting one physical page in an order from a physical page coupled to a 2nd word line WL2 to a physical page coupled to a 62nd word line WL62 from the 4th non-volatile memory device 2100-4, and store four (4) sets of the 1st through 4th logical page data LPDi_1˜LPDi_4 in the 1st through 4th physical pages, respectively, included in a corresponding physical page group.
Then, the control unit 2210 may determine a 64th physical page group PPG64 by selecting a physical page coupled to a 64th word line WL64 from the 1st through 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting a physical page coupled to the 63rd word line WL63 from the 4th non-volatile memory devices 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD253—1˜LPD253—4, LPD254—1˜LPD254—4, LPD255—1˜LPD255—4 and LPD256—1˜LPD256—4, which are included in 253rd through 256th parity groups PARITY GROUP 253, PARITY GROUP 254, PARITY GROUP 255 and PARITY GROUP 256 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4 in the 1st through 4th physical pages, respectively, included in a 64th physical page group PPG64.
Then, the control unit 2210 may store four (4) sets of the 4th logical page data LPD1—4, LPD2—4, LPD3—4 and LPD4—4 included in 1st through 4th parity groups PARITY GROUP 1, PARITY GROUP 2, PARITY GROUP 3 and PARITY GROUP 4, respectively, and stored in the temporary memory (not illustrated), in a physical page that is included in the 1st physical page group PPG1 and is coupled to the last word line WL64 of the 4th non-volatile memory devices 2100-4.
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data, which are received from the host, by a unit of a logical page and generate the 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n may constitute a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in two of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine the physical page group including the 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n, respectively, such that at least two (2) of the 1st through Nth physical pages are coupled to word lines having different orders.
For example, as illustrated in
Then, the control unit 2210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st and 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting a physical page coupled to a 1st word line WL1 from the 3rd and 4th non-volatile memory devices 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD5—1˜LPD5—4, LPD6—1˜LPD6—4, LPD7—1˜LPD7—4 and LPD8—1˜LPD8—4, which are included in 5th through 8th parity groups PARITY GROUP 5, PARITY GROUP 6, PARITY GROUP 7 and PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2.
As described above with reference to
In similar manner, the control unit 2210 may determine 3rd through 63rd physical page groups PPG3 to PPG63 by selecting one physical page in an order from a physical page coupled to a 3rd word line WL3 to a physical page coupled to a 63rd word line WL63 from the 1st and 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting one physical page in an order from a physical page coupled to a 2nd word line WL2 to a physical page coupled to a 62nd word line WL62 from the 3rd and 4th non-volatile memory device 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPDi_1˜LPDi_4 in the 1st through 4th physical pages, respectively, included in a corresponding physical page group.
Then, the control unit 2210 may determine a 64th physical page group PPG64 by selecting a physical page coupled to a 64th word line WL64 from the 1st and 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting a physical page coupled to a 63rd word line WL63 from the 3rd and 4th non-volatile memory devices 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD253—1˜LPD253—4, LPD254—1˜LPD254—4, LPD255—1˜LPD255—4 and LPD256—1˜LPD256—4, which are included in 253rd through 256th parity groups PARITY GROUP 253, PARITY GROUP 254, PARITY GROUP 255 and PARITY GROUP 256 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in a 64th physical page group PPG64.
Then, the control unit 2210 may store four (4) sets of the 3rd and 4th logical page data LPD1—3˜LPD1—4, LPD2—3˜LPD2—4, LPD3—3˜LPD3—4 and LPD4—3˜LPD4—4 included in 1st through 4th parity groups PARITY GROUP 1, PARITY GROUP 2, PARITY GROUP 3 and PARITY GROUP 4, respectively, and stored in the temporary memory (not illustrated), in physical pages that are included in the 1st physical page group PPG1 and are coupled to the last word line WL64 of the 3rd and 4th non-volatile memory devices 2100-3 and 2100-4.
As described above, the SSD 2000 determines the logical page group including the 1st through Nth logical pages, such that at least two (2) of the 1st through Nth logical pages included in the logical page group are of different levels, and stores the 1st through Nth logical page data LPDi_1˜LPDi_n included in the same parity group in the 1st through Nth logical pages included in the logical page group, respectively. Therefore, the data recovery rate imbalance between parity groups may be decreased, and the number of times the SSD 2000 may not be able to recover damaged data may also be decreased. In other words, the SSD 2000 may increase overall stability.
Furthermore, the SSD 2000 may store the 1st through Nth logical page data LPDi_1˜LPDi_n included in the same parity group in a dispersed manner across physical pages coupled to word lines of different orders, such that the data recovery rate imbalance between parity groups is decreased and overall data recovery rate of the SSD 2000 increased.
The 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n included in the SSD 2000 of
Referring to
The 3D flash memory cell array 2110a may be formed on a substrate in a 3D or vertical structure. The 3D flash memory cell array 2110a may include a plurality of physical pages coupled to a plurality of word lines WLs formed in order on the substrate such that heights of the plurality of word lines WLs are different.
The 3D flash memory cell array 2110a may include a plurality of memory blocks BLK1, BLK2, . . . , BLKz. Here, z is a positive integer. Each of the plurality of memory blocks BLK1, BLK2, . . . , BLKz may include a plurality of physical pages. Each of the plurality of physical pages may include a plurality of multi-level cells. Each of the plurality of multi-level cells may store M-bit data. Therefore, each of the plurality of physical pages included in the 3D flash memory cell array 2110a may include M logical pages, which are called as the 1st level through the Mth level logical pages. The 3D flash memory cell array 2110a may perform a program operation and a read operation on a unit basis of a physical page and perform an erase operation on a unit basis of a memory block.
The structure and operation of the 3D flash memory cell array 1110 has been described above with reference to
The data I/O circuit 2120 may be connected to the 3D flash memory cell array 2110a through a plurality of bit lines BLs. The data I/O circuit 2120 may receive data (DATA) from the RAID controller 2200 and output data (DATA) read from the 3D flash memory cell array 2110a to the RAID controller 2200.
The address decoder 2130 may be connected to the 3D flash memory cell array 2110a through the plurality of word lines WLs, a string selection line SSL, and a ground selection line GSL. The address decoder 2130 may receive an address ADDR from the RAID controller 2200 and select a word line.
The control logic 2140 may control the program operation, the read operation, and the erase operation of the flash memory device 2100a by controlling the data I/O circuit 2120 and the address decoder 2130 based on a control signal CMD received from the RAID controller 2200. For example, in the program operation, the control logic 2140 may control the address decoder 2130 to allow a program voltage to be provided to a selected word line, and control the data I/O circuit 2120 to allow data to be programmed in memory cells connected to the selected word line.
As described above with reference to
In some example embodiments, the control unit 2210 may select a 1st word line having a 1st height and a 2nd word line having a 2nd height different from the 1st height in the 3D memory cell array from among the plurality of word lines WLs, and select one of a physical page coupled to the 1st word line and a physical page coupled to the 2nd word line from each of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n to determine the physical page group. In this case, at least one of the 1st through Nth physical pages included in the physical page group may be coupled to the 1st word line and a remainder of the 1st through Nth physical pages included in the physical page group may be coupled to the 2nd word line.
It is illustrated in
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data received from the host on a logical page basis in order to generate 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate an Nth logical page data LPDi_n by performing the parity operation on the 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n constitute a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in one of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine a plurality of the physical page groups by selecting one physical page in an order from a physical page coupled to a lowest word line in the memory cell array to a physical page coupled to a highest word line in the memory cell array from at least one of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n and selecting one physical page in an order from a physical page coupled to the highest word line in the memory cell array to a physical page coupled to the lowest word line in the memory cell array from a remainder of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n.
In some example embodiments, as illustrated in
In this case, the control unit 2210 may determine a 1st physical page group PPG1 by selecting a physical page coupled to a 1st word line WL1 from the 1st, 2nd and 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting a physical page coupled to the 8th word line WL8 from the 4th non-volatile memory device 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD1—1˜LPD1—4, LPD2—1˜LPD2—4, LPD3—1˜LPD3—4 and LPD4—1˜LPD4—4, which are included in 1st through 4th parity groups PARITY GROUP 1, PARITY GROUP 2, PARITY GROUP 3 and PARITY GROUP 4 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1.
As described above with reference to
In similar manner, the control unit 2210 may determine 2nd through 7th physical page groups PPG2 to PPG7 by selecting one physical page in an order from a physical page coupled to a 2nd word line WL2 to a physical page coupled to a 7th word line WL7 from the 1st through the 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting one physical page in an order from a physical page coupled to a 7th word line WL7 to a physical page coupled to a 2nd word line WL2 from the 4th non-volatile memory device 2100-4, and store four (4) sets of the 1st through 4th logical page data LPDi_1˜LPDi_4 in the 1st through 4th physical pages, respectively, included in a corresponding physical page group.
Then, the control unit 2210 may determine an 8th physical page group PPG8 by selecting a physical page coupled to an 8th word line WL8 from the 1st, the 2nd and the 3rd non-volatile memory devices 2100-1, 2100-2 and 2100-3 and selecting a physical page coupled to a 1st word line WL1 from the 4th non-volatile memory device 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD29—1˜LPD29—4, LPD30—1˜LPD30—4, LPD31—1˜LPD31—4 and LPD32—1˜LPD32—4, which are included in the 29th through 32rd parity groups PARITY GROUP 29, PARITY GROUP 30, PARITY GROUP 31 and PARITY GROUP 32 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
Hereinafter, operation of the SSD 2000 will be described with reference to
The buffer memory 2220 may buffer data received from the host on a logical page basis in order to generate the 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The parity generation unit 2230 may generate the Nth logical page data LPDi_n by performing the parity operation on the 1st through (N−1)th logical page data LPDi_1˜LPDi_(n−1). The 1st through Nth logical page data LPDi_1˜LPDi_n constitutes a parity group. As illustrated in
The level mix unit 2270 may reverse the order of the M logical page data stored in two of the 1st through Nth physical page buffers 2240-1, 2240-2, . . . , 2240-n. That is, as illustrated in
The control unit 2210 may determine a plurality of the physical page groups by selecting one physical page in an order from a physical page coupled to a lowest word line to a physical page coupled to a highest word line from at least one of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n and selecting one physical page in an order from a physical page coupled to the highest word line to a physical page coupled to the lowest word line from a remainder of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n.
In some example embodiments, as illustrated in
In this case, the control unit 2210 may determine a 1st physical page group PPG1 by selecting a physical page coupled to a 1st word line WL1 from the 1st and 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting a physical page coupled to an 8th word line WL8 from the 3rd and the 4th non-volatile memory devices 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD1—1˜LPD1—4, LPD2—1˜LPD2—4, LPD3—1˜LPD3—4 and LPD4—1˜LPD4—4, which are included in 1st through 4th parity groups PARITY GROUP 1, PARITY GROUP 2, PARITY GROUP 3 and PARITY GROUP 4 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1.
As described above with reference to
In similar manner, the control unit 2210 may determine 2nd through 7th physical page groups PPG2 to PPG7 by selecting one physical page in an order from a physical page coupled to a 2nd word line WL2 to a physical page coupled to a 7th word line WL7 from the 1st and the 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting one physical page in an order from a physical page coupled to a 7th word line WL7 to a physical page coupled to a 2nd word line WL2 from the 3rd and the 4th non-volatile memory device 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPDi_1˜LPDi_4 in the 1st through 4th physical pages, respectively, included in a corresponding physical page group.
Then, the control unit 2210 may determine an 8th physical page group PPG8 by selecting a physical page coupled to an 8th word line WL8 from the 1st and the 2nd non-volatile memory devices 2100-1 and 2100-2 and selecting a physical page coupled to a 1st word line WL1 from the 3rd and the 4th non-volatile memory device 2100-3 and 2100-4, and store four (4) sets of the 1st through 4th logical page data LPD29—1˜LPD29—4, LPD30—1˜LPD30—4, LPD31—1˜LPD31—4 and LPD32—1˜LPD32—4, which are included in 29th through 32nd parity groups PARITY GROUP 29, PARITY GROUP 30, PARITY GROUP 31 and PARITY GROUP 32 and stored in the 1st through 4th physical page buffers 2240-1, 2240-2, 2240-3 and 2240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
As described above, when each of the 1st through Nth non-volatile memory devices 2100-1, 2100-2, . . . , 2100-n includes the 3D flash memory cell array 2110a having multi-level cells, the SSD 2000 may store the 1st through Nth logical page data LPDi_1˜LPDi_n included in the same parity group and dispersed across logical pages of different levels as well as being dispersed across physical pages coupled to word lines at different heights in a memory cell array. Therefore, the data recovery rate imbalance between parity groups decreases and overall data recovery rate of the SSD 2000 increases.
Referring to
The method of programming data in a SSD described above with reference to
Referring to
The storage device 3000 may be connected to a host, such as a laptop computer, a personal computer, a mobile device, a digital camera, etc., to be used as a storage device.
Each of the 1st through Nth non-volatile memory devices 3100-1, 3100-2, . . . , 3100-n includes a non-volatile memory device. The non-volatile memory device may include a three-dimensional (3D) flash memory cell array that is formed on a substrate in a 3D or vertical structure.
The RAID controller 3200 may include a control unit 3210, a buffer memory 3220, a parity generation unit 3230, 1st through Nth physical page buffers 3240-1, 3240-2, . . . , 3240-n, a host interface 3250, and a memory interface 3260.
Comparing the storage device 3000 of
In
Hereinafter, operation of the storage device 3000 will be described with reference to
The buffer memory 3220 may buffer data received from the host on a physical basis in order to generate the 1st through (N−1)th physical page data PPDi_1˜PPDi_(n−1). The parity generation unit 3230 may generate the Nth physical page data PPDi_n by performing the parity operation on the 1st through the (N−1)th physical page data PPDi_1˜PPDi_(n−1). The 1st through Nth physical page data PPDi_1˜PPDi_n may constitute a parity group. The 1st through Nth physical page buffers 3240-1, 3240-2, . . . , 3240-n may store the 1st through Nth physical page data PPDi_1˜PPDi_n, which are included in the parity group, respectively.
The control unit 3210 may determine a physical page group including 1st through Nth physical pages. The 1st through Nth physical pages may be selected from the 1st through Nth SSDs 3100-1, 3100-2, . . . , 3100-n, respectively, such that at least two (2) of the 1st through Nth physical pages have different bit error rates (BERs). For example, the control unit 3210 may determine a plurality of the physical page groups by selecting one physical page in an order from a physical page coupled to a lowest word line WL1 to a physical page coupled to a highest word line WL8 from the substrate from at least one of the 1st through Nth SSDs 3100-1, 3100-2, . . . , 3100-n and selecting one physical page in an order from a physical page coupled to the highest word line WL8 to a physical page coupled to the lowest word line WL1 from a remainder of the 1st through Nth SSDs 3100-1, 3100-2, . . . , 3100-n.
In some example embodiments, as illustrated in
In this case, the control unit 3210 may determine a 1st physical page group PPG1 by selecting a physical page coupled to a 1st word line WL1 from the 1st, 2nd and 3rd SSDs 3100-1, 3100-2 and 3100-3 and selecting a physical page coupled to an 8th word line WL8 from the 4th SSD 3100-4, and then store the 1st through 4th physical page data PPD1—1˜PPD1—4, which are included in a 1st parity group PARITY GROUP 1 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1.
Then, the control unit 3210 may determine a 2nd physical page group PPG2 by selecting a physical page coupled to a 2nd word line WL2 from the 1st, 2nd and 3rd SSDs 3100-1, 3100-2 and 3100-3 and selecting a physical page coupled to a 7th word line WL7 from the 4th SSD 3100-4, and then store the 1st through 4th physical page data PPD2—1˜PPD2—4, which are included in a 2nd parity group PARITY GROUP 2 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2.
In similar manner, the control unit 3210 may determine an 8th physical page group PPG8 by selecting a physical page coupled to the 8th word line WL8 from the 1st, the 2nd and the 3rd SSDs 3100-1, 3100-2 and 3100-3 and selecting a physical page coupled to the 1st word line WL1 from the 4th SSD 3100-4, and then store the 1st through 4th physical page data PPD8—1˜PPD8—4, which are included in an 8th parity group PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
In other example embodiments, as illustrated in
In this case, the control unit 3210 may determine the 1st physical page group PPG1 by selecting a physical page coupled to the 1st word line WL1 from the 1st and the 2nd SSDs 3100-1 and 3100-2 and selecting a physical page coupled to the 8th word line WL8 from the 3rd and the 4th SSDs 3100-3 and 3100-4, and then store the 1st through 4th physical page data PPD1—1˜PPD1—4, which are included in the 1st parity group PARITY GROUP 1 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 1st physical page group PPG1. After that, the control unit 3210 may determine the 2nd physical page group PPG2 by selecting a physical page coupled to the 2nd word line WL2 from the 1st and the 2nd SSDs 3100-1 and 3100-2 and selecting a physical page coupled to the 7th word line WL7 from the 3rd and the 4th SSDs 3100-3 and 3100-4, and then store the 1st through 4th physical page data PPD2—1˜PPD2—4, which are included in the 2nd parity group PARITY GROUP 2 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 2nd physical page group PPG2. In the similar way, the control unit 3210 may determine the 8th physical page group PPG8 by selecting a physical page coupled to the 8th word line WL8 from the 1st and the 2nd SSDs 3100-1 and 3100-2 and selecting a physical page coupled to the 1st word line WL1 from the 3rd and 4th SSDs 3100-3 and 3100-4, and then store the 1st through 4th physical page data PPD8—1˜PPD8—4, which are included in the 8th parity group PARITY GROUP 8 and stored in the 1st through 4th physical page buffers 3240-1, 3240-2, 3240-3 and 3240-4, respectively, in the 1st through 4th physical pages, respectively, included in the 8th physical page group PPG8.
As described above, the storage device 3000 determines the physical page group including the 1st through Nth physical pages, such that at least two of the 1st through Nth physical pages included in the physical page group are coupled to word lines of different heights in the memory cell array, and stores the 1st through Nth physical page data PPDi_1˜PPDi_n included in the same parity group in the 1st through Nth physical pages included in the physical page group, respectively. Therefore, the data recovery rate imbalance between parity groups may be decreased, and the number of times the storage device 3000 may not be able to recover damaged data may also be decreased.
The SSD 4200 includes 1st through Nth non-volatile memory devices NVM1, NVM2, . . . , NVMn 4210-1, 4210-2, . . . , 4210-n and a redundant array of independent disks (RAID) controller 4220.
Each of the 1st through Nth non-volatile memory devices 4210-1, 4210-2, . . . , 4210-n may be implemented by a flash memory device. The 1st through Nth non-volatile memory devices 4210-1, 4210-2, . . . , 4210-n may be used as a storage medium.
The RAID controller 4220 is respectively coupled to the 1st through Nth non-volatile memory devices 4210-1, 4210-2, . . . , 4210-n via 1st through Nth channels CH1, CH2, . . . , CHn.
The RAID controller 4220 may exchange a signal SGL with the host 4100 through a signal connector 4221. The signal SGL may include a command, an address and data. The RAID controller 4220 may perform a program operation and a read operation on the 1st through Nth non-volatile memory devices 4210-1, 4210-2, . . . , 4210-n according to the command received from the host 4100.
The SSD 4200 may further include an auxiliary power supply 4230. The auxiliary power supply 4230 may receive power PWR from the host 4100 through a power connector 4231 and provide power to the RAID controller 4220. The auxiliary power supply 4230 may be placed inside or outside the SSD 4200. For example, the auxiliary power supply 4230 may be placed in a main board and provide auxiliary power to the SSD 4200.
The SSD 4200 may be embodied with the SSD 1000 of
The processor 5100 programs data in the SSD 5200 and reads data from the SSD 5200. The processor 5100 may perform various computing functions, such as executing specific software for performing specific calculations or tasks. For example, the processor 5100 may be a microprocessor or a central process unit. The processor 5100 may be connected to the SSD 5200 via bus such as an address bus, a control bus or a data bus, etc. The processor 5100 may be connected to an extended bus, such as peripheral component interconnect (PCI) bus.
The processor 5100 may be embodied as a single core architecture or a multi core architecture. For example, the processor 5100 may be embodied as a single core architecture when an operating frequency of the processor 5100 is less than 1 GHz, and the processor 5100 may be embodied as a multi core architecture when an operating frequency of the processor 5100 is greater than 1 GHz. The processor 5100 that is embodied as a multi core architecture may communicate with the SSD 5200 via an advanced extensible interface (AXI) bus.
The SSD 5200 performs a program operation, a read operation, and an erase operation under control of the processor 5100. The SSD 5200 includes 1st through Nth non-volatile memory devices NVM1, . . . , NVMn 5210-1, . . . , 5210-n and a redundant array of independent disks (RAID) controller 5220. The RAID controller 5220 is coupled to the 1st through Nth non-volatile memory devices 5210-1, . . . , 5210-n by 1st through Nth channels CH1, CH2, . . . , CHn, respectively.
The SSD 5200 may be embodied with the SSD 1000 of
The electronic device 5000 may further include a memory device 5300, a display device 5400, a user interface 5500 and an input/output device 5600. Although not illustrated in
The memory device 5300 may store data for operations of the electronic device 5000. The memory device 5300 may include at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, etc. and/or at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, etc.
The display device 5400 may display data stored in the SSD 5200. For example, when the SSD 5200 stores multimedia data, the processor 5100 may read the multimedia data from the SSD 5200 and generate video data by decoding the multimedia data, and the display device 5400 may display the video data. The display device 5400 may include any type of devices such as an organic light emitting display (OLED) device, a liquid crystal display (LCD) device, etc.
The user interface 5500 may include devices required for a user to control the electronic device 5000. The input/output device 5600 may include at least one input device (e.g., a keyboard, keypad, a mouse, a touch screen, etc.) and/or at least one output device (e.g., a printer, a speaker, etc.).
The electronic device 5000 may comprise any of several types of electronic devices, such as a mobile device, a smart phone, a cellular phone, a personal digital assistant (PDA), a desktop computer, a laptop computer, a work station, a personal media player (PMP), a digital camera, or the like.
The foregoing example embodiments are illustrative of the inventive concept and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to fall within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
Number | Date | Country | Kind |
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10-2012-0036509 | Apr 2012 | KR | national |