STACK-BASED RAY TRAVERSAL WITH DYNAMIC MULTIPLE-NODE ITERATIONS

Abstract

A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

Description

Claims

1. A method for performing ray tracing operations, the method comprising: in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

2. The method of claim 1, further comprising: preserving determinism by enforcing depth first boundary volume hierarchy traversal.

3. The method of claim 1, wherein increasing the intersection test parallelization includes causing the non-terminated work-items to perform additional ray intersection tests per intersection test iteration.

4. The method of claim 3, wherein prior to the threshold number of work-items having terminated, work-items are performing one intersection test per intersection test iteration.

5. The method of claim 4, wherein intersection test iterations comprise iterations of a loop executed by the work-items.

6. The method of claim 1, wherein work-items terminate upon completing traversal of an acceleration structure for ray tracing.

7. The method of claim 1, wherein increasing the intersection test parallelization includes requesting an intersection test circuitry to perform multiple intersection tests at least partially concurrently.

8. The method of claim 7, wherein the intersection test circuitry is configured to execute multiple intersection tests in parallel.

9. The method of claim 7, wherein the intersection test circuitry is pipelined.

10. A system for performing ray tracing operations, the system comprising: a memory configured to store instructions; anda processor configured to execute a wavefront, the executing including: in response to detecting that a threshold number of traversal stage work-items of the wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

11. The system of claim 10, wherein the processor is further configured to: preserve determinism by enforcing depth first boundary volume hierarchy traversal.

12. The system of claim 10, wherein increasing the intersection test parallelization includes causing the non-terminated work-items to perform additional ray intersection tests per intersection test iteration.

13. The system of claim 12, wherein prior to the threshold number of work-items having terminated, work-items are performing one intersection test per intersection test iteration.

14. The system of claim 13, wherein intersection test iterations comprise iterations of a loop executed by the work-items.

15. The system of claim 10, wherein work-items terminate upon completing traversal of an acceleration structure for ray tracing.

16. The system of claim 10, wherein increasing the intersection test parallelization includes requesting an intersection test circuitry to perform multiple intersection tests at least partially concurrently.

17. The system of claim 16, wherein the intersection test circuitry is configured to execute multiple intersection tests in parallel.

18. The system of claim 16, wherein the intersection test circuitry is pipelined.

19. A non-transitory computer-readable medium storing instructions that when executed by a processor cause the processor to perform operations including: in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions further cause the processor to: preserve determinism by enforcing depth first boundary volume hierarchy traversal.