Claims
- 1. An array of electrically erasable programmable read only memory (EEPROM) cells comprising:a substrate; a plurality of parallel bitlines formed in the surface of said substrate; a first pocket region formed on a first edge of each of the bitlines; a second pocket region formed on a second edge of each of the bitlines; a plurality of polysilicon contacts formed on and above said bitlines, wherein contacts overlying a first bitline are staggered with respect to contacts overlying a second bitline that is adjacent to the first bitline; a bitline oxide layer disposed on each of said bitlines; and an oxide-nitride-oxide (ONO) layer disposed between each of said bitlines.
- 2. The array of claim 1, wherein said array comprises two-bit memory cells.
- 3. The array of claim 1, wherein said bitline oxide layer is formed by thermal oxidation.
- 4. The array of claim 1, wherein said bitlines are implanted with an n-type dopant.
- 5. The array of claim 4, wherein said bitlines are implanted with arsenic.
- 6. The array of claim 4, wherein said arsenic is implanted with a dose of about 3×1015 to about 5×1015 ions per square centimeter.
- 7. The array of claim 1, wherein said ONO layer has continuous, substantially vertical sidewalls.
- 8. The array of claim 1, wherein the bitlines have a junction depth that is greater than a junction depth of said first and second pocket regions.
- 9. The array of claim 1, wherein said ONO layer comprises an oxide layer with a thickness that is less than or equal to 60 angstroms.
- 10. The array of claim 1, wherein said ONO layer comprises a silicon nitride layer with a thickness between approximately 20 to 100 angstroms.
Parent Case Info
Applicants claim, under 35 U.S.C. §119(e), the benefit of priority of the filing date of May 16, 2000, of U.S. Provisional Patent Application Serial No. 60/204,467, filed on the aforementioned date, the entire contents of which are incorporated herein by reference.
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