Patent Application
20240107748
The following relates to one or more systems for memory, including a staggered horizontal cell architecture for memory devices.
Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.
Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or non-volatile. Non-volatile memory, e.g., NAND, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.
Memory devices may include one or more arrays of memory cells and supporting circuitry formed over a substrate for operating and accessing the memory cells. For example, a memory device may include one or more memory arrays that have multiple levels of memory cells, where a level may refer to a plane above and, in some cases, parallel to the substrate (e.g., in a horizontal direction). In some cases, a memory cell of a memory array may include an access line coupled with a selection component (e.g., a switching component, a cell selection component, one or more transistors) that is operable to couple a capacitor with a voltage source (e.g., a digit line) such that the logic state may be written or read. For example, a word line may extend through each layer of the substrate (e.g., in a vertical direction) to couple with a respective memory cell on each layer. Increasing the density of memory cells may support increased storage capacity of the memory array relative to its size, among other benefits. In some cases, however, as memory cell density increases, the space between word lines on a substrate layer (e.g., in a horizontal direction) may become relatively small, which may result in shorts (e.g., discharge) between adjacent word lines (e.g., vertical word lines in a 3-dimensional (3D) dynamic random access memory (DRAM) system), cross-talk between adjacent word lines, other adverse effects, or any combination thereof.
In accordance with the examples described herein, memory devices may implement a staggered architecture for one or more access lines (e.g., bit lines in a DRAM architecture such as a 3D DRAM architecture), which may result in increased spacing (e.g., increase horizontal spacing compared to other different architectures) between access lines (e.g., adjacent, neighboring) while maintaining a relatively high cell density. In some cases, a memory device with multiple layers (e.g., a device with vertical stacking of memory cells and access lines) may include one or more staircase structures, such that each step of the staircase structure may correspond to a layer of the device. For example, a first staircase structure may be formed on one edge of the device, and a second staircase structure may be formed on another edge (e.g., an opposite edge) of the device. Additionally, a pattern may be etched into the layers (e.g., a continuous pattern, a serpentine pattern) and may be filled with a dielectric material (e.g., an oxide material). In some examples, multiple access lines (e.g., bit lines) may be formed through the stack and extend through each layer.
The access lines may have a staggered orientation. For example, a first set of access lines may be formed from a first portion of the stack (e.g., located near a first edge of the stack), and a second set of access lines may be formed from a second portion of the stack (e.g., located near a second edge of the stack opposite of the first edge). By arranging the sets of access lines relative to (e.g., on) different portions of the stack (e.g., the access lines may alternate from originating at the first portion and the second portion), a distance between access lines (e.g., adjacent, neighboring) in a respective portion may be increased. Such a staggered configuration (e.g., staggered architecture) may result in a reduced likelihood of shorts, cross-talk between access lines, other adverse effects, or any combination thereof. In some examples, in line with the examples of the present disclosure, a staircase structure on the edge of a memory device may couple with multiple sets of access lines to form scalable repeat units (e.g., a ‘tree’). For example, a first set of access lines may extend in a first direction, and a second set of access lines may extend in a second direction opposite the first direction. In such examples, multiple trees may be interlaced (e.g., in the staggered configuration), which may allow the memory device to maintain relatively high cell density while avoiding or mitigating adverse effects of access lines in relatively close proximity.
Features of the disclosure are initially described in the context of systems and devices with reference to
The system 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device 110 may be a component of the system 100 that is operable to store data for one or more other components of the system 100.
Portions of the system 100 may be examples of the host device 105. The host device 105 may be an example of a processor (e.g., circuitry, processing circuitry, a processing component) within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device 105 may refer to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller 120. In some examples, the external memory controller 120 may be referred to as a host (e.g., host device 105).
A memory device 110 may be an independent device or a component that is operable to provide physical memory addresses/space that may be used or referenced by the system 100. In some examples, a memory device 110 may be configurable to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 may be operable to support one or more of: modulation schemes to modulate the signals, various pin configurations for communicating the signals, various form factors for physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other functions.
The memory device 110 may be operable to store data for the components of the host device 105. In some examples, the memory device 110 (e.g., operating as a secondary-type device to the host device 105, operating as a dependent-type device to the host device 105) may respond to and execute commands provided by the host device 105 through the external memory controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.
The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input/output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host device 105 may be coupled with one another using a bus 135.
The processor 125 may be operable to provide functionality (e.g., control functionality) for the system 100 or the host device 105. The processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or an SoC, among other examples. In some examples, the external memory controller 120 may be implemented by or be a part of the processor 125.
The BIOS component 130 may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage data flow between the processor 125 and the various components of the system 100 or the host device 105. The BIOS component 130 may include instructions (e.g., a program, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.
The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a capacity (e.g., a desired capacity, a specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). A memory array 170 may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store one or more bits of data. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.
A memory die 160 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. In some examples, a 2D memory die 160 may include a single memory array 170. In some examples, a 3D memory die 160 may include two or more memory arrays 170, which may be stacked on top of one another or positioned next to one another (e.g., relative to a substrate). In some examples, memory arrays 170 in a 3D memory die 160 may be referred to as or otherwise include different sets (e.g., decks, levels, layers, dies). A 3D memory die 160 may include any quantity of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different decks may share a common access line such that some decks may share one or more of a word line, a digit line, or a plate line.
The device memory controller 155 may include components (e.g., circuitry, logic) operable to control operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.
A local memory controller 165 (e.g., local to a memory die 160) may include components (e.g., circuitry, logic) operable to control operation of the memory die 160. In some examples, a local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, a memory device 110 may not include a device memory controller 155, and a local memory controller 165 or the external memory controller 120 may perform various functions described herein. As such, a local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controllers 165 or both may include receivers for receiving signals (e.g., from the external memory controller 120), transmitters for transmitting signals (e.g., to the external memory controller 120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other components operable for supporting described operations of the device memory controller 155 or local memory controller 165 or both.
The external memory controller 120 may be operable to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105, such as the processor 125, and the memory device 110). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the components of the host device 105 and the memory device 110. In some examples, the external memory controller 120, or other component of the system 100 or the host device 105, or its functions described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof implemented by the processor 125 or other component of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120, or its functions described herein, may be implemented by one or more components of a memory device 110 (e.g., a device memory controller 155, a local memory controller 165) or vice versa.
The components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device 110. Each channel 115 may include one or more signal paths (e.g., a transmission medium, a conductor) between terminals associated with the components of the system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host device 105 and a second terminal at the memory device 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to act as part of a channel.
Channels 115 (and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be communicated over the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).
In some cases, a memory device 100 may support a staggered architecture, including but not limited to a DRAM architecture, for one or more access lines, which may be examples of digit lines (e.g., bit lines), word lines, or both. For example, an increased density of memory cells 105 may result in a reduced physical distance between access lines, such as digit lines (e.g., bit lines). In some cases, the access lines being relatively closer together may result in shorts, cross-talk, or both. In accordance with techniques described herein, the access lines of the memory device 100 may be arranged in a staggered manner, which may increase the distance between adjacent access lines on a first portion of the device and adjacent access lines on a second portion (e.g., edge) of the device. By implementing such techniques, the memory device 100 may realize relatively high density of memory cells and access lines while mitigating cross-talk, word line to word line shorts, and the like, among other benefits.
In some examples, a memory cell 205 may store a charge representative of the programmable states in a capacitor. In some examples of the present disclosure, a DRAM architecture may be implemented. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell 205 may include a logic storage component, such as capacitor 230, and a switching component 235 (e.g., a cell selection component). The capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor 230 may be coupled with a voltage source 240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.
The memory die 200 may include access lines (e.g., word lines 210, digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell 205 and may be used to perform access operations on the memory cell 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding. Memory cells 205 may be positioned at intersections of the word lines 210 and the digit lines 215.
Operations such as reading and writing may be performed on the memory cells 205 by activating access lines such as a word line 210 or a digit line 215. By biasing a word line 210 and a digit line 215 (e.g., applying a voltage to the word line 210 or the digit line 215), a single memory cell 205 may be accessed at their intersection. The intersection of a word line 210 and a digit line 215 in a two-dimensional or in a three-dimensional configuration may be referred to as an address of a memory cell 205. Activating a word line 210 or a digit line 215 may include applying a voltage to the respective line.
Accessing the memory cells 205 may be controlled through a row decoder 220, or a column decoder 225, or any combination thereof. For example, a row decoder 220 may receive a row address from the local memory controller 260 and activate a word line 210 based on the received row address. A column decoder 225 may receive a column address from the local memory controller 260 and may activate a digit line 215 based on the received column address.
Selecting or deselecting the memory cell 205 may be accomplished by activating or deactivating the switching component 235 using a word line 210. The capacitor 230 may be coupled with the digit line 215 using the switching component 235. For example, the capacitor 230 may be isolated from digit line 215 when the switching component 235 is deactivated, and the capacitor 230 may be coupled with digit line 215 when the switching component 235 is activated.
A word line 210 may be a conductive line in electronic communication with a memory cell 205 that is used to perform access operations on the memory cell 205. In some architectures, the word line 210 may be coupled with a gate of a switching component 235 of a memory cell 205 and may be operable to control the switching component 235 of the memory cell. In some architectures, the word line 210 may be coupled with a node of the capacitor of the memory cell 205 and the memory cell 205 may not include a switching component.
A digit line 215 may be a conductive line that couples the memory cell 205 with a sense component 245. In some architectures, the memory cell 205 may be selectively coupled with the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 may be operable to couple or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 may be coupled with the digit line 215.
The sense component 245 may be operable to detect a state (e.g., a charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sense component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell 205. The sense component 245 may compare a signal detected from the memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sense component 245 (e.g., to an input/output 255), and may indicate the detected logic state to another component of a memory device (e.g., a memory device 110) that includes the memory die 200.
The local memory controller 260 may control the accessing of memory cells 205 through the various components (e.g., row decoder 220, column decoder 225, sense component 245). The local memory controller 260 may be an example of the local memory controller 165 described with reference to
The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from a host device 105). The local memory controller 260 may be operable to perform other access operations not listed here or other operations related to the operating of the memory die 200 that are not directly related to accessing the memory cells 205.
In some cases, the various components of the memory die 200 may be placed in accordance with a staggered architecture, including but not limited to a DRAM architecture, that supports increased density of memory cells 205. For example, access lines (e.g., digit lines 215, word lines 210) may be staggered on each layer of the memory die 200. As an illustrative example, a first set of access lines may be placed opposite and offset from a second set of access lines on each layer of the memory die 200 (e.g., each access line on a layer may alternate from originating at a first portion of the device to originating at a second portion of the device). By implementing such techniques, the memory die 200 may realize relatively high density while mitigating cross-talk, word line to word line shorts, and the like, among other benefits.
In some examples, the first set of manufacturing operations may include forming various structures and materials over (e.g., on, in contact with, above) a substrate 330. The substrate 330 may be a semiconductor wafer or other substrate over which a stack of layers is formed (e.g., deposited, etched). For example, the stack of layers (i.e., stack of materials) may include alternating layers of a dielectric material 320 (e.g., an oxide material or another example of a dielectric material, a dielectric layer) and a conductive material 315 (e.g., a poly silicon material, a conductive layer). As an illustrative example, the first set of manufacturing operations may include forming (e.g., depositing) a layer of the dielectric material 320 over the substrate 330, forming (e.g., depositing) a layer of the conductive material 315 over the layer of dielectric material 320, forming (e.g., depositing) a second layer of the dielectric material 320 over the layer of the conductive material 315, and so on. In some examples, other operations may be performed between any of the operations described herein, or some operations may be removed. As an example, material may be removed (e.g., etched) in between forming (e.g., depositing) each layer of the dielectric material 320 and the conductive material 315, operations to planarize the layers may be performed, and the like.
In some examples, a portion of the layers of the dielectric material 320 may be an example of a sacrificial material or layer. A sacrificial layer may be a layer of material that provides structure and spacing during the manufacturing process but may be removed (e.g., etched) at various points of the process. Stated alternatively, a sacrificial layer or material may be absent from the final product of the manufacturing operations described herein.
The first set of manufacturing operations may include forming a pattern of dielectric fill 325 (e.g., an oxide material) through the stack of layers. For example, the forming such a pattern may include removing (e.g., etching) portions of the stack of layers, such that voids are formed in the pattern. A dielectric fill 325 may be formed (e.g., deposited) into the void to form the pattern of the dielectric fill 325. In some examples, the pattern may be an example of a continuous pattern (e.g., a serpentine pattern) as described herein. For example, the pattern may be a portion of the dielectric fill 325 formed (e.g., deposited) in the stack of layers without any separation via other materials or voids between the section of formed (e.g., deposited) dielectric fill 325, the pattern may outline the access lines (e.g., nano wires) of polysilicon that are staggered relative to each other, and the like. Additionally or alternatively, the pattern may be examples of other pattern types associated with a staggered architecture, such as two half-serpentine patterns, a pattern having a horizontal line with staggered perpendicular lines to form a staggered array, and the like, among other examples of patterns. In some examples, the pattern may not be continuous.
In some examples, such a pattern may support the formation and architecture of staggered memory elements (e.g., memory cells, capacitors, access devices, access lines such as bit lines, capacitor plates, and the like) as described herein. For example, as shown in the top-down view 335, the portions of the stack of materials removed by the pattern may be formed into access lines (e.g., bit lines, although it is to be understood such access line formation techniques may additionally or alternatively be applied to word lines) of a set of levels. For instance, the layers of conductive material 315 may be poly-silicon material that will be formed into at least a portion of an access device (e.g., each layer of the conductive material 315 may be formed into an access line in a vertical layer of the memory device). In some examples, the layers of conductive material 315 may be referred to as wires (e.g., poly silicon nano wires), access lines (e.g., bit lines, word lines), or both.
Such operations and patterns may result in the layers of conductive material 315 that are coupled to a first portion of the memory device (e.g., originating from a first edge) being staggered relative to the layers coupled to an opposite, second portion of the memory device (e.g., originating from a second edge). As an illustrative example, the conductive material 315 shown in the second cross section view 310 may show three access lines (e.g., bit lines in a DRAM system such as a 3D DRAM system) coupled to the first portion and separated from three access lines coupled to the second portion by the dielectric fill 325. By having a continuous pattern or a similar pattern, a distance between capacitors to be formed on the access lines of a respective portion of the memory device may be increased due to the staggered arrangement, as described herein with respect to
The layout 400 may include one or more layers of conductive material 415, conductive material 420, conductive material 425, or any combination thereof, which may be examples of conductive material 315 as described with reference to
The second set of manufacturing operations may include forming one or more staircase structures 460. A staircase structure 460 may support vertical layers of memory cells. For example, a staircase structure 460 may have a set of levels, and each level may correspond to a respective set of memory cells (e.g., capacitors) at a vertical distance from the substrate associated with that level. In the illustrative example of the layout 400, two staircase structures may be formed at two portions (e.g., edges, areas) of the memory device. The staircase structure 460-a may have 3 levels and the staircase structure 460-b may have 3 levels, although any quantity of levels or staircase structures 460 may be used. Each level of the staircase structure 460-a may be shown with a different conductive material for illustrative clarity, though the various conductive materials described herein may be a same conductive material (e.g., the conductive material 315 as described with reference to
The second set of manufacturing operations may include forming one or more structural lines 440. The structural lines 440 may be a material to provide structure and support to one or more components of the memory device (e.g., the access lines), for example, if one or more portions of sacrificial material are removed (e.g., the dielectric fill 435 may be removed in the serpentine pattern at a stage of manufacturing). Stated alternatively, the structural lines 440 may hold up and structurally support the capacitors (formed on the conductive material lines) once oxide fill is etched away from around the capacitors as described herein with reference to
The second set of manufacturing operations may include forming one or more memory elements (e.g., capacitors 465). For example, a first capacitor 465-a may be formed on the top layer of the second cross section view 410 (e.g., the capacitor 465-a may include gate metal 445 over gate dielectric). Additionally or alternatively, vertical capacitors 465 may be formed on each level (e.g., three capacitors 465 formed below the first capacitor 465-a, though any quantity or placement of capacitors 465 may be used), capacitors 465 may be formed in the horizontal direction (e.g., the other three access lines extending into the dielectric fill 435 in the top down view 455 may each have a capacitor 465), or a combination thereof. In the illustrative example of layout 400, four capacitors 465 may be formed on a respective access line as shown in the top down view 455, and each capacitor may have a set of capacitors in a vertical direction below (e.g., as shown in the second cross section view 410), although any quantity or configuration of capacitors 465 may be used.
In some examples, forming a memory element may include opening a hole in the dielectric material 430 (e.g., oxide around the poly silicon layers), for example, using a photo and etch step to remove the dielectric material 430. Gate dielectric 450 may be formed (e.g., deposited) in a first portion of the holes to form a base of the capacitor (i.e., memory element). Gate metal 445 may be formed (e.g., deposited) over the gate dielectric 450 in a second portion (e.g., a remaining portion) of the holes to form the memory element, which may be referred to as an access device situated on a respective access line (e.g., a capacitor situated on a bit line in a DRAM system such as a 3D DRAM system). Stated alternatively, the second set of manufacturing operations may include selectively removing oxide from around wires (e.g., lines of conductive material such as poly-silicon in each level of the staircase structures 460) and then filling the empty space the with the gate materials. In some examples, such operations may form the vertical word line device with gate dielectric and gate metal, which may be an example of a double gate or a gate all around (GAA).
Although described as being formed with various components and by various manufacturing operations, it is to be understood that any of the layouts described herein may include additional or alternative components formed by additional or alternative manufacturing operations, such as interconnection or routing circuitry, control circuitry, or other structures and materials, which may include various conductor, semiconductor, or dielectric materials between the structures and materials and the substrate. Further, although described as conductive materials 415, 420, 425, such materials may be examples of other terminology (e.g., semi-conductive materials).
In some examples, by staggering the capacitors 465 relative to each other as shown in the layout 400, a horizontal distance (e.g., a distance in the y direction of the top-down view 455) between capacitors 465 on a same portion (e.g., edge, area) of the memory device may be increased, which may result in reduced likelihood for access line shorts or crosstalk between the devices as described with reference to
The first layout 505 may illustrate an arrangement of access lines with capacitors (e.g., illustrated by the positions of gate metal 545) that does not use a staggered architecture. For example, the first layout 505 may illustrate an example of three access lines having three respective capacitors on a level of a memory device. The capacitors may be on a same portion of the memory device, and adjacent access lines and capacitors may have a relatively short horizontal distance to each other compared to the second layout 510. In some examples, such a configuration may result in shorting between access lines, cross-talk between access lines, or both.
Accordingly, the second layout 510 may illustrate a portion of a device formed using the techniques for a staggered architecture as described herein. For example, the second layout 510 may include a serpentine pattern of the dielectric fill 535 as described herein, resulting in access lines formed within the pattern having a staggered configuration. In such a staggered configuration, adjacent access lines and respective capacitors on a same portion of the memory device may be separated by a relatively larger spacing 550. For example, the second layout 510 may show four access lines, two located on the first portion of the memory device (e.g., a first edge of the memory device) and two located on the second portion (not shown), such as a second edge (e.g., side) of the memory device. For instance, a capacitor on the access line between the two shown capacitors may originate or otherwise be located on another portion of the device. Thus, the two shown capacitors may have a spacing 550 that is larger than the spacing between adjacent capacitors shown in the first layout 505, which may reduce the likelihood of cross-talk and shorting while maintaining a relatively high memory cell density in the memory device, among other benefits. Stated alternatively, the architecture of the second layout 510 may reduce a risk of word line to word line shorts by increasing the distance between adjacent fins and access devices on a same bit line.
The layout 600 may include one or more layers of conductive material 615, conductive material 620, conductive material 625, or any combination thereof, which may be examples of conductive materials 415, 420, and 425 as described with reference to
In some examples, the third set of manufacturing operations may be performed on the layout 400. For example, the third set of manufacturing operations may include removing (e.g., etching) portions of the dielectric fill 635. Stated alternatively, oxide may be removed from capacitor studs in the area 675 of the memory device (e.g., the substrate may be exposed in the top-down view 660 based on removing the dielectric fill 635). In some examples, the various layers of conductive material may be metallized. For example, a metallization operation may be performed on the exposed access lines (e.g., layers of conductive material 615, 620, and 625). Such an operation may aid in creation of a metal-insulator-metal (MIM) capacitor at each layer of the memory device. In some other examples, the layers of conductive material may not be metallized. In some cases, the exposed conductive layers may serve as capacitor studs, which may be supported by the one or more structural lines 640 (e.g., nitride lines after removing dielectric fill 635).
The third set of manufacturing operations may include forming (e.g., depositing) a capacitor top plate 655 on each of the access lines, as shown for example in the second cross section view 610. That is, the capacitor top plate 655 may be formed (e.g., deposited) over the access lines that were exposed (e.g., metallized cap studs) after forming (e.g., depositing) a capacitor dielectric. Stated alternatively, the capacitor top plate 655 may be formed (e.g., deposited) over a layer of capacitor dielectric located between lines of conductive material and the capacitor top plate 655. In some examples, the capacitor top plate 655 may be an example of a metal material, a poly silicon material, or any other conductive material. In some examples, forming (e.g., depositing, etching, etc.) the capacitor top plate 655 may finish the formation of capacitors with dielectric material. For example, the capacitor 680-a may be an example of a finished capacitor 680 having a capacitor top plate 655, a capacitor bottom plate (e.g., the conductive material 625), a gate metal portion 645, gate dielectric 650, and the like.
The third set of manufacturing operations may include forming contacts 670 from contact material 665. For example, contacts 670 may be formed to connect various components (e.g., gates, access lines) of the memory device to other circuitry, such as interconnect circuitry, control circuitry, and the like. In some examples, forming the contacts may include removing dielectric material (e.g., dielectric fill 635) to form a hole, and forming (e.g., depositing) the contact material 665 in the holes. In some examples, the contacts 670 may be located on one or more sides (e.g., portions) of the device. As an illustrative example, the contact 670-b may connect the memory device to a top side of the second cross section view 610. Additionally or alternatively, the contact 670-b may be located at a bottom side of the memory device (e.g., the contact 670-b may extend through the substrate to connect the components). In some examples, forming the contacts 670 may include a photo etch through a film such as a dielectric material above the array (not shown) and filling the resulting hole with contact material 665.
In some examples, a capacitor dielectric and capacitor top plate 655 may be formed (e.g., deposited) around the capacitor studs (e.g., the portions of the access lines in the area 675), for example, to form MIM capacitors. For example, the capacitor dielectric may be formed (e.g., deposited) to surround the capacitor studs at each layer, and may support a relatively high capacitance (e.g., have a large dielectric constant, K). The capacitor top plate 655 may then be formed (e.g., deposited) into the remaining space where the dielectric was removed.
In the example of the repeatable structure 700, the staircase structure 705 may be formed and coupled to the fins 710-a and 710-b. The fins 710 may have a set of vertical levels (e.g., three levels or any quantity of levels). For example, while the fin 710-a is shown with three capacitors (i.e., access devices, memory cells), the fin 710-a also include three levels and thus 9 total capacitors. For instance, the first set of three capacitors may be associated with a first level of the staircase structure 705, a second set of three capacitors below the first three capacitors may be associated with a second level (e.g., the conductive material 720), a third set of three capacitors may be below the second set of three capacitors and may be associated with a third level (e.g., the conductive material 715), and so on, although any quantity of levels, capacitors, and arrangements may be used.
The fin 710-a may extend in a first direction and the fin 710-b may extend in a second direction opposite the first direction. To obtain a staggered orientation as described herein, the repeatable structure 700 may be repeated in a staggered manner. For example, a fin of another repeatable structure may have a fin with access lines extending in the second direction such that a space between the access lines of the other fin and the access lines of the fin 710-a is a continuous (e.g., serpentine) pattern as described herein. Thus, the fins 710 of adjacent repeatable structures 700 may be offset by a horizontal distance such that the access devices (e.g., capacitors) of the fin 710-a are on a first portion of the memory device (e.g., a first area) and staggered relative to access lines of another fin 710 of another structure on a second portion of the memory device (e.g., a second area). Stated alternatively, interlacing multiple trees may support efficient packing of repeatable structures 700 (e.g., repeatable units) while mitigating the likelihood of shorts and crosstalk between adjacent access lines. Such a staggered configuration may be repeatable for any quantity of repeatable structures 700. For example, a manufacturing process may be scaled by fabricating back-to-back fins 710 on a single staircase structure 705.
Additionally or alternatively, the interlacing trees may support inverted staircase structures 705. For example, a first tree may have the staircase structure on a first portion (e.g., on the bottom of the view of
In some examples, end caps (e.g., cap structures) may be formed to finalize an array. For example, after forming a quantity of trees in a staggered configuration, a first end cap may be placed at the end of the array and a second end cap may be places at the other end of the array, which may complete the array. The end cap may be an example of the tree shown in
Although shown with certain quantities and arrangements of components, it is to be understood that any quantity or type of component may be used. For example, any quantity of levels, repeatable structures 700, access devices, and the like may be used. Additionally or alternatively, repeatable structures 700 (e.g., repeatable units) may be arranged above and below each other in any direction (e.g., the repeatable structure 700 may have an adjacent tree in any horizontal direction, such as below, above, left, and right). In some examples, a CMOS may be placed under the array. In some examples, the staircase structure 705 may be an example of the structure 800 as described herein with reference to
The staircase 805-a may be an example of a staircase with a single row of contacts 830. The staircase 805-b may be an example of a staircase with a staggered row orientation of contacts 830. The top view 810 and the side view 815 may be illustrative examples of the staircase 805-b.
As illustrated in the structure 800, the staircase 805-b may support a same quantity of contacts as the staircase 805-a while also providing a larger landing area for forming the contacts 830, resulting in a relatively more reliable fabrication process of the memory device. Stated alternatively, the staircase structure 805-b may lengthen the staircase to increase the contact landing area, and the staircase fin may be made wider. Such techniques may promote structural stability and may prevent or mitigate shorts between adjacent contacts 830. Additionally or alternatively, the staircase structure 805-b may be offset, which may further increase the landing pad area. For example, the side view 815 shows how the two rows have levels offset relative to their respective column. In some examples, the staircase structures 805 may be implemented in the staircase structures described herein.
At 905, the method may include forming (e.g., depositing) a stack of layers over a substrate, the stack of layers including alternating layers of a first dielectric material and a conductive material. The operations of 905 may be performed in accordance with examples as disclosed herein.
At 910, the method may include forming a second dielectric material in a continuous pattern through the stack of layers. The operations of 910 may be performed in accordance with examples as disclosed herein.
At 915, the method may include forming (e.g., etching) a first staircase structure at a first portion of the stack of layers and a second staircase structure at a second portion of the stack of layers, the first and second staircase structures each including a plurality of levels. The operations of 915 may be performed in accordance with examples as disclosed herein.
At 920, the method may include forming a plurality of gates through the stack of layers, a first portion of the plurality of gates arranged on a third portion of the stack of layers and a second portion of the plurality of gates arranged on a fourth portion of the stack of layers. The operations of 920 may be performed in accordance with examples as disclosed herein.
In some examples, an apparatus as described herein may perform a method or methods, such as the method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:
It should be noted that the described methods include possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.
An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:
An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:
Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.
The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.
The term “coupling” refers to a condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.
The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other if the switch is open. If a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.
The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials, or combinations thereof. In some examples, one layer or level may be composed of two or more sublayers or sublevels.
The terms “if” “when,” “based on,” or “based at least in part on” may be used interchangeably. In some examples, if the terms “if” “when,” “based on,” or “based at least in part on” are used to describe a conditional action, a conditional process, or connection between portions of a process, the terms may be interchangeable.
Additionally, the terms “directly in response to” or “in direct response to” may refer to one condition or action occurring as a direct result of a previous condition or action. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring independent of whether other conditions or actions occur. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited quantity of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed “based on,” “based at least in part on,” or “in response to” some other step, action, event, or condition may additionally, or alternatively (e.g., in an alternative example), be performed “in direct response to” or “directly in response to” such other condition or action unless otherwise specified.
The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping process or components.
A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” if a voltage less than the transistor's threshold voltage is applied to the transistor gate.
The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.
In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a hyphen and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”
Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.
The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.
