Staircase forward error correction coding

Abstract

In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code. Thus, each row in [Bi−1T Bi] and each column in

Description

FIELD OF THE INVENTION

This invention relates generally to encoding and decoding and, in particular, to staircase Forward Error Correction (FEC) coding.

BACKGROUND

FEC coding provides for correction of errors in communication signals. Higher coding gains provide for correction of more errors, and can thereby provide for more reliable communications and/or allow signals to be transmitted at lower power levels.

The Optical Transport Hierarchy (OTH), for example, is a transport technology for the Optical Transport Network (OTN) developed by the International Telecommunication Union (ITU). The main implementation of OTH is described in two recommendations by the Telecommunication Standardization section of the ITU (ITU-T), including:

Recommendation G.709/Y.1331, entitled “Interfaces for the Optical Transport Network (OTN)”, December 2009, with an Erratum 1 (May 2010), an Amendment 1 (July 2010), and a Corrigendum 1 (July 2010); and

Recommendation G.872, entitled “Architecture of optical transport networks”, November 2001, with an Amendment 1 (December 2003), a Correction 1 (January 2005), and an Amendment 2 (July 2010).

G.709 defines a number of layers in an OTN signal hierarchy. Client signals are encapsulated into Optical channel Payload Unit (OPUk) signals at one of k levels of the OTN signal hierarchy. An Optical channel Data Unit (ODUk) carries the OPUk and supports additional functions such as monitoring and protection switching. An Optical channel Transport Unit (OTUk) adds FEC coding. Optical Channel (OCh) signals in G.709 are in the optical domain, and result from converting OTUk signals from electrical form to optical form.

FEC coding as set out in G.709 provides for 6.2 dB coding gain. ITU-T Recommendation G.975.1, entitled “Forward error correction for high bit-rate DWDM submarine systems”, February 2004, proposes an enhanced FEC coding scheme with improved coding gain.

Further improvements in coding gain, without impractical additional processing resources, remain a challenge.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments of the invention will now be described in greater detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a sequence of two-dimensional symbol blocks.

FIG. 2 is a block diagram illustrating an example codeword.

FIG. 3 is a block diagram illustrating an example sub-division of a symbol block.

FIG. 4 is a block diagram representation of an example staircase code.

FIG. 5 is a block diagram representation of an example generalized staircase code.

FIG. 6 is a flow diagram illustrating an example encoding method.

FIG. 7 is a flow diagram illustrating an example decoding method.

FIG. 8 is a block diagram illustrating an example apparatus.

FIG. 9 is a block diagram illustrating another example apparatus.

FIG. 10 is a block diagram illustrating an example frame structure.

DETAILED DESCRIPTION

A staircase code is a blockwise recursively encoded forward error correction scheme. It can be considered a generalization of the product code construction to a family of variable latency codes, wherein the granularity of the latency is directly related to the size of the “steps”, which are themselves connected in a product-like fashion to create the staircase construction.

In staircase encoding as disclosed herein, symbol blocks include data symbols and coding symbols. Data symbols in a stream of data symbols are mapped to a series of two-dimensional symbol blocks. The coding symbols could be computed across multiple symbol blocks in such a manner that concatenating a row of the matrix transpose of a preceding encoded symbol block with a corresponding row of a symbol block that is currently being encoded forms a valid codeword of a FEC component code. For example, when encoding a second symbol block in the series of symbol blocks, the coding symbols in the first row of the second symbol block are chosen so that the first row of the matrix transpose of the first symbol block, the data symbols of the first row of the second symbol block, and the coding symbols of the same row of the second block together form a valid codeword of the FEC component code.

Coding symbols could equivalently be computed by concatenating a column of the previous encoded symbol block with a corresponding column of the matrix transpose of the symbol block that is currently being encoded.

With this type of relationship between symbol blocks, in a staircase structure that includes alternating encoded symbol blocks and matrix transposes of encoded symbol blocks, each two-block wide row along a stair “tread” and each two-block high column along a stair “riser” forms a valid codeword of the FEC component code.

In some embodiments, a large frame of data can be processed in a staircase structure, and channel gain approaching the Shannon limit for a channel can be achieved. Low-latency, high-gain coding is possible. For 1.25 Mb to 2 Mb latency, for example, some embodiments might achieve a coding gain of 9.4 dB for a coding rate of 239/255, while maintaining a burst error correction capability and error floor which are consistent with other coding techniques that exhibit lower coding gains and/or higher latency.

FIG. 1 is a block diagram illustrating a sequence of two-dimensional symbol blocks. In the sequence 100, each B_i(for i≥0) 102, 104, 106, 108, 110 is an m by m array of symbols. Each symbol in each block 102, 104, 106, 108, 110 may be one or more bits in length. Staircase codes are characterized by the relationship between the symbols in successive blocks 102, 104, 106, 108, 110.

During FEC encoding according to a staircase code, a FEC code in systematic form is first selected to serve as the component code. This code, hereinafter C, is selected to have a codeword length of 2m symbols, r of which are parity symbols. As illustrated in FIG. 2, which is a block diagram illustrating an example length 2m codeword 200, the leftmost 2m-r symbols 202 constitute information or data symbol positions of C, and the rightmost r symbols 204 are parity symbol positions, or more generally coding symbol positions, of C.

In light of this notation, for illustrative purposes consider the example sub-division of a symbol block as shown in FIG. 3. The example symbol block 300 is sub-divided into m-r leftmost columns 302 and r rightmost columns 304, where B_i,L is the sub-matrix including the leftmost columns, and similarly B_i,R is the sub-matrix including the rightmost columns of the symbol block B_i.

The entries of the symbol block B₀ are set to predetermined symbol values. For i≥1, data symbols, specifically m(m−r) such symbols, which could include information that is received from a streaming source for instance, are arranged or distributed into B_i,L by mapping the symbols into B_i,L. Then, the entries of B_i,R are computed. Thus, data symbols from a symbol stream are mapped to data symbol positions B_i,L in a sequence of two-dimensional symbol blocks B and coding symbols for the coding symbol positions B_i,R in each symbol block are computed.

In computing the coding symbols according to one example embodiment, an m by (2m−r) matrix, A=[B_i−1^T B_i,L], where B_i−1^T is the matrix-transpose of B_i−1, is formed. The entries of B_i,R are then computed such that each of the rows of the matrix [B_i−1^T B_i,R] is a valid codeword of C. That is, the elements in the jth row of B_i,R are exactly the r coding symbols that result from encoding the 2m−r symbols in the jth row of A.

Generally, the relationship between successive blocks in a staircase code satisfies the following relation: For any i≥1, each of the rows of the matrix [B_i−1^T B_i] is a valid codeword of C.

An equivalent description of staircase codes, from which their name originates, is suggested in FIG. 4, which is a block diagram representation of an example staircase code. Every row and every column that spans two symbol blocks 402, 404, 406, 408, 410, 412 in the “staircase” 400 is a valid codeword of C. It should be apparent that each two-block row in FIG. 4 is a row of the matrix [B_i−1^T B_i,L B_i,R], as described above for the computation of coding symbols. The columns are also consistent with this type of computation.

Consider the first two-block column that spans the first column of B₁ 404 and the first column of B₂^T 406. In the example computation described above, the coding symbols for the first row of B₂ would be computed such that [B₁^T B_2,L B_2,R] is a valid codeword of C. Since the first column of B₁ 404 would be the first row in B₁^T, and similarly the first column of B₂^T406 would be the first row of B₂, the staircase structure 400 is consistent with the foregoing example coding symbol computation.

Therefore, it can be seen that coding symbols for a block B_i could be computed row-by-row using corresponding rows of B_i−1^T and B_i, as described above. A column-by-column computation using corresponding columns of B_i−1 and B_i^T would be equivalent. Stated another way, coding symbols could be computed for the coding symbol positions in each symbol B_i, where i is a positive integer, in a sequence such that symbols at symbol positions along one dimension (row or column) of the two-dimensional symbol block B_i−1 in the sequence, concatenated with the information symbols and the coding symbols along the other dimension (column or row) in the symbol B_i, form a codeword of a FEC component code. In a staircase code, symbols at symbol positions along the one dimension (row or column) of the symbol block B_i in the sequence, concatenated with the information symbols and the coding symbols along the other dimension (column or row) in the symbol block B_i+1, also form a codeword of the FEC component code.

The two dimensions of the symbol blocks in this example are rows and columns. Thus, in one embodiment, the concatenation of symbols at symbol positions along a corresponding column and row of the symbol blocks B_i−1 and B_i, respectively, forms a codeword of the FEC component code, and the concatenation of symbols at symbol positions along a corresponding column and row of the symbol blocks B_i and B_i+1, respectively, also forms a codeword of the FEC component code. The “roles” of columns and rows could instead be interchanged. The coding symbols could be computed such that the concatenation of symbols at symbol positions along a corresponding row and column of the symbol blocks B_i−1 and B_i, respectively, forms a codeword of the FEC component code, and the concatenation of symbols at symbol positions along a corresponding row and column of the symbol blocks B_i and B_i+1, respectively also forms a codeword of the FEC component code.

In the examples above, a staircase code is used to encode a sequence of m by m symbol blocks. The definition of staircase codes can be extended to allow each block B_i to be an n by m array of symbols, for n≥m. As shown in FIG. 5, which is a block diagram representation of an example generalized staircase code, (n-m) rows of n predetermined symbols, illustratively zeros, are appended to each block B_i. This is shown in the staircase 500 at 504 for block B₀^T 506 and at 510 for block B₁ 512. The resultant matrices 502, 508, referenced below as D_i, are used in computing coding symbols. In this example, each of the rows of the matrix [D_i−1^T B_i] is a valid codeword of C. The first (n−m) row codewords are shortened codewords as a result of supplementing the block B₀^T with the (n−m) rows of predetermined symbols. With reference to D₀^T 502 and B₁ 512, the concatenation of the first (n−m) rows of D₀^T and the first (n−m) rows in B₁ forms (n−m) shortened codewords. Similar comments apply in respect of column codewords that result from concatenating the first (n−m) columns of D₁ 508 and B₂^T.

The (n−m) supplemental rows or columns which are added to form the D_i matrices in this example are added solely for the purposes of computing coding symbols. The added rows or columns need not be transmitted to a decoder with the data and coding symbols, since the same predetermined added symbols can also be added at the receiver during decoding.

FIG. 6 is a flow diagram illustrating an example encoding method 600 that provides staircase encoding. The example method 600 involves an operation 602 of mapping a stream of data symbols to data symbol positions in a sequence of two-dimensional symbol blocks B_i, i a positive integer. Each of the symbol blocks includes data symbol positions and coding symbol positions. As shown at 604, the example method 600 also involves computing coding symbols. Coding symbols are computed for the coding symbol positions in each symbol block B_i (i a positive integer) in the sequence such that, for each symbol B_i that has a preceding symbol block B_i−1 and a subsequent symbol block B_i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B_i−1, concatenated with the information symbols and the coding symbols along the other dimension in the symbol B_i, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol B_i, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B_i+1, form the same or a different codeword of the FEC component code.

The example method 600 is intended solely for illustrative purposes. Variations of the example method 600 are contemplated.

For example, all data symbols in a stream need not be mapped to symbol blocks at 602 before coding symbols are computed at 604. Coding symbols for a symbol block could be computed when the data symbol positions in that symbol block have been mapped to data symbols from the stream, or even as each row or column in a symbol block, depending on the computation being used, is mapped. Thus, the mapping at 602 and the computing at 604 need not strictly be serial processes in that the mapping need not be completed for an entire stream of data symbols before computing of coding symbols begins.

The mapping at 602 and/or the computing at 604 could involve operations that have not been explicitly shown in FIG. 6. One or more columns or rows could be added to symbol blocks or their matrix transposes for computation of coding symbols, where symbol blocks are non-square as described above.

FIG. 7 is a flow diagram illustrating an example decoding method. The example decoding method 700 involves receiving, at 702, a sequence of FEC encoded two-dimensional symbol blocks B_i. Each of the received symbol blocks includes received versions of data symbols at data symbol positions and coding symbols at coding symbol positions. The coding symbols for the coding symbol positions in each symbol block B_i, i a positive integer, in the sequence would have been computed at a transmitter of the received symbol blocks, as described herein, such that, for each symbol block B_i, that has a preceding symbol block B_i−1, and a subsequent symbol block B_i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B_i−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block B_i, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block B_i, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B_i+1, form a codeword of the FEC component code. At 704, the received FEC encoded symbol blocks are decoded. The decoding at 704 might involve syndrome-based iterative decoding, for example. During decoding, error locations in received data symbols are identified and corrected, provided the number of errors is within the error correcting capability of the FEC code, and iterative decoding proceeds on the basis of the corrected data symbols.

Embodiments have been described above primarily in the context of code structures and methods. FIG. 8 is a block diagram illustrating an example apparatus. The example apparatus 800 includes an interface 802, a FEC encoder 804, a transmitter 806, a receiver 808, a FEC decoder 810, and an interface 812. A device or system in which or in conjunction with which the example apparatus 800 is implemented might include additional, fewer, or different components, operatively coupled together in a similar or different order, than explicitly shown in FIG. 8. For example, an apparatus need not support both FEC encoding and FEC decoding. Also, FEC encoded symbol blocks need not necessarily be transmitted or received over a communication medium by the same physical device or component that performs FEC encoding and/or decoding. Other variations are possible.

The interfaces 802, 812, the transmitter 806, and the receiver 808 represent components that enable the example apparatus 800 to transfer data symbols and FEC encoded data symbol blocks. The structure and operation of each of these components is dependent upon physical media and signalling mechanisms or protocols over which such transfers take place. In general, each component includes at least some sort of physical connection to a transfer medium, possibly in combination with other hardware and/or software-based elements, which will vary for different transfer media or mechanisms.

The interfaces 802, 812 enable the apparatus 800 to receive and send, respectively, streams of data symbols. These interfaces could be internal interfaces in a communication device or equipment, for example, that couple the FEC encoder 804 and the FEC decoder 810 to components that generate and process data symbols. Although labelled differently in FIG. 8 than the interfaces 802, 812, the transmitter 806 and the receiver 808 are illustrative examples of interfaces that enable transfer of FEC encoded symbol blocks. The transmitter 806 and the receiver 808 could support optical termination and conversion of signals between electrical and optical domains, to provide for transfer of FEC encoded symbol blocks over an optical communication medium, for instance.

The FEC encoder and the FEC decoder could be implemented in any of various ways, using hardware, firmware, one or more processors executing software stored in computer-readable storage, or some combination thereof. Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), and microprocessors for executing software stored on a non-transitory computer-readable medium such as a magnetic or optical disk or a solid state memory device, are examples of devices that might be suitable for implementing the FEC encoder 804 and/or the FEC decoder 810.

In operation, the example apparatus 800 provides for FEC encoding and decoding. As noted above, however, encoding and decoding could be implemented separately instead of in a single apparatus as shown in FIG. 8.

The FEC encoder 804 maps data symbols, from a stream of data symbols received by the interface 802 from a streaming source for instance, to data symbol positions in a sequence of two-dimensional symbol blocks B_i. As described above, each symbol block includes data symbol positions and coding symbol positions. The FEC encoder computes coding symbols for the coding symbol positions in each symbol block B_i, in the sequence such that, for each symbol block B that has a preceding symbol block B_i−1 and a subsequent symbol block B_i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B_i−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol B_i, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block B concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B_i+1, form a codeword of the FEC component code. FEC encoded data symbols could then be transmitted over a communication medium by the transmitter 806.

FEC decoding is performed by the FEC decoder 810, on a sequence of FEC encoded two-dimensional symbol blocks B_i. These signal blocks are received through an interface, which in the example apparatus 800 would be the receiver 808. Each of the received symbol blocks includes received versions of data symbols at data symbol positions and coding symbols at coding symbol positions. The coding symbols for the coding symbol positions in each symbol block B_i in the sequence would have been computed at a transmitter of the received symbol blocks. The transmitter might be a transmitter 806 at a remote communication device or equipment. The coding symbol computation at the transmitter is such that, for each symbol block B_i that has a preceding symbol block B_i−1 and a subsequent symbol block B_i+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block B_i−1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol B_i, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol B_i, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B_i+1, form a codeword of the FEC component code. The FEC decoder 810 decodes the received FEC encoded symbol blocks.

Operation of the FEC encoder 804 and/or the FEC decoder 810 could be adjusted depending on expected or actual operating conditions. For example, where a particular application does not require maximum coding gain, a higher latency coding could be used to improve other coding parameters, such as burst error correction capability and/or error floor. In some embodiments, high coding gain and low latency are of primary importance, whereas in other embodiments different coding parameters could take precedence.

Other functions might also be supported at encoding and/or decoding apparatus. FIG. 9 is a block diagram illustrating an example optical communication system 900 that includes FEC encoding and FEC decoding. The example optical communication system 900 includes an OTUk frame generator 902, a mapper 904, and a FEC encoder 906 at an encoding/transmit side of an optical channel, and an OTUk framer 908, a FEC de-mapper 910, and a FEC decoder 912 at a receive/decoding side of the optical channel. In the example device 800, the FEC encoder 804 and the FEC decoder 810 implement mapping/coding and demapping/decoding, respectively. The example communication system 900 includes separate mapping, coding, demapping, and decoding elements in the form of the mapper 904, the FEC encoder 906, the FEC de-mapper 910, and the FEC decoder 912.

In operation, the OTUk frame generator 902 generates frames that include data and parity information positions. Data symbols in the OTUk frame data positions are mapped to data positions in the blocks B as described above. Coding symbols are then computed by the FEC encoder 906 and used to populate the parity information positions in the OTUk frames generated by the OTUk frame generator 902 in the example shown. At the receive side, the OTUk framer 908 receives signals over the optical channel and delineates OTUk frames, from which data and parity symbols are demapped by the demapper 910 and used by the FEC decoder 912 in decoding.

Examples of staircase FEC codes, encoding, and decoding have been described generally above. More detailed examples are provided below. It should be appreciated that the following detailed examples are intended solely for non-limiting and illustrative purposes.

As a first example of a G.709-compatible FEC staircase code, consider a 512×510 staircase code, in which each bit is involved in two triple-error-correcting (1022, 990) component codewords. The parity-check matrix H of this example component code is specified in Appendix B.2, The assignment of bits to component codewords is described by first considering successive two-dimensional blocks B_i, i≥0 of binary data, each with 512 rows and 510 columns. The binary value stored in position (row,column)=(j,k) of B_i is denoted d_i{j,k}.

In each such block, information bits are stored as d_i{j,k}, 0≤j≤511, 0≤k≤477, and parity bits are stored as {j,k}, 0≤j≤511, 478≤k≤509. The parity bits are computed as follows:

For row j, 0≤j≤1, select d_i{j,478}, d_i{j,479}, . . . , d_i{j,509}, such that v=[0, 0, . . . 0,d_i{j,0}, d_i{j,1}, . . . d_i{j,509}]

satisfiesHv^T=0

For row j, 2≤j≤511, select d_i{j,478}, d_i{j,479}, . . . , d_i{j,509}, such that v=[d_i−1{0,l}, d_i−1{1,l}, . . . d_i−1{511,l}, d_i{j,0}, d_i{j,1}, . . . , d_i{j,509}]

satisfiesHv^T=0where l=Π(j−2) and n is a permutation function specified in Appendix B.1.

The information bits in block B_i in this example map to two G.709 OTUk frames, i.e., frames 2i and 2i+1. The parity bits for frames 2i and 2i+1 are the parity bits from block B_i−1. The parity bits of the two OTUk frames into which the information symbols in symbol block B₁ are mapped can be assigned arbitrary values.

As shown in FIG. 10, which is a block diagram illustrating an example frame structure 1000 that reflects the OTN OTUk frame structure, an OTUk frame 1000 includes 4 rows of byte-wide columns. Each row includes 3824 bytes of data 1002 to be encoded, and 256 FEC bytes 1004. Thus, each row consists of 30592 information bits and 2048 parity bits. The mapping of information and parity bits for each row, and their specific order of transmission, are specified as follows:d_i{m mod 512·└m/512┘},30592l≤m≤30592l+30591  Informationd_i−1{m mod 512,478+└m/512┘},2048l≤m≤2048l+2047  Parity

The precise assignment of bits to frames, as a function of l, is as follows:

Frame 2i, row 1: l=0

Frame 2i, row 1: l=1

Frame 2i, row 1: l−2

Frame 2i, row 1: l=3

Frame 2i+1, row 1: l=4

Frame 2i+1, row 1: l=5

Frame 2i+1, row 1: l=6

Frame 2i+1, row 1: l=7.

In another example, each bit in a 196×187 staircase code is involved in two triple-error-correcting (383, 353) component codewords. The parity-check matrix H of the component code is specified in Appendix C.2. The assignment of bits to component codewords is again described by first considering successive two-dimensional blocks B_i,i≥0, of binary data, each with 196 rows and 187 columns. The binary value stored in position (row,column)=(j,k) of B_i is denoted d_i{j,k}.

In each such block, information bits are stored as d_i{j,k}, 0≤j≤195, 0≤k≤156, and parity bits are stored as {j,k}, 0≤j≤195, 157≤k≤186. The parity bits are computed as follows:

For row j, 0≤j≤8, select d_i{j,157}, d_i{j,158}, . . . , d_i{j,186}, such that v=[0, 0, . . . , 0,d_i{j,0}, d_i{j,1}, . . . , d_i{j,186}]

satisfiesHv^T=0.

For row j, 9≤j≤195, select d_i{j,157}, d_i{j,158}, . . . , d_i{j,186}, such that v=[d_i−1{0,l}, d_i−1{1,l}, . . . , d_i−1{195,l}, d_i{j,0}, d_i{j,1}, . . . , d_i{j,186}]

satisfiesHv^T=0.where l=Π(j−9), and Π is a permutation function specified in Appendix C.1.

The information bits in block B_i to one OTUk row. The parity bits for row i are the parity bits from block B_i−1; although there are four rows per OTUk frame, all rows could be numbered consecutively, ignoring frame boundaries. The information and parity bits to be mapped to row i, and their specific order of transmission, are specified as follows:d_i{m mod 196·└m/196┘},180≤m≤30771  Informationd_i−1{m mod 196,157+└m/196┘},0≤m≤5879.  Parity

In this example, eight dummy bits are appended to the end of the parity stream to complete an OTUk row. Furthermore, the first 180 bits in the first column of each staircase block are fixed to zero, and thus need not be transmitted.

Syndrome-based iterative decoding can be used to decode a received signal. Generation of the syndromes is done in a similar fashion to the encoding. The resulting syndrome equation could be solved using a standard FEC decoding scheme and error locations are determined. Bit values at error locations are then flipped, and standard iterative decoding proceeds.

The latency of decoding is a function of number of blocks used in the decoding process. Generally, increasing the number of blocks improves the coding gain. Decoding could be configured in various latency modes to trade-off between latency and coding gain.

What has been described is merely illustrative of the application of principles of embodiments of the invention. Other arrangements and methods can be implemented by those skilled in the art without departing from the scope of the present invention.

For example, the divisions of functions shown in FIGS. 8 and 9 are intended solely for illustrative purposes.

As noted above, the roles of columns and rows in a staircase code could be interchanged. Other mappings between bits or symbols in successive blocks might also be possible. For instance, coding symbols in a block that is currently being encoded could be determined on the basis of symbols at symbol positions along a diagonal direction in a preceding block and the current block. In this case, a certain number of symbols could be selected along the diagonal direction in each block, starting at a certain symbol position (e.g., one corner of each block) and progressing through symbol positions along different diagonals if necessary, until the number of symbols for each coding computation has been selected. As coding symbols are computed, the process would ultimately progress through each symbol position along each diagonal. Other mappings might be or become apparent to those skilled in the art.

In addition, although described primarily in the context of code structures, methods and systems, other implementations are also contemplated, as instructions stored on a non-transitory computer-readable medium, for example.

APPENDIX A: REPRESENTATION OF ELEMENTS IN GF(2^io)

For a root α of the primitive polynomial p(x)=1+x³+x¹⁰, the non-zero field elements of GF(2¹⁰) can be represented asαⁱ,0≤i≤1022,which we refer to as the “power” representation. Equivalently, we can writeαⁱ=b₉α⁹+b₈α⁸+ . . . +b₀,0≤i≤1022;we refer to the integer l=b₉2⁹+b₈2⁸+ . . . +b₀ as the “binary” representation of the field element. We further define the function log(⋅) and its inverse exp(⋅) such that for l, the binary representation of αⁱ, we havelog(l)=i andexp(i)=l.

APPENDIX B: G.709 COMPATIBLE HIGH-GAIN FEC MAPPING

B.1—Specification of Π

Π is a permutation function on the integers i, 0≤i≤509. In the following, Π(M:M+N)=K:K+N is shorthand for Π(M)=K, Π(M+1)=K+1, . . . , Π(M+N)=K+N. The definition of Π is as follows:

Π(0:7)=478:485 Π(8)=0 Π(9:11)=486:488 Π(12)=1

Π(13)=489 Π(14:16)=2:4 Π(17:19)=490:492 Π(20)=5

Π(21)=493 Π(22:24)−6:8 Π(25)=494 Π(26:32)−9:15

Π(33:35)=495:497 Π(36)=16 Π(37)=498 Π(38:40)=17:19

Π(41)=499 Π(42:48)=20:26 Π(49)=500 Π(50:64)=27:41

Π(65:67)=501:503 Π(68)=42 Π(69)=504 Π(70:72)=43:45

Π(73)=505 Π(74:80)=46:52 Π(81)=506 Π(82:128)=53:99

Π(129)=507 Π(130)=100 Π(131)=508 Π(132:256)=101:225

Π(257)=509 Π(258:509)=226:477

B.2—Parity-Check Matrix

Consider the function ƒ which maps an integer i, 1≤i≤1023, to the column vector

$f\left(i\right)=\left[\begin{array}{c}{\beta }_i\\ {\beta }_i^2\\ {\beta }_i^3\\ F\left({\beta }_i\right)\\ \stackrel{\_}{F\left({\beta }_i\right)}\end{array}\right],$ whereβ_i=α^log(i), andF(β_i)=b₂^lb₁^lb₀^l∨b₂^lb₁^l∨b₂^lb₁^lb₀^l,for l the binary representation of β_i, and x is the complement of x. Then, H=[ƒ(1021) ƒ(1022) ƒ(1) . . . ƒ(510) ƒ(511+Π⁻¹(0)) . . . ƒ(511+Π⁻¹(509))].

APPENDIX C: 20% HIGH-GAIN FEC MAPPING

C.1—Specification of Π

Π is a permutation function on the integers i, 0≤i≤186. In the following, Π(M:M+N)=K:K+N is shorthand for Π(M)=K,Π(M+1)=K+1, . . . , Π(M+N)=K+N. The definition of Π is as follows:

Π(0:7)=157:164 Π(8)=0 Π(9:11)=165:167 Π(12)=1

Π(13)=168 Π(14:16)=2:4 Π(17:19)=169:171 Π(20)=5

Π(21)=172 Π(22:24)−6:8 Π(25)=173 Π(25:32)−9:15

Π(33:35)=174:176 Π(36)=16 Π(37)=177 Π(33:40)=17:19

Π(41)=178 Π(42:48)=20:26 Π(49)=179 Π(53:64)=27:41

Π(65:67)=180:182 Π(68)=42 Π(69)=183 Π(73:72)=43:45

Π(73)=184 Π(74:128)=46:100 Π(129)=185 Π(130)=101

Π(131)=186 Π(131:186)=102:156

C.2—Parity-Check Matrix

Consider the function ƒ which maps an integer i, 315≤i≤697, to the column vector

$f\left(i\right)=\left[\begin{array}{c}{\beta }_i\\ {\beta }_i^2\\ {\beta }_i^3\end{array}\right],$ whereβ_i=α^log(i).for l the binary representation of β_i. Then,H=ƒ(315)ƒ(316)ƒ(317) . . . ƒ(697)].

Claims

1. An apparatus comprising: a mapper to receive a stream of data symbols from a transport network and to map the stream of data symbols among data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer, each of the symbol blocks comprising data symbol positions and coding symbol positions; anda Forward Error Correction (FEC) encoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the mapper, to process coding symbols for the coding symbol positions in each symbol block in the sequence, the coding symbols being processed such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with symbols at symbol positions along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code,wherein each symbol block comprises an n row by m column array of symbols, m, n≥1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block Bi based on Di−1 and Bi, where Di−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of Bi−1.

2. The apparatus of claim 1, wherein the mapper maps the stream of data symbols to the symbol positions from one or more Optical channel Transport Unit (OTUk) frames.

3. The apparatus of claim 1, wherein the predetermined symbols comprise all zeros.

4. The apparatus of claim 1, wherein the symbol blocks comprise 512 rows by 510 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (1022, 990) code.

5. The apparatus of claim 4, wherein the mapping comprises mapping information bits of two Optical channel Transport Unit (OTUk) frames to information symbols in each symbol block Bi, i≥1, the method further comprising: mapping the coding symbols in each symbol block Bi−1, i≥2, to parity bits of the two OTUk frames to which the information symbols in symbol block Bi are mapped.

6. The apparatus of claim 1, wherein the symbol blocks comprise 196 rows by 187 columns of bits, and wherein the FEC component code comprises a Bose-Chaudhuri-Hocquenghem (383, 353) code.

7. The apparatus of claim 6, wherein the mapping comprises mapping information bits of one of four rows of an Optical channel Transport Unit (OTUk) frame to information symbols in each symbol block Bi, i≥1, and mapping the coding symbols in each symbol block Bi−1, i≥2, to parity bits of the Optical channel Transport Unit (OTUk) frame to which the information symbols in symbol block Bi are mapped.

8. An apparatus that comprises: an interface to receive a sequence of FEC encoded two-dimensional symbol blocks Bi, i a positive integer, each of the received symbol blocks comprising received versions of data symbols at data symbol positions and coding symbols at coding symbol positions, the coding symbols for the coding symbol positions in each symbol block Bi in the sequence having been processed at a transmitter of the received symbol blocks such that, for each symbol block Bi that has a preceding symbol block Bi−1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi−1, concatenated with symbols at symbol positions along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with symbols at symbol positions along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code; andan FEC decoder device comprising an Application Specific Integrated Circuit (ASIC), operatively coupled to the interface, to decode the received FEC encoded symbol blocks,wherein each symbol block comprises an n row by m column array of symbols, m, n>1, n>m, the FEC encoder device processing the coding symbols for the coding symbol positions in each symbol block Bi based on Di−1 and Bi, where Di−1 is a matrix formed by the ASIC adding (n−m) sets of n predetermined symbols along the one dimension of Bi−1.