Patent Application
20220050948
The present disclosure relates to a standard cell establishment method. More particularly, the present disclosure relates to a standard cell establishment method for optimizing the circuit performance.
Currently for time speed (Propagation Delay) consideration, during circuit simulation, checking devices performance based on current process technology is in need. For each new process generation establishment, in order to find the best performance devices for design application, the process of evaluating devices performance well including devices pitch (width/length/space) and all parasitic devices (capacitance/diode/resistance) is in need.
An aspect of the present disclosure is to provide a standard cell establishment method. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully.
In sum, the embodiments of the present disclosure are to provide a standard cell establishment method, so as to evaluate devices performance well including devices pitch (width/length/space) and all parasitic devices (capacitance/diode/resistance) to find the best performance devices for design application. In the embodiments of the present disclosure, different technology application is included and CV/I for generation evolution are applied. It provides an easy way to setup MOSFET database no matter based on Silicon split or TCAD split, and the circuit performance is optimized by propagation delay.
The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
In order to make the description of the disclosure more detailed and comprehensive, reference will now be made in detail to the accompanying drawings and the following embodiments. However, the provided embodiments are not used to limit the ranges covered by the present disclosure; orders of step description are not used to limit the execution sequence either. Any devices with equivalent effect through rearrangement are also covered by the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” or “has” and/or “having” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.
Reference is made to
It should be noted that the method can be applied to a system or device having a structure with a processor and a memory.
It should be noted that, in some embodiments, the method may be implemented as a computer program. When the computer program is executed by a computer, an electronic device, or the one or more processor. The computer program can be stored in a non-transitory computer readable medium such as a ROM (read-only memory), a flash memory, a floppy disk, a hard disk, an optical disc, a flash disk, a flash drive, a tape, a database accessible from a network, or any storage medium with the same functionality that can be contemplated by persons of ordinary skill in the art to which this invention pertains.
In addition, it should be noted that in the operations of the following method, no particular sequence is required unless otherwise specified. Moreover, the following operations also may be performed simultaneously or the execution times thereof may at least partially overlap.
Furthermore, the operations of the following method may be added to, replaced, and/or eliminated as appropriate, in accordance with various embodiments of the present disclosure.
Reference is made to
In operation S110, an implant split case of a semiconductor cell is set. In some embodiments, the implant split case includes a well split parameter, an S/D split parameter, a LDD split parameter, and/or a halo split parameter.
In operation S120, at least one cell data is collected. In some embodiments, the at least one cell data includes channel length of the semiconductor cell for short channel effect by on/off ratio evaluation.
In operation S130, several characteristic parameters are obtained according to the implant split case. In some embodiments, the implant split case includes a saturation current value and a parasitic capacitance value. In some embodiments, the saturation current value is obtained by operating the semiconductor cell under a direct current (DC) mode. In some embodiments, the parasitic capacitance value is obtained by operating the semiconductor cell under an alternating current (AC) mode.
In some embodiments, the parasitic capacitance is sensitive to the implant split parameters. In some embodiments, the value of CV/I is calculated so as to optimize the saturation current value and the parasitic capacitance value.
In operation S140, the characteristic parameters are applied to a device delay metric so as to obtain a speed parameter. In some embodiments, the device delay metric includes a CV/I methodology. C represents the value of the parasitic capacitance value, I represents the saturation current value, and V represents the voltage value. In some embodiments, in operation S140, device modeling is operated with the parasitic capacitance value and the saturation current value.
In operation S150, whether the speed parameter is better than a previous speed parameter or not is determined. In some embodiments, the previous speed parameter is the speed parameter before setting the implant split case in the operation S110. In some embodiments, the previous speed parameter is the speed parameter of the semiconductor cell established in the last version.
If the speed parameter obtained in operation 5140 is better than the previous speed parameter, operation S160 is operated. On the other hand, if the speed parameter obtained in operation 5140 is not better than the previous speed parameter, operation S110 is operated. When the speed parameter obtained in operation S140 is not better than the previous speed parameter, another implant split case of the semiconductor cell is set, another at least one cell data is collected, and characteristic parameters according to the new implant split case is obtained.
In operation S160, a channel parameter is optimized and whether the channel parameter is optimized successfully or not is determined. In some embodiments, the channel parameter is WN/WP. WN is the width of the depletion region at the P doped area, and WP is the width of the depletion region at the N doped area. In operation 5160, the best WP/WN ratio is confirmed.
If the channel parameter is optimized successfully, operation 5170 is operated. On the other hand, if the channel parameter is not optimized successfully, operation 5110 is operated. When the channel parameter is not optimized successfully, another implant split case of the semiconductor cell is set, another at least one cell data is collected, and characteristic parameters according to the new implant split case is obtained.
In operation S170, a standard cell is established. In some embodiments, the standard cell is a semiconductor cell such as an inverter, a NAND logic gate, or a Nor logic gate.
In some embodiments, the semiconductor cell is a MOSFET semiconductor cell, and the MOSFET semiconductor cell includes several parasitic capacitances. Part of the parasitic capacitance value is increased when the dosage of the well split and/or the S/D split is shallow or heavier, while some other part of the parasitic capacitance value is increased when the dosage of the LDD split and/or halo split is shallow or heavier. The embodiments or the present disclosure optimizes the performance of the semiconductor cell, and both of the effects of the parasitic capacitance value and the saturation current value are under consideration.
In some embodiments, during different version of the development, the cell data of the semiconductor differs, for example, the channel length is shorter. With the embodiments of the present disclosure, the parasitic capacitance value and the saturation current value may be optimized.
According to the embodiment of the present disclosure, it is understood that the embodiments of the present disclosure are to provide a standard cell establishment method thereof, so as to evaluate devices performance well including devices pitch (width/length/space) and all parasitic devices (capacitance/diode/resistance) to find the best performance devices for design application. In the embodiments of the present disclosure, different technology application is included and CV/I for generation evolution are applied. It provides an easy way to setup MOSFET database no matter based on Silicon split or TCAD split, and the circuit performance is optimized by propagation delay.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
In addition, the above illustrations comprise sequential demonstration operations, but the operations need not be performed in the order shown. The execution of the operations in a different order is within the scope of this disclosure. In the spirit and scope of the embodiments of the present disclosure, the operations may be increased, substituted, changed and/or omitted as the case may be.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the present disclosure provided they fall within the scope of the following claims.
