Patent Grant
7605577
The present invention is related to a device and method for starting a low supply bandgap reference circuit.
The objective of a bandgap reference circuit is to provide a voltage that remains constant when the temperature changes. The bandgap reference circuit generates a stable voltage over a temperature range by utilizing two semiconductor circuits, one for providing a voltage that is proportional to absolute temperature (PTAT) and a second for providing a voltage that is complementary to absolute temperature (CTAT). Conventionally the sum of the two circuits is used to provide a temperature-stabilized voltage reference.
Ia=Aa*I0*exp(qVa/kT)
Ib=N*Aa*I0*exp(q(Vb−Ib*Rb)/kT)
If Va is set to be equal to Vb, and Ia=Ib, the above two equations can be simplified as
Ib*Rb=kT/q*ln(N),
so that the current Ib flowing through node B is proportional to absolute temperature.
The output voltage Vbg developed across a resistor in the output stage 110, is a PTAT current Ic, mirrored from Ib, on Rc in series with a negative-temperature-coefficient diode voltage. The Vbg could be designed to be temperature independent if the magnitudes of Ic and Rc are proper to compensate the negative temperature coefficient of a diode.
To reduce power consumption, the feedback loop is generally self-biased. Like other self-biasing circuits, the bandgap reference circuit 100 may have two stable states. The first stable state is when it begins normal operation as designed, and the second stable state is when all the currents are zero (or floating). The circuit can be at zero current when the bandgap circuit initially powers up or as a result of power interruptions. When this zero current state occurs, the bandgap circuit is in a non-started state and the bandgap voltage (Vbg) is improper. A “startup” circuit may be employed to ensure the bandgap reference circuit starts. The purpose of a startup circuit is to ensure the proper operational state can be set during power up without interfering with normal operation of the bandgap circuit once it is started.
To operate the power on reset of the bandgap reference circuit 200, the signal PONRST is controlled to a logical “high” such that the NMOS device N1 is turned on. Turning on the NMOS device N1 biases the PMOS devices P1 and P2 into conduction such that they provide a current to the nodes A and B. Once the current passes through either the node A or the node B, the voltages at the nodes A and B are established and the bandgap circuit is brought out of the non-started state and begins normal operation. The drawback to the power on a reset circuit is that is depends on an external signal PONRST to start the bandgap reference circuit.
The deficiencies of the conventional circuitry and methods for starting a bandgap circuit show that a need still exists for improvement. To overcome the shortcomings of the conventional circuitry, new circuitry and method for starting a bandgap circuit is needed.
This invention is for a startup circuit operating with a bandgap circuit having a predetermined node with a current change proportional to temperature change and a current source connected to the predetermined node comprising: a controllable current switch connected between the predetermined node and a control node of the current source; wherein when the voltage at the predetermined node is floating when starting the bandgap circuit, the controllable current switch biases the current source at the control node whereby the voltage at the predetermined node changes based on the current provided by the current source causing the bandgap circuit to start its normal operation.
The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
This invention relates generally to bandgap reference circuits and more specifically to a system and method of starting a bandgap reference circuit reliably and without interfering with normal circuit operation. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure or characteristic, but every embodiment may not necessarily include the particular feature, structure or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. Parts of the description are presented using terminology commonly employed by those of ordinary skill in the art to convey the substance of their work to others of ordinary skill in the art.
In view of the foregoing, when the Vb and Va are floating, such as when the bandgap reference 300 does not start, the PMOS device Mx controls the controlled current sources P1 and P2 to supply a current through the nodes A and B. Once the current passes through either node A or B, the voltages Va and Vb are established and the bandgap circuit is brought out of the non-started state and begins normal operation.
It will be appreciated by those having skill in the art that in this embodiment Mx should be designed so that the current flowing through Mx is much smaller than through P2. In a bandgap reference circuit operating with a supply voltage of about 1 volt, Vb should be set to a voltage very close to the voltage at node C (Vc) such that P2 is operating in the saturation region. To ensure proper operation, the initial voltage Vb should be less than Vc−|Vth| but the final voltage greater than Vc−|Vth| where Vth is the threshold voltage of Mx.
It is understood that one skilled in the art of integrated circuit design could affect different means to create a bandgap reference than the one shown. It will also be appreciated by those having ordinary skill in the art that this invention can be practiced using other devices or PN junction modules including but not limited to diodes, cascaded PMOS devices connected as diodes or other PN junction module configurations.
One aspect of the present invention is that it provides circuitry and a method for starting a bandgap circuit during initial power-up or following a power interruption. Some of the advantages of the present invention are simplicity, reliability and, that it does not affect normal bandgap circuit operation once started and would only require a small area if implemented monolithically.
In view of the foregoing, if the bandgap circuit fails to start, Vb could be floating causing Mx to control the controlled current sources P1 and P2 to supply current through the nodes A and B. Once current passes through either node A or B, the voltages at the nodes A and B are established and the bandgap circuit is brought out of the non-started state and begins normal operation.
It is understood by those having ordinary skill in the art that in this embodiment Vb should be set to a voltage very close to the voltage at node C (Vc) such that P2 is operating in the saturation region. During normal operation Vb should meet the condition Vb+|Vtp|>Vc to cutoff Mx where Vtp is the threshold voltage of Mx.
In this embodiment, if the bandgap circuit does not start, Vb could be floating near Vss. This could be seen as a logical zero on the input of inverter 502 causing a logical 1 at the output of the inverter 502. The logical 1 output of the inverter 502 drives the NMOS device Mx into conduction, thereby lowering the voltage at the gates of the controlled current sources P1 and P2. The devices P1 and P2 will then supply current through nodes A and B. Once current passes through either node A or B, the voltages at nodes A and B are established and the bandgap circuit is brought out of the non-started state and begins normal operation. Once in normal operation, Vb will be seen as a logical 1 at the input of inverter 502 causing a logical 0 at the output of inverter 502 thus shutting off NMOS device Mx.
These embodiments show one of the advantages of the current invention. Once the bandgap circuit is operating properly, device Mx does not affect the normal operation of the bandgap reference. Other advantages include its simplicity, that it does not draw any current from the output stage of the bandgap circuit and that it only operates if the bandgap circuit fails to start properly.
The above illustration provides many different embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4857823 | Bitting | Aug 1989 | A |
| 6191644 | Srinath et al. | Feb 2001 | B1 |
| 6894473 | Le et al. | May 2005 | B1 |
| 6972550 | Hong | Dec 2005 | B2 |
| 7286002 | Jackson | Oct 2007 | B1 |
| 7321256 | Vasudevan | Jan 2008 | B1 |
| Number | Date | Country | |
|---|---|---|---|
| 20080122526 A1 | May 2008 | US |
