Patent Application
20120229117
The invention relates generally to self-biased reference circuits and, more particularly, to a startup circuit for a low voltage cascode beta-multiplier current generator.
Reference circuits are frequently found in integrated circuit devices. A reference circuit provides a voltage or current level of known value. This voltage or current reference may be duplicated, or mirrored, for use across the integrated circuit. References are used to establish on-chip power supply levels, signal thresholds, and to insure stable operation of analog amplifiers, among other known applications.
Reference circuits can be categorized as non-biased or self-biased. In a non-biased circuit, the reference is generated by simply conducting current through a device or series of devices. For example, current may be conducted through a series of resistors in a voltage divider. Alternatively, current may be conducted through a diode or series of diodes. A diode drop, or summation of diode drops, is used as a reference voltage. These non-biased reference circuits are simple to construct and typically yield predictable results. However, non-biased references may suffer from several disadvantages. For example, resistor dividers are directly dependent on variations in supply voltages. Further, the current draw for the reference circuit can be large unless very high value resistors are used, and such resistors typically require large circuit areas to construct. Diode series are more predictable than resistor dividers but current draw is still an issue. Hence is can be difficult to construct non-biased reference circuits with low power consumption.
Self-biased circuits use transistor biasing, rather than voltage division, to establish the reference current. Ideally, a self-biased circuit is designed such that the voltage or current reference depends solely on device parameters and layout ratios while cancelling out dependence on the supply voltage. The resulting reference current or voltage is said to have higher output impedance since it is less susceptible to changes in the supply voltage. In addition, a self-biasing circuit is designed to operate with low power consumption. Generally, self-biased reference circuits are more suited to low power applications.
A well-known self-biased reference circuit is the beta-multiplier. In the beta-multiplier, a PMOS mirror circuit and a NMOS mirror circuit are arranged such that each mirror circuit replicates the current from the other circuit. Further, one of the mirrors includes a mismatched output transistor—one have a larger width than the input transistor—coupled to an output source resistor. The operating point of the circuit is mathematically determined by the beta (β) of the transistors, the width ratio of the mismatched transistors, and the size of the resistor. The beta-multiplier circuit thereby generates a current reference substantially independent of the voltage supply and with relatively low power consumption.
A significant issued with self-biased reference circuits in general, and beta-multiplier circuits in particular, is that they have two stable DC operating states. One state is an active state where both of the current mirrors conduct current and the desired current reference is generated. The other state is an inactive state where both current mirrors are OFF and no current reference is generated. To avoid the inactive state, it is common in the art to use a dedicated start-up circuit to force the self-biased reference circuit into the active state during integrated circuit power-up. After a start-up operation is completed, the start-up circuit is shut off The active state, self-biased reference circuit is then allowed to settle to its stable operating point.
U.S. Pat. No. 7,755,419 to Rao, el al, discloses an implementation of a beta-multiplier reference circuit with a start-up circuit. Referring now to
The prior art start-up circuit 408 includes (1) a current reference transistor N23460, (2) a current supply transistor P24464, and (3) a switching transistor P25456. When the integrated circuit is powered OFF, VCC 412 and VSS 414 are at the same level. When the integrated circuit is first powered ON, VCC 412 immediately rises to a high level with respect to VSS 414. At that moment, the capacitance of transistor N23460 will cause the initial voltage Start 468 to stay at a low level. Therefore, the gate of transistor P25456 is pulled toward VSS 414, and the transistor is turned ON. Transistor P25456 will conduct current to pull voltage VBN 448 towards VCC 412. This will cause current I1 to flow through transistor N21424 and elevated voltage VBN 448 such that mirror input transistor N21424 and output transistor N22428 are ON. Output current I2 will flow through N22428 to induce gate voltage VBP 452 onto PMOS mirror input transistor P22420 and output transistor P21416. This will cause current I1 to flow. At this point all of the transistors in the beta-multiplier circuit are ON, and the circuit is in the active state. Voltage VBP 452 will bias output transistor P23436 and induce current I3 through output resistor R22440 to generate the voltage reference VREF 444. The start-up circuit 408 is designed such that the transistor P24464 will dominate a voltage divider created by transistors P24464 and N23460. As a result, the voltage Start 468 rapidly rises toward VCC 412 until transistor P25456 is shut OFF. Once P25 shuts OFF, the beta-multiplier circuit 404 will settle to the active state operating point as described above.
There are two practical problems with this prior art implementation. First, the current conducted through the self-biased reference circuit 404 during start-up will substantially exceed the nominal, or steady-state, level to cause much higher power consumption. This higher current is due to a large bias voltage VBN 448 forced onto the NMOS mirror input transistor N21424 during start-up. Further, the large start-up inrush current I1 is replicated in current I2 and output current I3, as well as any other branches referenced to the voltage VBP 452. These large currents are not compatible with low-power operation and can be a serious problem for switched capacitor (SC) filters, dynamic bias circuits, and other sensitive analog circuits. A second problem is that, even during steady, active state operation, the output current I2 of the beta-multiplier circuit 404 has a strong supply voltage dependence (low output impedance). The simple, single-stage PMOS and NMOS current mirrors are influenced by variation in the supply voltage VCC 412 to cause modulation of the currents I1 and I2 (and all subsequent reproductions). Therefore, the current and voltage references from the prior art circuit are not optimal.
Referring now to
The prior start-up circuit 508 includes (1) switch transistor NST 588, (2) current source transistor N5590, and (3) capacitor CST 592. Immediately after powering up the integrated circuit, the voltage START 594 will be about the same as the supply voltage VCC 512 due to the presence of the capacitor CST 592. As a result, the switch transistor NST 588 will be biased to the ON state. Transistor NST 588 will therefore connect together the nodes VPC 568 and VNC 540 which will cause current to flow in the NMOS and PMOS current mirrors 516 and 518. The reference current IREF will bias diode-connected transistor N4576 to generate a bias voltage 578 that is further connected to current source transistor N5590. Current source transistor N5590 discharges the capacitor CST 592 such that the START voltage 594 is eventually pulled to below the turn-on voltage for NST 588. At this point, the start-up circuit 508 is disabled, and the bias-multiplier circuit 504 is allowed to settle to steady state.
It is found that minimum operating supply voltage, or headroom voltage, for the prior art beta-multiplier circuit 504 is governed by the left branch of each current mirror 516 and 518, composed of the diode-connected, NMOS transistors N1520 and NC1524 and the PMOS transistors P1544 and PC1548. The transistors N1520 and NC1524 are typically biased in the sub-threshold region since this operating mode reduces the effect of the R0 tolerance. In this operating mode, the minimum voltage headroom necessary to operate the beta-multiplier circuit 504 is found to be about two NMOS transistor diode drops plus two PMOS transistor saturation voltages, or about VCCmin=2VTN+2VDSATP.
It is further found that the prior art start-up circuit 508 requires a minimum supply voltage of about two NMOS transistor diode drops plus one NMOS transistor drain-to-source voltage and one PMOS transistor gate-to-source voltage, or about VCCmin=2VTN+2VDSN+VGSP. This minimum supply voltage includes the voltage across the NMOS diode-connected transistors N1520 and NC1524, the drain-to-source drop of the switch transistor NST 588, and the gate-to-source drop of the voltage bias transistor PC3560. In addition, the voltage necessary to turn ON the start-up switch transistor NST 588 is found to be in excess of VSTART=2 VTN+VGSNST. This analysis reveals the main disadvantage of the prior art start-up circuit 508. Namely, the minimum supply voltage VCCmin necessary for the correct operation of the start-up circuit 508 is found to be higher than the minimum supply voltage VCCmin required to operate the beta-multiplier current 504. To optimize the combined reference circuit 500, it is essential that the start-up minimum supply voltage be reduced.
A principal object of the present invention is to provide an improved self-biased reference circuit device.
A further object of the present invention is to provide a self-biased reference circuit device with an improved start-up circuit.
Another further object of the present invention is to provide a self-biased reference circuit device with a start-up circuit with a reduced minimum operating supply voltage.
Another further object of the present invention is to provide an improved method to start-up a self-biased reference circuit.
In accordance with the objects of this invention, an improved self-biased reference circuit device is achieved. The self-biased reference circuit device includes a first cascode current mirror, a second cascode current mirror, and a startup circuit. The first cascode current is capable to generate first and second bias voltages in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror is capable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes first and second switches. The first switch is capable to connect the first and fourth bias voltages during startup. The second switch is capable to connect the third bias voltage and an inner drain-source connection in the output stage of the first cascode current mirror during startup.
Also in accordance with the objects of this invention, another improved self-biased reference circuit device is achieved. The self-biased reference circuit device includes a first cascode current mirror, a second cascode current mirror, and a startup circuit. The first cascode current mirror is capable to generate a first bias voltage in response to a first current, to generate a second bias voltage in response to a fourth current, and to generate a second current in response to the first and second bias voltages. The second cascode current mirror is capable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes first and second switches. The first switch is capable to connect the first and fourth bias voltages during startup. The second switch is capable to connect the second and third bias voltages during startup.
Also in accordance with the objects of this invention, an improved method to startup a self-biased reference circuit is achieved. First and second cascode current mirrors are provided. The first cascode current mirror is capable to generate first and second bias voltages in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror is capable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The first and fourth bias voltages are connected. The third bias voltage is connected to an inner drain-source connection in the output stage of the first cascode current mirror. Subsequently, the first and fourth bias voltages are unconnected and the third bias voltage is unconnected from the inner drain-source connection.
Also in accordance with the objects of this invention, another improved method to startup a self-biased reference circuit is achieved. First and second cascode current mirrors are provided. The first cascode current mirror is capable to generate a first bias voltage in response to a first current, to generate a second bias voltage in response to a fourth current, and to generate a second current in response to the first and second bias voltages. A second cascode current mirror is capable to generate a third bias voltage in response to the second current, to generate a fourth bias voltage in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The first and fourth bias voltages are connected. The second and third bias voltage are connected. Subsequently, the first and fourth bias voltages are unconnected and the second and third bias voltage are unconnected.
As such, a novel device and method are disclosed for starting up a low-voltage cascode beta-multiplier reference circuit that does not limit the minimum supply voltage required for the reference circuit. In the present invention, a novel and robust method and circuit device to start up a low-voltage cascode beta-multiplier reference circuit are described. The invention provides a simple start-up circuit that works at supply voltages lower than the minimum supply voltage needed to operate the reference circuit. The invention insures complete startup of the reference circuit via a novel dual-stage scheme. The invention works well with a low-voltage, cascode beta-multiplier design. Other advantages will be recognized by those of ordinary skill in the art.
The present invention and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the invention, taken in conjunction with the following drawings, where like numerals represent like elements, in which:
The second, or PMOS, cascode current mirror 118 includes transistors P1144, PC1148, P2152, and PC2156. The PMOS transistors are configured to form a low-voltage, cascode current mirror 118. This cascode current mirror 118 is operable at a reduced headroom voltage. In this configuration, the minimum required input voltage drop for the PMOS cascode current mirror 118 is only one diode while the output compliance voltage is about two saturation voltages. The PMOS cascode current mirror 118 generates third and fourth bias voltages, VP 164 and VPC 168, respectively, in response to input current I2. To achieve the low supply voltage operation, the PMOS cascode current mirror 118 requires that bias voltage VPC 168 be generated by flowing current through diode-connected transistor PC3160. Transistors N3174, N4176, P4170, and PC4172 allow the third and fourth bias voltages VP 164 and VPC 168 to mirror the reference current Iref to the bias voltage generating transistor PC3160. Transistors P5180 and PC5182 and resistor R1184 are used to generate reference voltage VREF 186.
As an important feature of the present invention, a novel start-up circuit 108 is used. The start-up circuit 108 includes a first switch transistor NST1188 and a second switch transistor NST2196. The two-switch, or dual-stage, start-up circuit 108 can be successfully integrated in alternative beta-multiplier current references, such as the embodiment shown in
Referring again to
As another important feature of the present invention, the second switch transistor NST2196 is coupled between the third bias voltage VP 164 and an inner drain-source connection 130. It is found that, while the current flowing through the first switch transistor NST1188 during start-up provides the correct biasing of the node VPC 168 and the node VN 136, this alone does not guarantee proper start-up of the beta-multiplier circuit 104. The additional, second switch transistor NST2196 ensures current flow in the output side of the NMOS cascode current mirror 116. In particular, the second switch transistor NST2196 ensures current flow in the second start-up branch defined by transistors P2152, PC2156, NST2196, and N2128 where transistors PC2156 and N2128 are already enabled (pre-biased) by the operation of the first switch transistor NST1188 and the first start-up branch. The required turn-on voltage for the second switch transistor NST2196 is only about VSTART2=VDSN2+VGSNST2. In addition, the supply voltage required to allow current flow through start-up path controlled by the second switch transistor NST2196 during start-up is only about VCCmin=VDSN1+VDSNST2+VGSP2. Again, the minimum turn-on voltage and operating voltage for the second part of the start-up circuit 108—controlled by the second switch transistor NST2196—are less than the minimum operating voltage VCCmin required for operation of the beta-multiplier circuit 104 so that this is not the limiting factor for low voltage circuit operation.
Immediately after powering up the integrated circuit, the voltage START 194 will be the about same as the supply voltage VCC 112 due to the presence of the capacitor CST 192. As a result, the first switch transistor NST1188 and the second switch transistor NST2196 will be biased to an ON state. Transistor NST1188 will connect together the nodes VPC 168 and VN 136 to cause current to flow in the NMOS and PMOS current mirrors 116 and 118. The reference current IREF will bias diode-connected transistor N4176 to generate a bias voltage 178 that is further connected to the current source transistor N5190 of the start-up circuit 108. Current source transistor N5190 discharges the capacitor CST 192 such that the START voltage 194 eventually falls to below the turn-on voltage for NST1188. At this point, the start-up circuit 108 is disabled, and the bias-multiplier circuit 104 is allowed to settle to steady state.
The main function of the additional, second switch transistor NST2196 is to ensure initial current flow I2 in transistor P2152 of the right branch of the beta-multiplier 118. Via the PMOS cascode mirror 118, and particularly transistors P1144 and P2152, this current I2 is mirrored to generate current I1 in the left-side branch. Current I1 then biases the VNC bias voltage 140 to turn ON the diode-connected NC1124 transistor and the mirror transistor NC2132. This final process completes the full start-up of the low voltage cascode beta-multiplier 104.
The first cascode current mirror 216 includes transistors N1220, NC1224, N2228, and NC2232. These NMOS transistors are configured to form a low-voltage, cascode current mirror 216. In this configuration, the minimum required input voltage drop for the NMOS cascode current mirror 216 is only one diode while the output compliance voltage is about two saturation voltages. A resistor R0234 in the source path of transistor N2228 is included to overlay the beta-multiplier function onto the output current I2. To achieve the low supply voltage operation, the NMOS cascode current mirror 216 requires that a second bias voltage VNC 240 be generated by flowing current Iref through diode-connected transistor NC4276. The NMOS cascode current mirror 216 generates a first bias voltage VN 236 in response to the input current Il.
The second, or PMOS, cascode current mirror 218 includes transistors P1244, PC1248, P2252, and PC2256 as in the prior embodiment. The PMOS transistors are configured to form a low-voltage, cascode current mirror 218—that is a cascode current mirror operable at a reduced headroom voltage. In this configuration, the minimum required input voltage drop for the PMOS cascode current mirror 218 is only one diode while the output compliance voltage is about two saturation voltages. The PMOS cascode current mirror 218 generates third and fourth bias voltages, VP 264 and VPC 268, respectively, in response to input current I2. To achieve the low supply voltage operation, the PMOS cascode current mirror 218 requires that bias voltage VPC 268 be generated by flowing current through diode-connected transistor PC3260. Transistors N3274, N4276, P4270, and PC4272 allow the third and fourth bias voltages VP 264 and VPC 268 to mirror the reference current Iref to the bias voltage generating transistor PC3260. Transistors P5280 and PC5282 and resistor R1284 are used to generate reference voltage VREF 286.
As an important feature of this embodiment of the present invention, a novel start-up circuit 208 is used. The start-up circuit 208 includes a first switch transistor NST1288 and a second switch transistor NST2296. While the first and second switch transistors NST1288 and NST2296 are shown as NMOS transistors, it is understood that other embodiments may be substituted, such as PMOS transistors properly biased to turn on during start-up. In addition, the start-up circuit 208 includes a current source transistor N5290, and a capacitor CST 292. It is further understood that these components may be replaced with other known embodiments such as flipping the capacitor and transistor or replacing the NMOS transistor M5290 with a PMOS transistor.
As another important feature of this embodiment of the present invention, the first switch transistor NST1288 is coupled between the first bias voltage VN 236 and the fourth bias voltage VPC 268. The connection of the first switch transistor NST1288 again differs from that of the prior art where the single switching transistor is connected from the PMOS cascode bias voltage VPC to the NMOS cascode bias voltage VNC. By connecting to the gate of the lower NMOS transistor N1220 of the NMOS cascode stack, the required turn-on voltage for the first switch transistor NST1288 is again reduced by one diode drop to about VSTART1=VTN1+VGSNST1. Because of this key difference, the supply voltage required to allow current flow through start-up path controlled by the first switch transistor NST1288 during start-up is reduced to about VCCmin=VTN1+VDSNST1+VGSPC3. Unlike the prior art, the minimum turn-on voltage and operating voltage for the first part of the start-up circuit 208—controlled by the first switch transistor NST1288—are less than the minimum operating voltage VCCmin required for operation of the beta-multiplier circuit 204 so that this is not the limiting factor for low voltage circuit operation.
As another important feature of this embodiment of the present invention, the second switch transistor NST2296 is coupled between the second bias voltage VNC 240 and the third bias voltage VP 264. It is found that, while the current flowing through the first switch transistor NST1288 during start-up provides the correct biasing of the node VPC 268 and the node VN 236, this alone does not guarantee proper start-up of the beta-multiplier circuit 204. The additional, second switch transistor NST2296 ensures current flow in the output side of the NMOS cascode current mirror 216. In particular, the second switch transistor NST2296 ensures current flow in the second start-up branch defined by transistors P2252, PC2256, NST2296, NC2232, and N2228 where transistors PC2256 and N2228 are already enabled (pre-biased) by the operation of the first switch transistor NST1288 and the first start-up branch. The required turn-on voltage for the second switch transistor NST2296 is only about VSTART2=VTN4+VGSNST2. In addition, the supply voltage required to allow current flow through start-up path controlled by the second switch transistor NST2296 during start-up is only about VCCmin=VTN4+VDSNST2+VGSP2. Again, the minimum turn-on voltage and operating voltage for the second part of the start-up circuit 208—controlled by the second switch transistor NST2296—are less than the minimum operating voltage VCCmin required for operation of the beta-multiplier circuit 204 so that this is not the limiting factor for low voltage circuit operation.
Immediately after powering up the integrated circuit, the voltage START 294 will be about the same as the supply voltage VCC 212 due to the presence of the capacitor CST 292. As a result, the first switch transistor NST1288 and the second switch transistor NST2296 will be biased to an ON state. Transistor NST1288 will connect together the nodes VPC 268 and VN 236 to cause current to flow in the NMOS and PMOS current mirrors 216 and 218. The reference current IREF will bias diode-connected transistor N4276 to generate the second bias voltage 240 that is further connected to the current source transistor N5290 of the start-up circuit 208. Current source transistor N5290 discharges the capacitor CST 292 such that the START voltage 294 eventually falls below the turn-on voltage for NST1288. At this point, the start-up circuit 208 is disabled, and the bias-multiplier circuit 204 is allowed to settle to steady state.
The main function of the additional, second switch transistor NST2296 is to ensure initial current flow I2 in transistor P2252 of the right branch of the beta-multiplier 204. Via the PMOS cascode mirror 218, and particularly transistors P1244 and P2252, this current I2 is mirrored to current I1 in the left-side branch. Current I1 then generates the VN bias voltage 236 to turn ON the diode-connected N1220 transistor and mirror transistor N2228. This final process completes the full start-up of the low voltage cascode beta-multiplier 204.
A novel device and method are disclosed for starting up a low-voltage cascode beta-multiplier reference circuit that does not limit the minimum supply voltage required for the reference circuit. In the present invention, a novel and robust method and circuit device to start up a low-voltage cascode beta-multiplier reference circuit is described. The invention provides a simple start-up circuit that works at supply voltages lower than the minimum supply voltage needed to operate the reference circuit. The invention insures complete startup of the reference circuit via a novel dual-stage scheme. The invention works well with a low-voltage, cascode beta-multiplier design.
The above detailed description of the invention, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the invention have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 11368007.8 | Mar 2011 | EP | regional |
