Claims
- 1. A state machine that has a latch means for storing data representing an intended state and a state control means for producing data representing a subsequent state according to an intended state provided by said latch means and a detection signal, and every time said latch means latches data provided by said state control means synchronously with a clock, said state machine comprising:
- a state transition stopping means for stopping state transition and storing a state at that time instant;
- a transition stoppage specification data input means for specifying whether normal operation should be performed or said state transition stopping means should be activated to stop state transition, said state transition control circuit enabling retention of an intended state;
- a state data input means for inputting data representing an intended state from which an operation of the state machine starts, said intended state being optionally designated;
- a selecting means for selecting either data provided by said state control means or data provided by said state data input means so as to supply selected data as data representing a subsequent state to said latch means; and
- a control data input means for inputting control data for use in controlling selection performed by said selecting means, said state machine making it possible to designate an intended state directly at an external unit;
- wherein said state data input means and said control data input means are externally and directly writable registers.
- 2. A state machine according to claim 1, wherein said state data input means and said control data input means are external ports.
- 3. A state machine according to claim 1, wherein said state transition stopping means is a circuit for substantially stopping input of said clock to said latch means.
- 4. A state machine according to claim 3, further comprising:
- a state dat input means for inputting data representing an intended state from which an operation of the state machine starts, said intended state being optionally designated;
- a selecting means for selecting either data provided by said control means or data provided by said state dat input means so as to supply selected data as data representing a subsequent state to said latch means; and
- a control data input means for inputting control data for use in controlling selection performed by said selecting means, said state machine making it possible to designate an intended state directly at an external unit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-224655 |
Sep 1994 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 08/494,087 filed Jun. 23, 1995, now abandoned.
US Referenced Citations (19)
Non-Patent Literature Citations (1)
Entry |
Katoozi, M.; Soma, M.; "Built-in test of CMOS state machines with realistic faults"; IEEE Journal of Solid-State Circuits; pp. 482-489, Apr. 1990. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
494087 |
Jun 1995 |
|