Processors utilize one or more arithmetic logic units (ALUs) to perform high speed, power-hungry mathematical operations like addition, subtraction, multiplication and division. An integral part of the ALU is an adder that is utilized to add strings of binary numbers together. The speed of the adder is based on the number of levels of computation required to add the strings. A carry ripple adder circuit includes a string of adders where a carry calculated for one bit is forwarded to the next bit and so one. Such an adder would be relatively slow since each adder would need to wait for the previous adder to calculate the carry bit.
Various adders have been developed to reduce the number of levels of computation. Carry look ahead adders calculate carry propagate (p) and generate (g) signals for each bit position in parallel. Group carry propagates (P) and generates (G) are calculated based on p and g. Additional levels of P and G are calculated based on previous levels until the P and G have been propagated through for the most significant bit. Conditional sum adders calculate two possible sums per carry blocks based on what the carry value into the least significant bit of the carry block is (carry from previous block).
The features and advantages of the various embodiments will become apparent from the following detailed description in which:
The P and G values may be calculated for the current location (i) and all previous locations in the group. For example, for groups of two the P and G values may be calculated for locations i and i−1. As illustrated, at the first level, the P and G values (P1, G1) are generated for a first location (bit 1) based on the p and g values for bits 0 and 1 and for a second location (bit 3) based on the p and g values for bits 2 and 3. For the second level, the P and G values (P2, G2) are generated for a first location (bit 3) based on the P1 and G1 values from the first and second locations (bits 1 and 3 respectively). The P values for the first level (P1) may equal pipi−1 and for subsequent levels (P2, P3) may equal PiPi−1. The G values for the first level (G1) may equal gi−1pi+gi and for subsequent levels (G2, G3) may equal Gi−1Pi+Gi. The P values may be generated with an AND gate 230 where the inputs are pi and pi−1 (Pi and Pi−1) and the G values may be generated with logic 240 where the inputs are gi, gi−1 and pi (Gi, Gi−1 and Pi). The logic 240 may include an AND gate 242 and an OR gate 244. The inputs to the AND gate 242 may be gi−1 and pi (Gi−1 and Pi) and the inputs to the OR gate 244 may be the output of the AND gate 242 and gi (Gi).
For each bit position gi*pi=gi, so that Gi can be written as gi−1pi+gipi or pi(gi−1+gi). If we factor out the pi then a pseudo Gi (G′i) can be written as gi−1+gi which is the Ling equation for group carry generates where the group is two. A corresponding pseudo Pi (P′i) can be written as pi−2*pi−1 which is the Ling equation for group carry propagates where the group is two. The G′i and P′i may be generated directly from the inputs where G′i=ai−1bi−1+aibi, and P′i=(ai−2+bi−2)*(ai−1+bi−1). The pi that is factored out may be propagated through a prefix tree and utilized in a conditional summer.
The number of delay stages (levels of circuitry required to propagate P′, G′ through the adder) in the second stage 320 is LOGXN. As illustrated, the second stage 320 generates group carries for two groups at a time and the number of bits in the adder 300 is 8 so that there are three delay stages. The third stage 330 is a conditional summer that selects the sum for each bit based on some condition. As the first stage 310 is not included in the critical path, the critical path (number of delay stages) may be reduced to LOGXN+1.
The use of the logic 410, 420 to calculate the Ling carry and propagate signals (G′1, P′1) directly from the inputs enables elimination of the first stage logical level (e.g., 310 of
For subsequent levels, the P′ values may be calculated as P′iP′i−1 and the G′ values may be calculated as Gi−1Pi+Gi. The P′ values may be generated with an AND gate (not illustrated) where the inputs are P′i and P′i−1 and the G values may be generated with logic 430 where the inputs G′i, G′i−1 and P′i. The logic 430 may include an AND gate 432 and an OR gate 434. The inputs to the AND gate 432 may be G′i−1 and P′i and the inputs to the OR gate 434 may be the output of the AND gate 432 and G′i. As illustrated, for the second level, the G′ value (G′2) is generated for a first location (bit 3) based on the P′1 value for the second location (bit 3) and G′ 1 values for the first and second locations (bits 1 and 3 respectively). Since there is no P′ 1 signal for the first location (bit 1) a P′2 value can not be calculated for the first location (bit 3).
Focusing on bits 4-7 we can see that the control signal for these four bits is G′2(3), the second level propagated group carry generate from bits 0-3. The true carry into bits 4-7 would be G′2(3)*p3. For bit 4, the inputs to the summer 500 are X4 and p3, where Xi denotes ai xor bi. The X4 and p3 are inputs to a XOR gate and X4 and the output of the XOR gate are the inputs to the multiplexer 510. Accordingly, the multiplexer may select X4 or X4 xor p3 based on the G′2(3) input. If the G′2(3) is 0 X4 is selected as the output and if G′2(3) is 1 the X4 xor p3 output is selected. That is, the p3 value that was extracted from the calculation of G′1(3) and thus was not part of the true carry is factored back in based on the G′2(3) result.
For bit 5, the inputs to the summer 500 are X5, P′(5) and g4, where P′(5) is p3p4. The X5 and g4 are inputs to a first XOR gate, P′(5) and g4 are inputs to an OR gate, the outputs of the first XOR and the OR are inputs to a second XOR and the outputs of the first and second XORs are inputs to the multiplexer 510. Accordingly, the multiplexer may select X5 xor g4 or X5 xor (g4+P′2(5)) as outputs based on the G′2(3) input. If the G′2(3) is 0, X5 xor g4 is selected as the output. If G′2(3) is 1, the X5 xor (g4+P′2(5)) or X5 xor (g4+p3p4) in expanded form is selected as the output. Again, the p3 value that was extracted from the true carry is factored back in based on the G′2(3) result.
For bit 6, the inputs to the summer 500 are X6, P2′(5) and G′2(5), where P′2(5) is P′(5)p5 which is p3p4p5, and where G′2(5) is G′(5)p5 which is p5(g4+g5). The X6 and G′2(5) are inputs to a first XOR gate, P′2(5) and G′2(5) are inputs to an OR gate, the outputs of the first XOR and the OR are inputs to a second XOR and the outputs of the first and second XORs are inputs to the multiplexer 510. Accordingly, the multiplexer may select X6 xor G′2(5) or X6 xor (G′2(5)+P′2(5)) as outputs based on the G′2(3) input. If the G′2(3) is 0, X6 xor G′2(5) or X6 xor p5(g4+g5) in expanded form is selected as the output. If G′2(3) is 1, the X6 xor (G′2(5)+P′2(5)) or X6 xor (p5(g4+g5)+p3p4p5) in expanded form is selected as the output. Again, the p3 value that was extracted from the true carry is factored back in based on the G′2(3) result.
For bit 7, the inputs to the summer 500 are X7, P2′(6) and G′2(6), where P′2(6) is P′(7)P′(5) which is p3p4p5p6, and where G′2(6) is g6+P′(7)G′(5) which is g6+p5p6(g4+g5). The X7 and G′2(6) are inputs to a first XOR gate, P′2(6) and G′2(6) are inputs to an OR gate, the outputs of the first XOR and the OR are inputs to a second XOR and the outputs of the first and second XORs are inputs to the multiplexer 510. Accordingly, the multiplexer may select X7 xor G′2(6) or X7 xor (G′2(6)+P′2(6)) as outputs based on the G′2(3) input. If the G′2(3) is 0, X7 xor G′2(6) or X5 xor (g6+p5p6(g4+g5)) in expanded form is selected as the output. If G′2(3) is 1, the X4 xor (G′2(5)+P′2(5)) or X4 xor (g6+p5p6(g4+g5)+p3p4p5p6) is selected as the output.
Adders (e.g., prefix tree adders) may be used to multiply a binary number by three (a three times (3×) adder). 3× adders may multiply a binary number by three by shifting the binary number one bit to the left and then adding the binary number and the binary number shifted to the left. The result of the addition is a multiple of three of the binary number. A static logic Ling adder (such as that depicted in
Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.