Claims
- 1. A semiconductor memory device comprising:
- a plurality of memory cells arranged near the intersecting points of a plurality of pairs of complementary data lines and a plurality of word lines, the select terminals thereof being connected to their corresponding word lines and the pairs of input/output terminals being connected to their corresponding pairs of complementary data lines; and
- a parity check circuit which is connected to said plurality of pairs of data lines, and effects the parity checking based on a plurality of complementary signals read out from a plurality of memory cells connected to a word line that is selected;
- wherein said parity check circuit includes:
- first and second FETs of which the gate terminals are connected to one data line of the pairs of complementary data lines, and third and fourth FETs of which the gate terminals are connected to the other data line,
- means which connects a common connection point of the input/output terminals on one of said first and third FETs corresponding to the first pair of complementary data lines to a common connection point of the input/output terminals on one side of said second and fourth FETs corresponding to the second pair of complementary data lines close to said first pair of complementary data lines, and
- means which connects a common connection point of the input/output terminals on one of said second and fourth FETs corresponding to said first pair of complementary data lines to a common connection point of the input/output terminals on one of said first and third FETs that correspond to said second pair of complementary data lines.
- 2. A semiconductor memory device according to claim 1, wherein said parity check circuit further comprises:
- means which supplies a first power source voltage level to a common connection point of input/output terminals of one of said first and third FETs corresponding to a pair of complementary data lines arranged at one end portion of said plurality of pairs of complementary data lines; and
- means which supplies a second power source voltage level to a common connection point of input/output terminals of one of said second and fourth FETs.
- 3. A semiconductor memory device according to claim 2, wherein said parity check circuit further comprises:
- an output circuit that forms a parity check detect signal based on a signal of a common connection point of the input/output terminals on the other FET of said first and fourth FETs corresponding to a pair of complementary data liens arranged at the other end portion of said plurality of pairs of complementary data lines, and based on a signal of a common connection point of the input/output terminals on the other FET of said second and third FETs.
Priority Claims (1)
Number |
Date |
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Kind |
1-55938 |
Mar 1989 |
JPX |
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Parent Case Info
This application is a divisional application of U.S. Ser. No. 07/490,745, filed Mar. 8, 1990 now U.S. Pat. No. 5,195,075.
US Referenced Citations (9)
Foreign Referenced Citations (3)
Number |
Date |
Country |
52-21733 |
Feb 1977 |
JPX |
53-73039 |
Jun 1978 |
JPX |
57-198592 |
Jun 1982 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Electronic Technology, vol. 23, No. 3, 1981 (pp. 31-32). |
Divisions (1)
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Number |
Date |
Country |
Parent |
490745 |
Mar 1990 |
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