Shepard, Kenneth L. et al., “Noise in Deep Submicron Digital Design”, Proc. of the IEEE/ACM International Conference on Computer-Aided Design, Nov. 1996, pp. 524-531. |
Chen, Pinhong et al. “Towards True Crosstalk Noise Analysis”, Int. Conf. on Computer-Aided Design, 1999, pp. 132-137. |
Xiao, Tong et al., “Worst Delay Estimation in Crosstalk Aware Static Timing Analysis”, Int. Conf. on Computer-Aided Design, 2000, pp. 115-120. |
Scheffer, Lou, “What is the Appropriate Model for Crosstalk Control?”, 13th Symp. on Integrated Circuits and Systems Design, 2000, pp. 315-320. |
Alpert, Charles J. et al., “Buffer Insertion for Noise and Delay Optimization”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 11, Nov. 1999, pp. 1633-1645. |
Chen, Lauren Hui et al, “Aggressor Alignment for Worst-Case Crosstalk Noise”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 5, May 2001, pp. 612-621. |
Shepard, K.L. et al., “Cell characterization for noise stability”, IEEE 2000 Custom Integrated Circuits Conference, 2000, pp. 91-94. |
Levy, Rafi et al., “ClariNet: A noise analysis tool for deep submicron design”, Design Automation Conference, 2000, pp. 233-238. |
CeltIC User Guide, Cadence Design Systems, Inc., Aug. 2002. |
PacifIC User Guide, Cadence Design Systems, Inc., Aug. 2002. |