Patent Grant
7219250
The invention relates to a method and an apparatus for detecting status indications output by a hardware device. Generally, for detecting or latching indication pulses or status indications in a storage device, the status indications are output by the hardware device synchronized to a first reference clock and a processing device or other monitoring equipment may want to read the status indication, for example a bit, synchronized to a second reference clock which has a different phase and/or frequency to said first reference clock. Therefore, status indications may get lost due to the phase and/or frequency mismatch between the two different “clock domains”.
The present invention in particular addresses the problem how a stable transfer of indications from the first reference clock domain to the second reference clock domain can be achieved for arbitrary phase relationships between the first and second reference clock.
ASICS (Application Specific Integrated Circuits) can be used to manipulate and/or to monitor data streams. Within such ASICS there are typically circuits and functional blocks which generate short pulse-shaped status or error indications. Furthermore, the ASICS must update a latch register as soon as the indication was fetched from the hardware device. As already mentioned above, a register or flip-flop latching the status indication (e.g. a bit) operates in a different clock domain than the circuitry processing the latched indication (e.g. a microcontroller interface). Consequently, a synchronization functionality is needed to avoid metastability when accessing the latch register.
Metastability can occur if the setup-hold window of a flip-flop (FF) is violated. When metastability occurs the logical state of the FF output can not be predicted and furthermore the exact point of time at which the undefined logical value settles to a defined state can only be given to a certain probability of error. Of course, in principle even a metastable flip-flop can be read out. However, it is completely uncertain which logical value is read out due the metastability.
Furthermore, the synchronization and update functionality must not overlap the detection of an error indication, even if the update request and a new indication coincide in time.
A typical environment where there is need for latching such status indication is for example in the framework of SONET/SDH applications. For such an application a circuitry shall latch short, clock cycle long indications, synchronize them to a microcontroller interface and provide an update at read functionality, while not covering new indications during the read and update phase. For example, a SDH/SONET ASIC shall receive, monitor and process potentially 16 SDH/SONET data steams. In this case, clocks are recovered from the data steams in SDH/SONET applications and therefore the ASIC involves 16 clock domains with the same nominal clock frequency but unpredictable phase relationship amongst each other and to the microcontroller interface which enables a controlling and configuring controller to access the latched indications. The latched indications are supposed to be available until the microcontroller reads them and thereby updates them to the new indication status not covering indications that came in during the read out phase. Therefore, by only two consecutive read accesses the microcontroller is able to detect a change in the indication status.
The above problem of updating and latching (detecting) status indications from a hardware device is a general task not limited to the above SONET/SDH application. For example, the German patent application P 198 14 359 (corresponding PCT/EP99/0226 (WO99/50727) and U.S. Ser. No. 09/280,984 now U.S. Pat. No. 6,408,366) by the same applicant describes the problems of storing and accessing status indications as principally shown in
A hardware device HW outputs status indications SI, for example synchronized to the first reference clock CLK_A, to an input storage means ISM belonging to the clock domain A. The status indications SI′ are transferred from the input storage means ISM to the output storage means OSM. For example, the read request RDRQ is output by a processing means PROC in order to read out the status indications SI″ from the output storage means OSM. The reading out of the status indications SI″ may be synchronized to a second clock CLK_B belonging to the clock domain B whilst the transfer of status indications SI′ from the input storage means ISM may be synchronized to a first clock CLK_A belonging to the clock domain A such that generally the readout and the transfer, respectively, do no take place at the same timing (see also the times PD1, PD2 in
In the aforementioned patent applications it is described that the status indication (bits) are collected in the input storage means ISM and are then transferred or copied to several registers in the output storage means OSM such that one or more processing means PROC can access the status indications in the output storage means OSM simultaneously.
The U.S. Pat. No. 5,357,613 discloses a similar circuit as shown in
The U.S. Pat. No. 5,638,015 also discloses a configuration similar to
As explained above, conventional technologies cannot be used generically for all phase and frequency relations between indication latching and indication fetching clock domains (hereinafter referred to as clock domain A and clock domain B). The classic synchronization stage approach, as for example described in the aforementioned U.S. Pat. No. 5,357,613 and U.S. Pat. No. 5,638,015, for example does not work if the fetching clock domain B works on a slower clock CLK_B than the latching domain A, which operates on the clock CLK_A. Therefore, conventional techniques may fail to synchronize or do not deliver the stored (latched or detected) indication as fast as possible if clear at read functionality is required at arbitrary phase/frequency relations.
Therefore, conventionally there is not known a status indication detection apparatus and a status indication detection method which incorporates all three functions of latching, synchronization and update at the read time simultaneously without missing incoming status indications.
As described above with reference to the prior art and in particular with respect to the above
Therefore, the object of the present invention is to provide a status indication detection method and apparatus, which can guarantee for every frequency and phase relationship between the latching reference clock and the readout clock that no status indication gets lost, i.e. that for every frequency and phase relationship a status can be stably transferred to an output register from an input register whilst any new incoming status indication can be read in without being lost.
This object is solved by a method for detecting status indications wherein raw status indications are read into an input storage stage of a first reference clock domain such that the status indications are available in said input storage stage synchronized to a first reference clock of said first reference clock domain; and said read status indications are input into an output storage stage of a second reference clock domain, such that the status indications are available in said output storage stage synchronized to a second reference clock of said second reference clock domain, said second reference clock of said second reference clock domain having a different phase and/or frequency to said first reference clock; wherein said status indications in said input storage stage are shifted to an intermediate storage stage of said first reference clock domain synchronized to said first reference clock; and in response to a read request signal being input into said output storage stage a hold signal is applied to said intermediate storage stage for holding a current status indication in said intermediate storage stage and blocking a shifting of a new status indication from said input to said intermediate storage stage; and during said hold signal a read out signal is applied to said output storage stage for reading the current status indication in said intermediate storage stage into said output storage stage synchronized to said second reference clock.
Furthermore, this object is solved by a status indication detection apparatus for detecting raw status indications, comprising an input storage stage of a first reference clock domain for reading said raw status indications such that the status indications are available in said input storage stage synchronized to a first reference clock of said first reference clock domain; and an output storage stage of a second reference clock domain into which said read status indications are input such that the status indications are available in said output storage stage synchronized to a second reference clock of said second reference clock domain said second reference clock of said second reference clock domain having a different phase and/or frequency to said first reference clock; wherein an intermediate storage stage of said first reference clock domain is provided between the input storage stage and the output storage stage, wherein said status indications in said input storage stage are shifted to an intermediate synchronized to said first reference clock; said output storage stage comprises a control pulse generator for generating a read out signal to be applied to an output register of said output storage stage for reading the current status indication in the intermediate storage stage into said output register synchronized to said second reference clock in response to a read request signal being input into said output storage stage; and said intermediate storage stage comprises a synchronization stage for generating a hold signal to be applied to an intermediate register of said intermediate storage stage for holding a current status indication in said intermediate register and for blocking a shifting of a new indication from said input to said intermediate storage stage.
Thus, in accordance with the present invention the status indication detection apparatus comprises a further stage called the intermediate storage stage belonging to the latching domain. The intermediate storage stage is controlled in such a manner that a current status indication in the intermediate storage stage is locked for the time period of the hold signal such that the output storage stage can apply a readout pulse synchronous to said second reference clock during the hold signal duration. In this case the readout pulse can be still synchronized to the second reference clock whilst the hold signal can be synchronized to the first reference clock. Thus, it does not matter what phase and/or frequency relationship the two reference clocks have.
Furthermore, the format of the read status indications is not necessarily identical to the format of the raw status indications. For example, the raw indications may correspond to occurrences of events while the read indications to a counted number of raw indications.
The present invention also has the advantage that a value fetched by the output storage stage from the intermediate storage stage will always be the most recent status (e.g. error) indication properly transmitted over the clock domain borders.
Preferably, during said hold signal a new raw status indication is read into and kept stored in the input storage stage; and after the hold signal ceases the status indication in the input storage stage is shifted to said intermediate storage stage synchronized to said first reference clock. At the same time, new raw status indications may be input into the input storage stage and at least for the time period of the hold signal they are kept in the input storage stage and will be prevented from being shifted to the intermediate storage stage. Thus, the generation of the readout signal synchronized to the second reference clock during the duration of the hold signal prevents the loss of any status indications despite arbitrary phase and/or frequency relationships of the two reference clocks.
Whilst the read request signal can have any phase with respect to the first or second reference clock, preferably in accordance with one embodiment the read request signal is input into the output storage stage synchronized with said second reference clock. Thus, it can be guaranteed that the generation of the readout signal is also synchronized to said second reference clock.
In accordance with another embodiment, the hold signal is applied to said intermediate storage stage synchronized with said first reference clock.
Furthermore, in accordance with another embodiment of the invention, the status indication from the input storage means is kept in the input storage stage at least for one more first reference clock before the status indication is shifted to the intermediate storage stage.
In accordance with another embodiment of the invention, in response to said read request signal, said control pulse generator generates a read lock pulse synchronized to said second reference clock and supplies it from said second reference clock domain to said first reference clock domain, said read lock pulse having a pulse length being the sum of a time duration needed to allow a safe synchronisation of said read lock pulse in said first reference clock domain with said first reference clock and a time duration to read said status indication from said intermediate storage stage into the output storage stage.
Advantageously said synchronisation stage of said intermediate storage stage synchronizes said read lock pulse to said first reference clock and derives said hold signal with a pulse length of at least the duration of the synchronized read lock pulse from said synchronized read lock pulse.
Advantageously said synchronisation stage derives said hold signal in such a manner that it has a duration of at least one and preferably two periods of said first reference clock and covering at least one clock pulse of the second reference clock.
Advantageously said pulse generator generates said read out signal synchronized to the end of the read lock pulse.
In accordance with another embodiment of the invention, an input update control means of said input storage stage generates a clear pulse for deleting status indications from the input storage stage, said clear pulse being generated after the ceasing of said hold signal. A check whether the contents of said input storage stage and said intermediate storage stage coincide can avoid that the input storage stage is updated with a status indication although the intermediate storage stage has not sampled the old content of the input storage stage as yet. However, alternative solutions to avoid a loss of status indications are possible.
Further preferably the read request signal is synchronized to said second reference clock and has a duration of one second reference clock period. That is, the read request signal only serves as a basis for generating the read lock pulse which can be much longer than one second reference clock period, for example for the case when the second reference clock has a much higher frequency than the first reference clock.
Further preferably the status indications are generated synchronized to the first reference clock. Thus, the status indications can be caught without additional synchronisation problems.
Further preferably said read status indications can comprise one bit in said input, intermediate and output storage stages.
Further preferably said read status indications comprise n bits in said input, intermediate and output storage stages.
Further preferably, for single bit and n bit accumulation, the output register can comprise an output multiplexer and a connected output D flip flop or an n-bit register.
Furthermore, for single bit and n bit accumulation, the control pulse generator can comprise a control means receiving said read request signal and outputting said read lock signal and said readout signal.
Further preferably, for single bit and n bit accumulation, said intermediate register comprises an intermediate multiplexer and an intermediate D flip flop or an n-bit register.
Further preferably, for single bit and n bit accumulation, the synchronization stage comprises at least two serially connected D-flip flops.
Furthermore, for single bit accumulation, the input register can comprise two serially connected multiplexers and an input D flip flop.
Furthermore, for n bit accumulation, the input register can comprise an n-bit register capable of storing n bits simultaneously.
Furthermore, for single bit accumulation, the input update control means can comprise a D flip flop, two AND gates and an XNOR gate.
Furthermore, for n-bit accumulation, the input update control means can comprise a D flip flop, one AND gate and a four input/single output multiplexer.
The hold signal has a primary function to be long enough to cover the occurrence of at least one second clock reference pulse to prevent metastability in the output register and the hold signal is synchronized to the first reference clock to avoid metastability in the intermediate register. Preferably, all operations in the input storage stage and in the intermediate storage stage are carried out synchronized to said first reference clock and all operations in said output storage stage are carried out synchronized to the second reference clock.
The status indications may for example be generated by the surveillance of a plurality, e.g. 16, SDH/SONET data bit streams.
A further embodiment covers the realization of the input, intermediate and output stage by VSLI structures.
Furthermore, it should be noted that the invention also covers various modifications and variations, for example combinations of features and/or steps which have been described separately in the description and/or the claims.
Hereinafter, the invention will be described with reference to its embodiments and as illustrated in the attached drawings.
In the drawings the same or similar reference numerals denote the same or similar steps throughout. In the drawings:
a shows the relationships of signals shown in
b shows the case where the first and second reference clocks CLK_A, CLK_B have the same frequency fA=fB;
c shows the relationship of signals shown in
It may in particular be noted that in
Single Bit or N Bit Status Indication
Hereinafter, the principle of the invention will be described with reference to
As shown in
As one of the differences to the apparatus in
Therefore, also in
As shown in
As shown in
For example, IN_STATUS may be synchronized to the first reference clock CLK_A but may be longer than this first reference clock CLK_A period. In this case a negative edge detection could be performed (for example similarly as with the gates I10, I11, I12 in
As a further example, the status indication IN_STATUS may be asynchronous to the first reference clock CLK_A. In this case, a conventional synchronisation stage (comprising at least two serially connected flip-flops like I09, I10 in
The status indications IN_STATUS are latched in the input storage means INS, are then transferred to the intermediate storage stage ISS and are then transferred to the output storage stage OSS when a read request signal RDRQ is input into the output storage stage OSS. For example, a processing device interested in the status indications may output such a read request signal RDRQ to the output storage stage OSS at any arbitrary timing although as explained above also an inputting only synchronized to the second reference clock CLK_B is possible.
As shown in
Thus, it can be said that for the status indication detection apparatus SIDM shown in
STROBE Readout Signal Generation
Since the time relationships and functions of the signals CLEAR_PULSE LOCK and STROBE is relevant for the understanding of the invention, hereinafter, with reference to
As shown in
As indicated with the arrow RQ in
In response to receiving the read request signal RDRQ with the above-described configuration, a control pulse generator CG of the output storage stage OSS generates the read lock pulse RDLCK and the readout signal STROBE respectively applied to the input storage stage ISS and an output register ORM of the output storage stage OSS, as indicated with steps S1, S2 in
As seen in
RDLCKL, RDLKCL′, RDLCKL″≧Tclk—A+Tsetup_hold (1)
because this allows the capturing of the read clock pulse for arbitrary phase relationships between the clock domains. Thus, the read lock signal RDLCK (read lock) is derived from the read request pulse RDRQ synchronously to the second reference clock CLB_B. Basically, it is the pulse RDRQ widened synchronously to the second reference clock CLK_B.
The readout signal STROBE has preferably a pulse length equal to one period of the second reference clock CLK_B; in particular the readout signal STROBE with the single pulse period length is synchronized to the end of the read lock pulse RDLCK. Due to the different frequency relationships
As indicated in
Since neither the exact temporal occurrence of the read request pulse RDRQ nor the exact temporal occurrence of a new status indication IN_STATUS can be known beforehand and since furthermore the first and second reference clock CLK_A and the second reference clock CLK_B have arbitrary frequency and/or phase relationships, no definite and fixed relationship between the occurrence of RDRQ, RDLCK and STROBE with respect to IN_STATUS can be established. All that can be said is that in response to the read request signal RDRQ a number of second clock reference CLK_B periods (in
With respect to the expression “later”, this means that the readout pulse STROBE must be generated during but at the end of the read lock pulse RDLCK. As explained above, the read lock pulse RDLCK must be so long that it can be safely synchronized in the clock domain A and that it can cause a holding (via the hold signal LOCK) of the data in the intermediate storage stage ISS until the data has been shifted to the output register ORM. That is, if one was to place the readout signal STROBE completely arbitrarily within the duration of the read lock pulse RDLCK, then a situation could occur where it is for example placed at the beginning of the read lock signal RDLCK, i.e. at a point of time in which the read lock pulse RDLCK has not as yet been synchronized in the clock domain A and thus the hold signal LOCK has not been generated as yet. However, if the hold signal LOCK is not generated, the freely changing data in the intermediate register could cause a metastability in the output register which is in particular serious when for the frequency relationship fA>>fB. Therefore, the readout pulse STROBE should preferably be generated for one second clock period at the end of the readout pulse STROBE.
Furthermore, although
Locking the Content of the Intermediate Resister INT
As can be understood from
However, other mechanisms for generating the hold signal LOCK could be used. Important is that the hold signal LOCK has a duration LOCKL; LOCKL′; LOCKL″ (shown in
The timing of generation the hold signal LOCK and the duration of the hold signal LOCK can be easily understood by looking at the time relationships of the read lock pulse RDLCK, the hold signal LOCK itself and the readout signal pulse STROBE. It is best to first look at the generation of RDLCK. RDLCK is mainly responsible for generating the hold signal LOCK, used for freezing the status indication transferred to the intermediate register INT. The duration of the read lock signal RDLCK mainly determines the duration of the hold signal LOCK. Essentially, the hold signal LOCK must be long enough that the data from the intermediate register INT can be moved to the output register ORM with the read pulse STROBE. Furthermore, the read lock signal must be long enough to allow a clocking or sampling of it into the clock domain A since otherwise the hold signal LOCK cannot be generated at all. More specifically, the duration of the read lock pulse RDLCK is the sum of the time for the safe synchronization of RDLCK into the first clock domain A plus the transfer time for data from the intermediate register INT to the output register ORM. Thus, the duration of the hold signal LOCK solely depends from the length of the read lock signal RDLCK and is not automatically 2 clock periods of the first reference clock CLK_A long (although in
It can be seen from
As with the readout signal STROBE, also no clear temporal relationship between the occurrence and the shifting of a status indication ST1, ST2 and the actual occurrence of the hold signal LOCK can be made, at least for the reason that LOCK is for example based on RDLCK and thus on the occurrence of the RDRQ pulse.
However, what is important is that after the occurrence of the read request pulse RDRQ a hold signal LOCK, which has a length covering at least one clock pulse of the second reference clock, is generated, preferably synchronized to the first reference clock CLK_A and, since it is at least of the duration of the read lock pulse RDLCK transferred to the first clock domain A, with a duration which allows the capturing of RDLCK in the clock domain A plus the necessary setup-hold time in accordance with the above equation (1). Furthermore, it is important that during the duration of the hold signal LOCK the current status indication in the intermediate register INT is kept (for example by a clock cycling procedure as will be explained with the specific embodiment in
Temporal Relationship of STROBE and LOCK Pulse
Whilst no exact definition of temporal relationships between the reading in of new status indications (in steps ST1, ST2) into the input register INM and the occurrence of the read request pulse RDRQ, the readout pulse STROBE and the hold pulse LOCK can be made, i.e. a hold signal LOCK covering at least one period of the second reference clock occurs some time after a read request pulse RDRQ, an important quasi-temporal relationship exists between the strobe pulse STROBE and the hold pulse LOCK.
That is, in response to the receipt of the read request signal RDRQ a readout pulse STROBE having a duration of one second clock pulse CLK_B period is placed at the end of the read request signal RDRQ synchronized to the second reference clock CLK_B (to avoid that the readout pulse STROBE is generated before the read lock pulse RDLCK being based on the read request signal RDRQ has been synchronized in the clock domain A). On the other hand, the read lock signal RDLCK has a duration necessary for the synchronization in the clock domain A plus a duration necessary for the setup-hold (in accordance with equation (1)) and at least of a duration allowing a shifting of data from the intermediate register to the output register. Finally, the hold signal LOCK has a duration at least of the same duration as the read lock signal RDLCK, i.e. long enough to allow the transfer of the data from the intermediate register to the output register.
That is, as seen in all
On the other hand, after the end of the hold signal LOCK (as shown with the arrow LE, LE′ and LE″ in
Next, the interaction of the control exercised by the hold signal LOCK on the intermediate register INT and the control executed by an input storage control means DM with the clear pulse CLEAR_PULSE on the input register INM is explained.
As can be seen from
Thus, one can say that the clear pulse CLEAR_PULSE for allowing the take-in of a new status indication is only generated after the expiration of the hold signal LOCK and when the stored contents of the input register INM and the intermediate register INT coincide. This is the purpose of steps S4, S5 carried out by the input storage control means DM and explained hereinafter with more detail regarding the special embodiment in
As explained above, the duration or pulse length LOCKL, LOCKL′, LOCKL″ of the hold signal LOCK (in
As explained above, the hold signal LOCK has a duration long enough to allow a transfer of data from the intermediate register INT to the output register ORM when the readout pulse STROBE is generated. Since the length of the hold signal LOCK is also based on the length of the read lock pulse RDLCK which itself must have a duration allowing its synchronisation in the clock domain A (plus the setup-hold time in the synchronisation stage SS), a typical length for the hold signal LOCK (also covering at least one pulse of the second reference clock at which the read out strobe STROBE is generated) is a multiple, e.g. twice or three times the first reference clock CLK_A period. For the frequency relationships in
Thus, the hold signal LOCK causing the holding of a current status indication in the intermediate storage stage and blocking a shifting of a new status indication from the input storage stage acts as a kind of “masking time” long enough for compensating any frequency and/or phase relationships of the two reference clocks CLK_A, CLK_B, as can easily be seen from
Thus, the following essential steps can be summarized as follows:
This procedure works independently of any frequency relationships fA>fB, fA<fB; fA=fB of the first and second reference clock frequencies fA, fB. That is, in response to the read request signal RDRQ output by the processing means PROC, for example from a microcontroller (MC), eventually the hold signal LOCK is generated. The feature of the invention that the MC always receives the “most recent” status indication is a consequence that after the read access from the output register to the intermediate register the clear pulse CLEAR_PULSE is generated allowing an updating of the input register INM, i.e. of the STATEG.
Therefore, in the present invention the provision of an input register INM, an intermediate register INT (both belonging to the clock domain A) and an output register ORM (belonging to the clock domain B) and their special control with the readout signal STROBE and hold signal LOCK is a relationship responsible for allowing that independently of the phase and frequency relationships no new input status will be lost and the most recent status indication is transferred via the domain boarders.
Furthermore, by the above combination of features the metastability in the output register ORM can be avoided by functional means, i.e. by the appropriate generation of the readout pulse STROBE.
Delayed Shifting from Input to Intermediate Resister
As shown in
Examples in
Above it was explained how the relationship between the signals STROBE, LOCK and CLEAR_PULSE is in response to a single occurrence of the read request pulse RDRQ. However, as can be seen from
As can be seen from
If, however, the status indication is asserted during the n-th read access, it will be visible in the output register ORM (OUTPUT_REG) after the (n+1)-th read access. Therefore, a maximum of n+2 read access cycles (synchronized to the second reference clock CLK_B) are sufficient in order to shift the new status indication from the input register IRM into the output register ORM. That is, two read accesses are necessary because there may be a case where RDRQ and IN_STATUS have such an inappropriate time relationship that the signal CLEAR_PULSE (essentially derived from the read request signal RDRQ) must be suppressed to avoid loosing a status indication. In such a case an indication which occurs in the n-th read cycle will only be visible for the microcontroller MC (the processing means PROC) in the (n+1)th read cycle.
However, the procedure is completely independent of the phase and/or frequency relationships, i.e. the procedure works in the same manner for
Hereinafter, a special embodiment of circuit elements used for the output register ORM, the synchronization stage SS, the intermediate register INT, the input storage control means DM and the input register INM is explained with reference to
Logic Gate Implementation for Qualitative Status Indication
More specifically, the output storage stage OSS comprises for said output register ORM an output multiplexer 106 and an output D flip flop 107; OUTPUT_REG. For a positive logic the output terminal Q is fed to the “0” input of the multiplexer 106 and the clock input of the D flip flop 107 receives the second reference clock CLK_B input from the outside. The “1” input of the multiplexer 106 is connected to the intermediate storage stage ISS.
The control pulse generator CG generally comprises a control means CNTRL receiving the externally input read request signal RDRQ and outputting said read lock pulse RDLCK and said readout signal STROBE. When the read out signal STROBE is high then the multiplexer IO6 selects the “1” terminal and when it is low it selects the “0” terminal of the multiplexer IO6 (for a positive logic). Furthermore, the second reference clock CLK_B is also input to the control means CNTRL.
As can be seen from the feedback of the Q-output to the “0” terminal of the multiplexer 106, in a previous second clock reference cycle a status indication IN_STATUS′ has been stored in said D flip flop IO7 (for this purpose the read out signal is high to select the “1” terminal), and when the readout signal STROBE is subsequently switched to low, then any status indication IN_STATUS′ read into the D flip flop is kept cycling, synchronized to the second reference clock CLK_B through the feedback and the multiplexer IO6. Thus, one can say that in a time period in which the read-out signal STROB is low (“0”) the “0” terminal will be selected and any status indication is kept cycling in the D flip flop 107 whilst, due to the selection of the “0” terminal, the transfer of any further current status indication IN_STATUS′ from the intermediate storage stage ISS is blocked. That is, when the read out signal STROBE is generated (is high) a new status indication is input into the output register ORM and when it is not generated (low) a status indication is kept (cycling) in the output register ORM.
As can be seen from
When the hold signal LOCK is not generated (is low) the lower “0” terminal is selected allowing a transfer of a new status indication from the input storage stage INS. Therefore, one can say that in time periods where the hold signal LOCK is generated, any current status indication is kept cycling in the intermediate register INT whilst the transfer of a new status indication from the input storage stage INS is blocked. When the hold signal LOCK is not generated, a new status indication can be read into the D flip flop IO5, BRIDGEREG.
As can be seen from
As already explained with reference to
Depending on the phase and/or frequency difference, the hold signal LOCK which is now synchronized to the first reference clock CLK_A may be slightly shorter than the read lock pulse RDLCK. The hold signal LOCK is applied to the intermediate multiplexer IO4.
As also shown in
The output of the first multiplexer IO1 is connected with the “0” terminal of the second multiplexer IO2 whose “1” terminal is connected permanently with a “1” level. The select signal applied to the second multiplexer IO2 is the status indication IN_STATUS. That is, if (for appositive logic) a “1” status indication is received, the multiplexer IO2 will select its “1” terminal and therefore forwards the “1” level of the “1” terminal to the D input of the D flip flop IO3. Otherwise, i.e. when there is not status indication, the output of the first multiplexer IO1 is supplied to the input D flip flop IO3.
The “1” terminal of the first multiplexer IO1 is connected permanently to an “0” level and the “0” terminal of the first multiplexer IO1 receives the signal from the Q-output of the D flip flop IO3.
Therefore, when the CLEAR-PULSE is generated (is high for a positive logic) then the “0” level of the selected “1” terminal is passed to the “0” terminal of the second multiplexer IO2. When the CLEAR_PULSE is not generated (is low for a positive logic), then the output Q of the D flip flop is passed to the “0” terminal of the second multiplexer IO2.
Therefore, one can say that a new status indication IN_STATUS stored in the D flip flop IO3 is kept (cycling with the first reference clock CLK_A) in the input register INM when the CLEAR_PULSE is not generated and when no new status indication IN_STATUS occurs.
When a new status indication IN_STATUS occurs then this new status indication will be clocked into the D flip flop IO3 by selecting the “1” level input to the “1” terminal of the second multiplexer IO″ and one first reference clock period later this new status indication is kept (cycling) in the input register INM as long as the CLEAR_PULSE is not generated.
On the other hand, the generation of the clear signal CLEAR_PULSE causes an inputting of the “0” level from the “1” terminal of the first multiplexer IO1 to the “0” terminal of the second multiplexer IO2. Therefore, the first multiplexer IO1 serves to reset status indications in the input register INM and the second multiplexer IO2 serves to set a new status indication in the input register INM.
The clear pulse CLEAR_PULSE is generated by the input update control means DM having the following configuration. The input update control means DM comprises a D flip flop I11 locked with the first reference clock CLK_A and receiving at its D-input the output of the D flip flop I10, i.e. the hold signal LOCK. The Q-output of the D-flip-flip I11 is input into a first terminal of the first AND gate I12. An inverted version of the hold signal LOCK is input to second terminal of the first AND-gate I12 and thereby implementing a negative edge detection on the hold signal LOCK. The output of the first AND gate I12 is the CP signal which is also shown in
A first input of an XNOR Gate I13 receives the output of the intermediate D flip flop IO5 and a second terminal of the XNOR Gate I13 receives the output of the input D flip flop IO3. An inverted version of the output of the XNOR gate I13 is supplied to a first terminal of a second AND gate I14 and the CP signal is input to a second terminal of this AND gate I14. The output of the second AND gate I14 and the CP signal is input to a second terminal of this AND gate I14. The output of the second AND gate I14 is the clear pulse CLEAR_PULSE which is input to the first multiplexer I01 of the input register INM.
Due to the circuit interconnection of the D flip flop I11 and the first AND gate I12 a pulse CP will be generated as shown in step S4 in
As also shown in particular in
With the generation of the CLEAR_PULSE the new status indication in the D flip flop IO3, STATREG is shifted to the intermediate register INT; BRIDGEREG, as shown with step ST5 in
Since the generation of the final CLEAR_PULSE implicitly depends on the inputting of a signal from the Q-output of the intermediate n-bit register IO5; BRIDGEREG, one can say that a transfer of any new status indication in the input n-bit register IO3, STATREG to the intermediate storage stage ISS will only take place when a current status indication has been read out from the intermediate storage stage ISS, more particularly from the intermediate n-bit register IO5. This is necessary in order to avoid that a new inputting of new status indication from the input storage stage INS causes an alteration of the content of the intermediate storage stage before the intermediate storage stage content has been successfully read out to the output storage stage.
Having described above the principal functions and interconnections of the gates and flip-flops and multiplexers in
Operation of the Clock Domain A
During a “regular” operation, i.e. when the clear pulse CLEAR_PULSE and the hold signal LOCK both are not generated (are “0”), the input flip-flop IO3 and the intermediate flip-flop IO5 work like a shift register. That is, the input flip-flop IO3 is set to “1” via the second input multiplexer IO2 as soon as the new status indication IN_STATUS occurs and the intermediate flip-flop IO5 samples the input flip-flop IO3 via the intermediate multiplexer IO4. Thus, the intermediate flip-flop IO5 holds the same content as the input flip-flop IO3 with one first reference clock CLK_A cycle delay.
Once the input flip-flop IO3 is set, it holds its content by feeding back its Q output to its D input via a first and second multiplexer IO1 and IO2. In this manner, a one-pulse status indication on IN_STATUS gets captured in the input register INM and is kept there cycling (unless a new indication IN_STATUS or a CLEAR_PULSE signal occurs).
As explained above in great detail for the configuration in
During this “safe” operation, the input n-bit register is not affected by the locking or holding of the intermediate register INT content. The input stage INS can therefore still capture new status indications (which are kept cycling in the input register INM) until the hold signal LOCK ceases.
In the clock domain A the n-bit register I11 and the first AND gate I12 are needed to perform a negative edge detection on the hold signal LOCK for generating the raw clear pulse CP (for positive logic). A change from high to low on the hold signal LOCK indicates (for positive logic) the end of a read access and the potential start of an update phase for the input n-bit register IO3. The clear pulse CLEAR_PULSE is derived from the raw clear pulse CP using the XNOR gate I13 and the second AND gate I14, substantially in order to suppress the clear pulse CLEAR_PULSE in situations in which an update of the input n-bit register 103 would alter the input n-bit register IO3 although the intermediate n-bit register has not sampled the old content of the input n-bit register IO3 yet.
Operation in the Clock Domain B
As explained above, the clock domain B is the domain to which any new status indication IN-STATUS captured in the input storage stage INS has to be transferred to securely for further processing. The final destination of a status indication captured in the input storage INS is therefore the output register ORM. The n-bit register IO7 of the output register ORM samples the intermediate n-bit register IO5 when the read out signal STROBE is generated. Otherwise the status indication in the output n-bit register IO7 is fed back to the output multiplexer IO6 and therefore does not change.
The control means CNTRL is, as explained above, responsible for properly generating the read lock pulse RDLCK and the read out signal STROBE. As explained above and as can be seen from
As also explained above, the read out signal STROBE is a signal which occurs always within the duration of the hold signal LOCK and in particular it is located in the last cycle duration of the read lock pulse RDLCK.
It should be mentioned that for the purpose of the embodiment in
Input Storage Stage Including a Counter
Since the time relationship between the occurrence of a status indication IN_STATUS and the occurrence of a read request signal RDRQ is generally not defined, the following may happen.
Assume that a first raw status indication IN_STATUS (i.e. first status bit) has been input and stored in the input n-bit register IO3. As long as no new status indication is input to the input storage stage INS, the presently available status indication is kept (cycling) in the input register INM. As explained above, when the read request signal RDRQ occurs, a safe transfer of this status indication to the intermediate storage stage and then a safe reading out of the intermediate storage stage during the duration of the hold signal LOCK to the output register ORM is performed.
However, this assumes that no new raw status indication is input into the input storage stage INS before the read request signal RDRQ occurs. If on the other hand the read request signal RDRQ does not occur for a long period of time, it may happen that there is another new raw status indication IN_STATUS which is then clocked into the intermediate n-bit register IO3. This would mean that in response to the read request signal RDRQ only the latest, i.e. most recent new status indication, would be transferred to the intermediate stage IS and then to the output stage OSS.
Logic Gate Implementation for Counting Status Indications
As can be seen by a comparison of
The input storage stage INS also comprises an input register INM and an input update control device DM performing similar functions as in
The input update control device comprises a n-bit register I11 and an AND gate I12 which have a similar circuit connection as the corresponding n-bit register I11 and the AND gate I12 in
The input input storage INS further comprises a four input/single output multiplexer I15 whose output is connected to the D input of the n-bit register I17 of the input register INM. A first input of the multiplexer I15 is connected directly to the output of the n-bit register I17. A second input is connected to the output of an adder (incrementer) I18 which adds a “1” to the current content of register STATCNT. A third input receives a logical “0” and a fourth input receives an integer “1”. For switching one of the four inputs to the output of the multiplexer, the multiplexer receives as switching signals the status indication pulse IN_STATUS and the output CLEAR_PULSE of the AND gate I12. As indicated in the I15 block, the first input is selected with “00”, the second input is selected with “10”, the third input is selected with “01” and the fourth input is selected with “11”.
The selection is done bit-wise. This means that whenever a new raw status indication bit arrives, this bit together with the corresponding logical output level of the AND gate I12 will provide the respective switching signals to the multiplexer I15. As can be understood from the circuit connections in
The hold signal LOCK output by the n-bit register I11 is, similar as in
Although the embodiment in
A more detailed description of the signal flow in
Assume that in
The embodiment in
To understand the functional behaviour of the circuit in
In
Similarly as in
The input register counter STATCNT stores the number of accumulated indication pulses. In a circuit implementation the STATCNT is the register of a counter constituted with the adder I16 via the multiplexer I15.
The hold signal LOCK is the synchronized version of RDLCK. It serves for holding or allowing the taking in of status indications from the input storage stage INS. Thus, as in
The output register OUTPUT_REG stores a copy of the contents of the input register counter STATCNT synchronized to the clock domain B. Although a read access is superimposed by an indication pulse sequence, OUTPUT_REG will correctly indicate 8+6=14 received indication pulses. The other signals and circuits are the same as in
For illustrating the functional behaviour and the dependencies in
In the first case, e.g. for 19≦clkcnt_a≦27, there is no action. STATCNT, BRIDGEGREG and OUTPUT_REG do not change their value. They perform a storage operation. All other remaining internal signals are logically 0.
In the second case there is a read access, however, no new status indication pulse occurs. This occurs in the clock cycles 26≦CLKCNT_A≦31.
The read request pulse RDRQ causes the control pulse generator CG to generate a pulse RDLCK which has at least a length of one CLK_A period plus the setup-hold-window-width of the Flip-Flop I09 (events A, B). Preferably, the RDLCK is implemented such that it is two CLK_A periods long. Through the Flip-Flop I09 and I10 RDLCK is synchronized to the clock CLK_A. The synchronization stage SS (I09/I10) can in the general case be longer than two Flip-Flops. Two Flip-Flops are the minimum. With respect to the STROBE signal (event C), this signal has already been explained above in great detail with reference to
The third case is shown for the clock cycles 4≦CLKCNT_a≦9. With each occurrence of a new indication pulse, the input “10” is selected and the contents of STATCNT is through the intermediary of the adder (incrementer) I16 incremented. The CLEAR_PULSE is in the third case always 0, because it is not set due to the absence of read pulses RDLCK. In the third case, the BRIDGEREG takes in, with each cycle of the first clock CLK_A, the value from STATCNT, because the hold signal LOCK is not set.
For the sequence of signals from RDRQ until CLEAR-PULSE all the considerations for the second case apply. The only difference to the second (and third) case is that the input “11”=1 is selected at the multiplexer I15 and that STATCNT is therefore set to 1 in the clock cycle 13. Logically, this corresponds to a reset to 0 with an immediate incrementing procedure.
Summarizing, the embodiment in
Thus, also the number of status indications can be determined (accumulated) and can be safely transferred to the output storage stage OSS without losing any status indication.
As explained above, in accordance with the present invention an intermediate storage stage ISS is provided between the input stage INS and the output stage OSS. Status indications are shifted into the intermediate storage stage ISS and during the generation of a hold signal holding the content of the intermediate storage stage ISS and blocking a transfer of a new status indication from the input storage stage INS, the content of the intermediate storage stage ISS is transferred to the output storage stage OSS without causing metastability in the output register ORM.
The design is operable for any frequency and/or phase relationship between the first reference clock and the second reference clock and still no new status indication will be lost. Furthermore, it is always guaranteed that the content of the output register is the most recent status indication and is properly transmitted over the clock domain border.
Such a status indication detection apparatus and status indication detection method are particularly useful for monitoring SONET/SDH applications as hardware devices. Furthermore, the input, intermediate and output stage may be realized by VLSI structures in ASICS.
Furthermore, it should be noted that the invention can comprise various other modifications and variations within the scope of the invention as described. In particular, the invention may comprise further embodiments consisting of features and/or steps which have been separately described and/or claimed in the description and/or in the following claims.
In the claims, reference numerals only serve clarification purposes.
| Number | Date | Country | Kind |
|---|---|---|---|
| 01115751 | Jul 2001 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP02/07376 | 7/3/2002 | WO | 00 | 7/9/2004 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO03/007096 | 1/23/2003 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4851710 | Grivna | Jul 1989 | A |
| 5357613 | Cantrell et al. | Oct 1994 | A |
| 5602878 | Cross | Feb 1997 | A |
| 5638015 | Gujral et al. | Jun 1997 | A |
| 5726595 | Lin et al. | Mar 1998 | A |
| 5799175 | Cassiday et al. | Aug 1998 | A |
| 6493818 | Robertson | Dec 2002 | B2 |
| 7058799 | Johnson | Jun 2006 | B2 |
| Number | Date | Country | |
|---|---|---|---|
| 20040250151 A1 | Dec 2004 | US |
