Step-up / step-down circuit

Abstract

A step-up/step-down circuit can be simplified as compared with conventional circuits by including a step-down unit for receiving a system clock pulse alternately providing a reference voltage (GND) and a system voltage VDD in a repeated manner to output a voltage V4 lower than the reference voltage (GND) by using a potential difference between the reference voltage (GND) and the system voltage VDD, a level shift unit for receiving the system clock pulse and the voltage V4 output from the step-down unit to output a pulse signal Vo having a greater potential difference than the potential difference between the reference voltage (GND) and the system voltage VDD, and a step-up unit for receiving the pulse signal Vo output from the level shift unit to output a voltage V7 higher than the reference voltage (GND).

Description

CROSS-REFERENCE TO RELATED APPLICATION

The entire disclosure of Japanese Patent Application No. 2004-190654 including the specification, claims, drawings, and abstract is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a step-up/step-down circuit with a simplified circuit configuration.

2. Description of the Related Art

Photoelectric conversion devices including photoelectric conversion elements have come to be widely used in recent years. Because devices are often incorporated into portable terminal devices, such as mobile phones, reduction in size of not just the photoelectric conversion devices, but also of peripheral power supply circuits, is desired.

For vertical and horizontal transfer and output of information electric charges produced in accordance with incident light, photoelectric conversion devices having a CCD solid-state image sensing element require a predetermined transfer clock pulse to be applied to vertical and horizontal transfer registers, a gate electrode, and a transfer electrode in an output unit. A crest value of such a pulse, i.e. a pulse voltage, is set at a predetermined voltage level by stepping up or down the voltage of a system clock of the photoelectric conversion device.

The photoelectric conversion device having the CCD solid-state image sensing element generally uses a system clock pulse of 0-3 V. The transfer clock pulse is produced by boosting or bucking the voltage of the system clock pulse. A step-down circuit includes a charge pump circuit as shown in FIG. 5. A main circuit unit 10 is formed as a semiconductor element. Often, capacitors Ca-Cd included in the step-down circuit are connected to external terminals Ta-Td outside the main circuit unit 10. In such a step-down circuit, a reference voltage terminal is connected to ground, and the system clock pulse of 0-3 V is applied to an input terminal, thereby obtaining potentials Va-Vd at connection nodes A-D, respectively, as shown in FIG. 6. More specifically, the voltage is reduced from the reference ground potential (GND) through the two-stage charge pump action, and the potential Vc of approximately −6 V is applied to a regulator 12, so that the regulator 12 can produce the output voltage Vd of approximately −4 V. On the other hand, a step-up circuit also includes a charge pump circuit as shown in FIG. 7 similarly to the step-down circuit. A main circuit unit 14 is formed as a semiconductor element. Capacitors Ce-Ch included in the step-up circuit are often connected to external terminals Te-Th outside the main circuit unit 14. In this step-up circuit, a system voltage V_DD of 3 V is supplied to a reference voltage terminal, and the system clock pulse of 0-3 V is applied to an input terminal, thereby obtaining potentials Ve-Vh at connection nodes E-H, respectively, as shown in FIG. 8. More specifically, the voltage is boosted from the reference system voltage V_DD through the two-stage charge pump action, and the potential Vg of approximately 9 V is supplied to a regulator 16, which converts the potential Vg into the output voltage Vh of approximately 7 V, and outputs the converted voltage.

Conventional step-down and step-up circuits such as those described above are generally formed as completely independent circuits for producing the desired output voltages Vd and Vh from the system clock pulse, a large number of components are required for the step-up/step-down circuits, thereby increasing the scale and size of the circuit. In addition, because a large number of external terminal pins for connecting to the capacitors Ca-Ch are required, the area occupied by pad electrodes for extracting the external terminals in the step-up/step-down circuit is increased, preventing further reduction in size of the photoelectric conversion circuit.

SUMMARY OF THE INVENTION

The present invention provides a step-up/step-down circuit comprising a step-down unit for receiving a system clock pulse alternately providing a reference voltage and a first voltage different from the reference voltage in a repeated manner, and supplying a second voltage lower than the reference voltage by using a potential difference between the reference voltage and the first voltage, a level shift unit for receiving the system clock pulse and the second voltage supplied from the step-down unit, and supplying a pulse having a potential difference greater than the potential difference between the reference voltage and the first voltage, and a step-up unit for receiving the pulse supplied from the level shift unit, and supplying a third voltage higher than the reference voltage.

The present invention also provides a step-up/step-down circuit comprising a step-up unit for receiving a system clock pulse alternately providing a reference voltage and a first voltage different from the reference voltage in a repeated manner, and supplying a second voltage higher than the reference voltage by using a potential difference between the reference voltage and the first voltage, a level shift unit for receiving the system clock pulse and the second voltage supplied from the step-up unit, and supplying a pulse having a potential difference greater than the potential difference between the reference voltage and the first voltage, and a step-down unit for receiving the pulse supplied from the level shift unit, and supplying a third voltage lower than the reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will be described in further detail based on the following drawings, wherein:

FIG. 1 shows a configuration of a step-up/step-down circuit according to an embodiment of the present invention.

FIGS. 2A-2D show voltages of various sections in the step-up/step-down circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a level shift unit according to the embodiment of the present invention.

FIG. 4 shows another configuration example of the step-up/step-down circuit according to the embodiment of the present invention.

FIG. 5 shows a step-down circuit in a background art.

FIG. 6 shows voltages of various sections in the step-down circuit in the background art.

FIG. 7 shows a step-up circuit in the background art.

FIG. 8 shows voltages of various sections in the step-up circuit in the background art.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A step-up/step-down circuit according to an embodiment of the present invention includes a timing generator (TG) 20, a step-down unit 22, a level shift unit 24, and a step-up unit 26, as shown in FIG. 1.

The timing generator 20 is a circuit receiving a system voltage V_DD of a photoelectric conversion device or the like as an input voltage, and generating a system clock pulse f_s. When, for example, the system voltage V_DD is 3 V, the system clock pulse f_s repeatedly alternating between a ground voltage (GND), which is a reference voltage, and the system voltage V_DD in a predetermined cycle is produced. The timing generator 20 is configured similarly to commonly-used clock generation circuits, and therefore will not be described here in this specification. An output terminal of the timing generator 20 is connected to the step-down unit 22 and an input terminal T_IN1 of the level shift unit 24. As a result, the system clock pulse f_s is supplied to input terminals of the step-down unit 22 and the level shift unit 24.

The step-down unit 22 is configured similarly to the conventional step-down circuit, and includes a main unit 30 formed on a semiconductor substrate, and capacitors C₁-C₄ connected to the main unit. The main unit 30 and the capacitors C₁-C₄ form a charge pump circuit.

The configuration of the main unit 30 according to the present embodiment will be specifically described. A reference voltage terminal receiving the reference voltage, which is a reference for voltage step-down, is connected to an external terminal T₁ through a source and a drain of a switching element Tr₁. A connection node between the external terminal T₁ and the switching element Tr₁ is connected through a source and a drain of a switching element Tr₂ to an external terminal T₂. A connection node between the external terminal T₂ and the switching element Tr₂ is connected through a source and a drain of a switching element Tr₃ to an external terminal T₃. A connection node between the external terminal T₃ and the switching element Tr₃ is connected to an input terminal of a regulator 32, whose output terminal, i.e. an output terminal of the step-down unit 22, is connected to an external terminal T₄. On the other hand, the input terminal of the step-down unit 22 is connected to input terminals of a buffer element 34 and of an inverting element 36. An output terminal of the buffer element 34 is connected to an external terminal T_x1, and an output end of the inverting element 36 is connected to an external terminal T_x2.

The capacitors C₁-C₄ are connected to the external terminals T₁-T₄ and T_x1 and T_x2 outside the main unit 30. The capacitor C₁ is connected between the external terminals T₁ and T_x1. The capacitor C₂ is connected between the external terminals T₂ and T_x2. The capacitor C₃ has one end connected to the external terminal T₃, and the other end connected to ground. The capacitor C₄ has one end connected to the external terminal T₄, and the other end connected to ground. The reference voltage terminal is connected to ground, and the input terminal is connected to the output terminal of the timing generator 20. The capacitances of the capacitors C₁-C₄ are preferably determined based on a load capacitor connected to the external terminal T₄, the required response time, and the like.

The system clock pulse f_s of 0-3 V is supplied from the timing generator 20 to the input terminal of the step-down unit 22 to switch the switching elements Tr₁-Tr₃, thereby stepping down the voltage of the system clock pulse f_s, as illustrated in the graph of FIG. 2B. For example, a pulsed potential V₁ for alternately supplying the ground potential (GND) and approximately −3 V is achieved at the external terminal T₁. A pulsed potential V₂ for alternately supplying, for example, approximately −3 V and approximately −6 V is achieved at the external terminal T₂. At the external terminal T₃, a fixed potential V₃ of, for example, approximately −6 V is obtained, and this potential V₃ is supplied to the regulator 32. Consequently, as an output of the regulator 32, a voltage V₄ of, for example, approximately −4 V is supplied to the external terminal T₄.

The level shift unit 24 includes a level shift circuit formed on a semiconductor substrate. While the level shift circuit can be formed, for example, as a circuit illustrated in FIG. 3, its configuration is not limited to that described above.

The input terminal T_IN1 is connected to a gate of a transistor Tr_a of a first conductivity type, and to an input terminal of an inverting element 38, whose output terminal is connected to a gate of a transistor Tr_b of the first conductivity type. Sources of the transistors Tr_a and Tr_b receive the system voltage V_DD. Drains of the transistors Tr_a and Tr_b are connected to drains of transistors Tr_c and Tr_d of a second conductivity type, and to gates of the transistors Tr_d and Tr_c, respectively. The input terminal T_IN2 is connected to sources of the transistors Tr_c and Tr_d. An output terminal T_o is drawn from the drain of the transistor Tr_d.

In such a level shift circuit, the system clock pulse f_s is supplied from the timing generator 20 to the input terminal T_IN1, and the output voltage V₄ is supplied from the step-down unit 22 to the input terminal T_IN2. Consequently, as illustrated in the graph of FIG. 2C, a pulse signal V_o having a larger potential difference than that of the system clock pulse f_s, i.e. a pulse signal alternately providing the voltage V₄ supplied to the input terminal T_IN2 and the system voltage V_DD, is output from the output terminal T_o. For example, in the present embodiment, the voltage of approximately −4 V and the voltage of approximately 3V are alternately supplied in a repeated manner.

The step-up unit 26 includes a main unit 40 formed on a semiconductor substrate, and capacitors C₅-C₇ connected to the main unit. The main unit 40 and the capacitors C₅-C₇ form a charge pump circuit. By providing the step-down unit 22 in the preceding stage, and achieving the pulse signal V_o with a greater potential difference between an ON voltage and an OFF voltage than the system clock pulse f₅ through the level shift circuit, the number of stages of the charge pump circuit in the step-up unit 26 is decreased from that of the conventional circuit.

A configuration of the main unit 40 according to the present embodiment will be specifically described. A reference voltage terminal receiving a reference voltage used as a reference for voltage increase is connected to an external terminal T₅ through a source and a drain of a switching element Tr₅. A connection node between the external terminal T₅ and the switching element Tr₅ is connected to an external terminal T₆ through a source and a drain of a switching element Tr₆. A connection node between the external terminal T₆ and the switching element Tr₆ is connected to an input terminal of a regulator 42, whose output terminal, i.e. an output terminal of the step-up unit 26, is connected to an external terminal T₇. An input terminal of the step-up unit 26 is connected to an input terminal of a buffer element 44, whose output terminal is connected to an external terminal T_x5.

The capacitors C₅-C₇ are connected to the external terminals T₅-T₇ and T_x5 outside the main unit 40. The capacitor C₅ is connected between the external terminals T₅ and T_x5. The capacitor C₆ has one end connected to the external terminal T₆, and the other end connected to ground. The capacitor C₇ has one end connected to the external terminal T₇, and the other end connected to ground. The system voltage V_DD is applied to the reference voltage terminal, and the output from the level shift unit 24 is supplied to the input terminal. The capacitances of the capacitors C₅-C₇ are preferably determined based on a load capacitor connected to the external terminal T₇, required response time, and the like.

By switching the switching elements Tr₅-Tr₆, the step-up unit 26 steps up the pulse signal V_o of the level shift unit 24 as illustrated in the graph of FIG. 2D. For example, a voltage V₅ equals the reference system voltage V_DD plus the pulse signal V_o from the level shift unit 24, i.e. alternating voltages of approximately +3 V and +10 V, emerges at the external terminal T₅. Subsequently, a voltage V₆ of, for example, approximately +10 V, obtained by smoothing the voltage V₅ emerges at the external terminal T₆. To the output end terminal of the regulator 42, a voltage of V₇ of approximately +7 V obtained by reducing the voltage V₆ is supplied.

As described above, by using the step-up/step-down circuit of the present embodiment, an output voltage of approximately −4 V and an output voltage of approximately +7 V can be obtained from the step-down unit 22 and the step-up unit 26, respectively.

The timing generator 20 of the step-up/step-down circuit, the main unit 30 of the step-down unit 22, the level shift unit 24, and the main unit 40 of the step-up unit 26 can be formed on the same semiconductor substrate as a single semiconductor element.

In the step-up/step-down circuit of the present embodiment, the number of stages of the charge pump circuit in the step-up unit 26 can be decreased as compared to the conventional circuit by supplying the output of the step-down unit 22 to the level shift unit 24. Such a decrease in number of stages of the charge pump circuit contributes to a decrease in number of capacitors externally connected to the step-up unit 26. That is, the circuit configuration of the step-up/step-down circuit can be simplified. The area occupied by the newly added level shift unit 24 is smaller than the area where the eliminated capacitor is disposed, and the area occupied by the pad electrode for extracting the external terminal to be connected to the capacitor can also be reduced. As a result, the step-up/step-down circuit can be reduced in size as compared with the conventional circuit.

In addition, because the number of externally connected capacitors is reduced, the manufacturing process can also be simplified. Reliability of the step-up/step-down circuit can also be enhanced, and photoelectric conversion devices and the like using such a step-up/step-down circuit can be downsized.

While the step-down unit 22 and the step-up unit 26 are disposed in the preceding and succeeding stages, respectively, in the present embodiment, the configuration is not limited thereto. For example, as illustrated in FIG. 4, a step-up unit 52 may be disposed in a preceding stage, so that an output of the step-up unit 52 is shifted by a level shift unit 54, and that an output from the level shift unit 54 can be stepped down by a step-down unit 56 in a succeeding stage.

Claims

1. A step-up/step-down circuit, comprising: a step-down unit for receiving a system clock pulse alternately providing a reference voltage and a first voltage different from the reference voltage in a repeated manner, and supplying a second voltage lower than the reference voltage by using a potential difference between the reference voltage and the first voltage;a level shift unit for receiving the system clock pulse and the second voltage supplied from the step-down unit, and supplying a pulse having a potential difference greater than the potential difference between the reference voltage and the first voltage; anda step-up unit for receiving the pulse supplied from the level shift unit, and supplying a third voltage higher than the reference voltage.

2. A step-up/step-down circuit, comprising: a step-up unit for receiving a system clock pulse alternately providing a reference voltage and a first voltage different from the reference voltage in a repeated manner, and supplying a second voltage higher than the reference voltage by using a potential difference between the reference voltage and the first voltage;a level shift unit for receiving the system clock pulse and the second voltage supplied from the step-up unit, and supplying a pulse having a potential difference greater than the potential difference between the reference voltage and the first voltage; anda step-down unit for receiving the pulse supplied from the level shift unit, and supplying a third voltage lower than the reference voltage.

3. The step-up/step-down circuit according to claim 1, wherein the step-down unit or the step-up unit includes a charge pump circuit.

4. The step-up/step-down circuit according to claim 2, wherein the step-down unit or the step-up unit includes a charge pump circuit.

5. The step-up/step-down circuit according to claim 3, wherein a part of the charge pump circuit included in the step-down unit or the step-up unit is formed on a semiconductor substrate, and at least one of a plurality of capacitors forming the charge pump circuit is connected to the exterior of the semiconductor substrate.

6. The step-up/step-down circuit according to claim 4, wherein a part of the charge pump circuit included in the step-down unit or the step-up unit is formed on a semiconductor substrate, and at least one of a plurality of capacitors forming the charge pump circuit is connected to the exterior of the semiconductor substrate.