Stepped voltage drive for driving capacitive loads

Abstract

A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than or equal to 2 and wherein the n-stage stacked charging circuit may comprise n−1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n−1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n−1th discharging time period through the respective n−1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Description

FIELD

The present invention relates to voltage drives and particularly to stepped or staged voltage drives providing energy savings in switching applications.

BACKGROUND

Heavy capacitive loads are very common in industrial and commercial systems and equipment. A common example is a piezoelectric element which is used extensively in such applications as ink jet printers, speakers and motor drives. A piezoelectric element, formed by piezoelectric material sandwiched between two electrodes, is typically electrically modeled as a large capacitor, with the piezoelectric material acting as both a dielectric between the electrodes and an actuator under the influence of the electric field resulting from the application of a voltage across the electrodes. Indeed, an entire matrix of piezoelectric actuators for individual droplet making mechanisms in an inkjet printer head may be modeled as a single capacitive load. Throughout this application, unless otherwise expressly stated, discussion of a capacitive load in the form of a piezoelectric actuator will be understood to also include a matrix of such actuators, producing a single capacitive load to which an output voltage is applied, and that this capacitive load also has typically resistive and inductive components to it. The operation of load drive circuits for other loads with high capacitance and with added inductance, such as in an LC tank circuit may be improved with embodiments of the present invention.

The electrical drive to the capacitive load, such as a piezoelectric actuator, may be a controlled high voltage waveform delivered, as an example once per cycle of printer head operation or the like. The shape, period, and frequency of this waveform can be heavily dependent upon the application. Such loads may have, as is the case with most piezoelectric element drive waveforms, fast switching transitions.

Therefore, typically a fast linear high voltage (HV) amplifier is used to deliver the waveform to the piezoelectric element. In such a fast linear high voltage (HV) amplifier, power dissipated while switching a load capacitor between a ground voltage GND to the high voltage VDD (as an example 50 V) is given by:P_DISS=C_L·VDD²·f  (1)where C_L=Load Capacitor capacitance, f=Frequency of drive waveform.

Existing linear capacitive load drives conform to equation 1. This relationship can result in limitations on attributes of the application or engineering system, such as maximum load capacitance and frequency of the waveform. This relationship can further limit the number of actuators that can be driven, such as in the piezoelectric inkjet printer print head application, the number of inkjets and thereby the resolution of the printing by the print head, as well as the speed of printing, i.e., cycles per second of actuation. Achieving higher resolution by being able to drive more inkjets and higher frequency of the drive voltage waveform is generally desirable. In inkjet printer piezoelectric applications, faster operation is always a goal resulting in faster printing speed.

FIG. 1 shows a schematic diagram of a circuit 10 useful in understanding energy dissipation while driving a capacitive load C_LOAD 20. FIG. 1 shows two switches 22, 24 for charging and discharging the capacitor C_LOAD 20. The circuit 10 includes a voltage supply 26, such as a 50 V DC power supply, which when voltage controlled switch 22 is closed, charges the load capacitor 20 through a resistor 28 that is modeling ON resistance of the switch, and a voltage controlled switch 24, which when closed, discharges the load capacitor 20 through a resistor 30 to ground. Each of the switches 22, 24 has a respective switch voltage supply 40, 42 to assist in the control of the timing and operation of the respective switches.

FIG. 1 shows switch 22, that when closed, charges the load capacitor 20 with a charge Q=C_LOAD×V_DD. The energy from the supply 26 to provide this charge is E_SUPPLY=Q×V_DD=C_LOAD·V_DD². The energy stored in the capacitor 20 is E_c=C_LOAD·×V_DD²/2. These results can also be derived by integrating the instantaneous power over the period of interest.

$\begin{array}{c}{E}_{\mathrm{SUPPLY}}={\int }_0^{\infty }{i}_{\mathrm{VDD}}\left(t\right)·V_{\mathrm{DD}}\left(t\right)dt\\ =C_L·V_{\mathrm{DD}}·{\int }_0^{\infty }\frac{d{V}_{\mathrm{OUT}}·dt}{dt}\\ =C_L·V_{\mathrm{DD}}·{\int }_0^{50}d{V}_{\mathrm{OUT}}\\ =C_L\times 50\times 50=2500·C_L\end{array}$ $\begin{array}{c}{E}_C={\int }_0^{\infty }{i}_{\mathrm{dd}}\left(t\right)·v_{\mathrm{out}}\left(t\right)·dt\\ =C_L·{\int }_0^{\infty }\frac{d{v}_{\mathrm{OUT}}\left(t\right)}{dt}·V_{\mathrm{OUT}}\left(t\right)·dt\\ =C_L·{\left[\frac{v_{{\mathrm{OUT}}^2}}{2}\right]}_0^{50}=1250·C_L{E}_{\mathrm{diss}1}=E_{\mathrm{SUPPLY}}-E_C=1250·C_L\end{array}$

This analysis shows that half of the energy supplied by the voltage source is stored in the load capacitor while the other half is dissipated in switch 22 and resistor 28. During the discharge phase, the charge is removed from C_LOAD 20, and the energy is dissipated in switch 24 and resistor 30. Thus the energy dissipated during each switching cycle is given by:E_diss=C_LOAD·V_DD²=2500·C_LOAD(V_DD=50V)  Equ (1)

Adiabatic switching has been done at low voltages in digital circuits as discussed in the following references. Indermaur et al., Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design, IEEE Symposium on Low Power Electronics (1994), relates to charge recovery through adiabatic switching (from rail high or low voltage to the other rail voltage over sequential rails) for power reduction in CMOS integrated circuits. Gabara, Pulsed Power Supply CMOS—PPS CMOS, IEEE Symposium on Low Power Electronics (1994), relates to similar ramped driving and charge recovery, called “pulsed power” in CMOS circuits. Similarly Svensson et al., Driving a Capacitive Load Without Dissipating fCV², IEEE Symposium on Low Power Electronics (1994), describes a similar “stepwise charging” in CMOS circuits.

While existing systems are of great benefit, there is always a need to improve performance of capacitive load drive systems, such as a piezoelectric drive system, including performance in energy savings, improved speed of operation, ability to drive more load elements which would allow for increased resolution of inkjet printing. Accordingly, there is a need in the art for a more effective and efficient drive circuit.

SUMMARY

In one aspect, a voltage drive circuit according to a possible embodiment of the disclosed subject matter may comprise a multi-stage voltage drive circuit.

It will be understood that a capacitive load drive circuit and method of load driving is disclosed which may comprise a stepped voltage drive circuit configured to cyclically charge a capacitive load to a selected high voltage during a ramp up and configured to discharge the capacitive load to a selected low voltage during a ramp down. A voltage supply circuit comprises a circuit configured to sequentially supply to the load a variable voltage varying between each of a plurality of rails. Each rail has a rail high voltage and a rail low voltage with the rail low voltage of the sequentially next rail essentially equal to the rail high voltage of the sequentially preceding rail, during the ramp up. The circuit for the voltage supply circuit is configured to supply to the load a variable voltage varying between each of a plurality of rails, each having a rail high voltage and a rail low voltage, with the rail high voltage of the sequentially next rail essentially equal to the rail low voltage of the sequentially preceding rail during the ramp down.

In an illustrative embodiment, the rails may be equal and some fraction of a high voltage such as V_DD/n where n is the number of separate rails. The rails could be V_DD/n positive rails and V_DD/n negative rails, such as 0V−(+VDD/4), +V_DD/4−(+V_DD/2), +V_DD/2−(+3V_DD/4), 3V_DD/4−V_DD and −V_DD−(−3V_DD/4), −3V_DD/4−(−V_DD/2), −V_DD/2−(−V_DD/4) and −V_DD/4−0V assuming four positive and four negative rails of equal difference between the rail high voltage and the rail low voltage, i.e., V_DD/4.

The drive circuit could also comprise a multi-stage stacked charging circuit configured to be electrically connected to the capacitive load and may comprise a first capacitor configured to be electrically connected to the capacitive load through a first switch during a first charging time period; a voltage supply configured to be electrically connected to the capacitive load through a second switch during a second charging time period with the first capacitor configured to be electrically connected to the capacitive load through the first switch during a first discharging time period. The circuit may also comprise a third switch configured to electrically connect the capacitive load to a selected low voltage during a second discharging time period.

The voltage supply circuit could comprise an n-stage stacked voltage supply circuit which may comprise n−1 capacitors and a voltage source configured to each be sequentially electrically connected to the capacitive load through a respective first through nth switch during a respective first through nth charging time period; the n−1th capacitors configured to each be sequentially electrically connected to the capacitive load in reverse order during a first through n−1th discharging time period through the respective n−1th through first switches. The circuit may also comprise an n+1th switch configured to electrically connect the capacitive load to the selected low voltage during an nth discharging period.

The drive circuit could comprise an amplifier selectively connected across a plurality of n sequential intermediate rails each with a rail high voltage V₁ and a rail low voltage V₂ with respective selected ranges having an increasing value of V₁ during the ramp up and with the respective ranges having a decreasing value of V₁ during the ramp down, each defining an output range of the amplifier. The amplifier could comprise a floating low voltage operational amplifier, and V₁-V₂ could be the same for each respective rail. The rails can extend between a positive circuit high voltage and a negative circuit low voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, functions, and advantages that are disclosed can be achieved independently in various embodiments of the present disclosure or may be combined in yet other embodiments, further details of which can be seen with reference to the following description and drawings, wherein like numerals depict like parts, and wherein:

FIG. 1 shows a conventional voltage drive circuit;

FIG. 2 shows a schematic circuit diagram of a drive circuit according to aspects of an embodiment of the present invention;

FIG. 3 shows schematically an example of a timing of the operation of the circuit of FIG. 2.

FIG. 4 shows a schematic circuit diagram of a drive circuit according to aspects of an embodiment of the present invention;

FIG. 5 shows an example of a simulation of the operation of the circuit of FIG. 4;

FIG. 6 illustrates schematically the principal elements of a printer head with which the present invention may be used;

FIG. 7 shows a graph of normalized energy dissipation for given values of a step voltage; and

FIG. 8 shows schematically and in block diagram form a variable voltage staged capacitive load drive circuit according to aspects of an embodiment of the present invention.

DETAILED DESCRIPTION

A novel drive circuit according to aspects of the present invention can be utilized to reduce a substantial amount of power dissipation in piezoelectric systems or like systems involving driving large capacitive loads. As an example, aspects of the present invention can greatly improve performance of voltage drives, such as piezoelectric drive systems, including performance through energy savings, improved speed of operation, ability to drive more piezoelectric elements which would allow for increased resolution of inkjet printing.

FIG. 2 shows a schematic circuit diagram of a capacitive load drive circuit 10′ having a multi-supply arrangement, in the specific example, a two stage stepped voltage supply. The circuit 10′ contains the elements of the circuit 10 of FIG. 1 for charging C_LOAD 20 to V_DD during the ramp up and discharging during ramp down. In a stepped voltage drive with n steps, such as n=2 as illustrated in FIG. 2, there can be a number (n) of intermediate rails with specific voltage levels between the rails, which may be, but need not necessarily be equal, as in the example where the incremental values are equal to V_DD/n. In addition there can be a number (n) of switches controlling current flow, as an example for either the charging or discharging of the load, as the case may be, during such charging and discharging of the capacitor 20 by (V_DD C_LOAD) amounts.

In addition to the elements of FIG. 1, the circuit 10′ of FIG. 2 contains, by way of example, a current supply, which may comprise a charge storage device, such as capacitor C_BIG 54. The capacitor 54 may be connected to the load capacitor 20 through a resistor 52 when switch 50 is closed. The timing of the closing of switch 50 may be done by a voltage supply 56, which may provide a time varying closure signal, to the V+ and V− terminals of the voltage controlled switch 50.

FIG. 3 illustrates an output voltage waveform 60 for the circuit 10′ of FIG. 3 illustrating a timing of operation of the circuit. The control of the timing of the closing of the switches by the respective switch control signals 40, 42 and 56 can be set up so that during a first charging time period, switch 50 is closed and a portion 62 of the output waveform 60 of the voltage supply circuit 10′ is generated during the first charging time period. In an exemplary embodiment, where the output waveform serves to charge a capacitive load, such as actuation of a piezoelectric element, the portion 62 of the output waveform 60 initiates the actuation of the piezoelectric element 130 shown in FIG. 6. Also in an exemplary embodiment, this can begin to squeeze a channel 124 in an inkjet printer inkjet 122, or a nozzle 122 in such a channel 124, to begin to force out ink from the individual inkjet nozzle 122 in an inkjet printer print head (not shown). During the first charging time period 62, the output waveform can provide an output voltage varying from 0 to V_DD/2, which in the exemplary embodiment is the value of the voltage on C_BIG 54.

Thereafter, with switch 22 closed, the voltage supply V_DD is connected to the load, and in the exemplary embodiment, a capacitive load such as a piezoelectric element in an inkjet printer print head, increases the output voltage applied to the load C_LOAD from V_DD/2 to V_DD during a second charging time period 64. During a subsequent time period 66, the output voltage may be maintained at V_DD. Thereafter, with switch 50 closed, the charge storage element, such as capacitor C_BIG 54 may be charged to V_DD/2 from the charge storage device C_LOAD 20 during a first discharging time period 68, wherein the load goes from V_DD to V_DD/2. In other words, the charge that was initially provided by the V_DD/2 supply during ramp up is dumped back into C_BIG 54.

In the exemplary embodiment, this reduction of voltage to the load 20 can begin to relax the piezoelectric element 130 squeeze on the channel in an inkjet printer ink droplet producing mechanism 120, by relaxing the deformation of the piezoelectric element or transducer 130 under the influence of the electric field created by the voltage across the electrodes of the piezoelectric element 130, to begin to draw ink into the individual inkjet nozzle channel 124 from a reservoir (not shown) in an inkjet printer print head (not shown), through an ink supply line 126. It will be understood that other means may be used, alone or in combination with such relaxation of the piezoelectric element, to resupply the channel 124 of the given nozzle 122, such as a pressure applied to the reservoir (not shown).

Finally, switch 24 may be closed to connect the load 20 to ground, thereby discharging the load capacitor C_LOAD 20 through switch 24 and resistor 30 during a second discharging time period 70, and the output waveform thus provides an output voltage varying from V_DD/2 to 0. In the exemplary embodiment, this reduction of voltage to the load 20 can completely relax the piezoelectric element pressure on the inkjet nozzle in preparation for a subsequent actuation of the piezoelectric element at a later time by the application of another output voltage waveform 60 to the load.

The following analysis of energy dissipation E_diss1 during such charging of the load 20 applies with the switch 50 closed.

$\begin{array}{c}{E}_{\mathrm{CBIG}}={\int }_0^{\infty }{i}_{\mathrm{CBIG}}\left(t\right)·v_{\mathrm{CBIG}}\left(t\right)dt\\ =C_L·\frac{V_{\mathrm{DD}}}{2}·{\int }_0^{\infty }\frac{d{V}_{\mathrm{OUT}}·dt}{dt}\\ =C_L·\frac{V_{\mathrm{DD}}}{2}·{\int }_0^{\frac{V_{\mathrm{DD}}}{2}}d{V}_{\mathrm{OUT}}\\ =C_L\times \frac{V_{\mathrm{DD}}}{2}\times \frac{V_{\mathrm{DD}}}{2}={25}^2·C_L\end{array}$ $\begin{array}{c}{E}_{\mathrm{CLoad}}={\int }_0^{\infty }{i}_{\mathrm{CLoad}}\left(t\right)·v_{\mathrm{out}}\left(t\right)·dt\\ =C_L·{\int }_0^{\infty }\frac{d{v}_{\mathrm{OUT}}\left(t\right)}{dt}·v_{\mathrm{OUT}}\left(t\right)·dt\\ =C_L·{\left[\frac{V_{{\mathrm{OUT}}^2}}{2}\right]}_0^{\frac{V_{\mathrm{DD}}}{2}}=\frac{{25}^2}{2}·C_L{E}_{\mathrm{diss}1}=E_{\mathrm{CBIG}}-E_{\mathrm{CLoad}}=\frac{{25}^2}{2}·C_L\end{array}$

It will be understood that, with the intermediate voltage set to an arbitrary voltage V₁ between V and V_DD, E_diss1 will equal (C_L×V₁²)/2.

Later, with switch 22 closed, during the charging from V₁ to V_DD, i.e., from V_DD/2 to V_DD, where V₁=V_DD/2, the following applies:

$\begin{array}{c}{E}_{\mathrm{SUPPLY}}={\int }_0^{\infty }{i}_{\mathrm{VDD}}\left(t\right)·V_{\mathrm{DD}}\left(t\right)dt\\ =C_L·V_{\mathrm{DD}}·{\int }_0^{\infty }\frac{d{V}_{\mathrm{OUT}}·dt}{dt}\\ =C_L·V_{\mathrm{DD}}·{\int }_{25}^{50}d{V}_{\mathrm{OUT}}\\ =C_L\times 50\times 25\end{array}$ $\begin{array}{c}{E}_C={\int }_0^{\infty }{i}_{\mathrm{dd}}\left(t\right)·v_{\mathrm{out}}\left(t\right)·dt\\ =C_L·{\int }_0^{\infty }\frac{d{v}_{\mathrm{OUT}}\left(t\right)}{dt}·V_{\mathrm{OUT}}\left(t\right)·dt\\ =C_L·{\left[\frac{v_{{\mathrm{OUT}}^2}}{2}\right]}_{25}^{50}=C_L·\left[\frac{{50}^2}{2}-\frac{{25}^2}{2}\right]E_{\mathrm{diss}2}=E_{\mathrm{SUPPLY}}-E_C=\frac{{25}^2}{2}·C_L\end{array}$

The total energy dissipated for the 0-V_DD transition is:E_{diss—RampUp}=E_diss1+E_diss2=25²×C_LOAD  Equ (2)

It will be seen that the energy dissipated in a discharging transition of the load from V_DD−0, E_{diss—RampDwn} will also equal 25²×C_LOAD.

The total energy dissipated during one switching cycle therefore is:E_diss—2=2×25²×C_LOAD  Equ (3)

Comparing equations 1 and 3, one can conclude that the energy savings factor with a two stage voltage drive as opposed to a one stage voltage drive is equal to 2. In a similar fashion, it can be shown that in theory, energy dissipated for an n-step voltage drive during one switching cycle is:E_diss—n=n×(V_DD/n)²·×C_LOAD  Equ (4)

The energy savings factor for an n-step drive is given by:

$\begin{array}{cc}{S}_n=\frac{V_{{\mathrm{DD}}^2}·C_{\mathrm{LOAD}}}{\left[C_{\mathrm{LOAD}}·\frac{V_{{\mathrm{DD}}^2}}{n^2}·n\right]}=n& \mathrm{Equ}\left(5\right)\end{array}$

With the intermediate voltage set to the arbitrary V₁, E_diss2 will equal C_LOAD×[V₁²+(V_DD−V₁)²], and the total energy dissipated will equal E_diss1+E_diss2, and the normalized total dissipation E_diss<n> will be [V₁²+(V_DD−V₁)²]/V_DD² which forms the parabola shown in FIG. 7, which can be utilized to select optimal values for the voltage steps, in an adiabatically driven output voltage, such as for driving high capacitive loads in piezoelectric drive actuators in ink jet printer head droplet production mechanisms. For example, on the left side of the curve, the normalized energy dissipation drops significantly down to about 10 or so steps and then more or less levels off so that the problems (such as greater complexity of circuitry) overtake any advantage in continued reductions in energy dissipation at smaller incremental changes.

In FIG. 4 there is shown a multi-supply capacitive load drive circuit 80, which may include an output connected to a load, such as a capacitive load C_LOAD 20 such as a 0.8 μF capacitance. The circuit 80 may include a multi-supply stacked (stepped) voltage supply to the load 20 which may comprise a switch 82, which when closed connects a current supply, such as capacitor 82C to the load 20 through a resistor 82R. The stacked supply 80 may further include a switch 84, through which a current supply, such as a capacitor 84C is connected to the load 20 through a resistor 84R. In similar fashion, the remaining stages including switch 86, capacitor 86C and resistor 86R, switch 88, capacitor 88C and resistor 88R, switch 90, capacitor 90C, and resistor 90R, switch 92, capacitor 92C, and resistor 92R, switch 94, capacitor 94C and resistor 94R, switch 96, capacitor 96C and resistor 96R, switch 98, capacitor 98C and resistor 98R, may serve to connect the respective current sources formed by the respective capacitor to the output and thus to the load 20.

A switch 100, when closed, may serve to connect a high voltage, such as V_DD 26, to the load 20 through a resistor 100R. A further switch 102 may serve to connect the load to ground through a resistor 102R.

In operation, as simulated in FIG. 5, the switches 82, 84, 86, 88, 90, 92, 94, 96, 98 and 100 may be sequentially closed (it being understood that throughout this discussion of FIG. 4, all other switches are open, including ones previously described as being closed, when a particular switch is or switches is/are said to be closed) to step the voltage at the output (“OUT”) by selected sequential amounts, such as regular intervals of, by way of example, 5 V intervals, for an exemplary ten stage/step circuit with V_DD equal to 50 V. It will be understood that the steps need not be identical rail to rail, such as, each being a specific fraction of V_DD, such as V_DD/n, as in the Example of FIG. 4.

As shown in FIG. 5, these voltages are sequentially applied at the output, and thus to the load 20 in increasing voltage steps from 0−V_DD, in the exemplary embodiment, 10 steps of voltage output varying in 5 V intervals from 0−V_DD. As with the exemplary two stage circuit of FIG. 2, the source of voltage applied to the load, applied in an exemplary embodiment in charging a capacitive load, is the high voltage source V_DD. The remaining voltage sources are formed in the exemplary embodiment by the respective capacitors 82C, 84C, 86C, 88C, 90C, 92C, 94C, 96C and 98C. This application of a voltage occurs during each of a respective ten successive charging time periods with all but the tenth charging time period causing the output to provide current flow to the load 20 from a respective charge storage device 82C, 84C, 86C, 88C, 90C, 92C, 94C, 96C and 98C. The tenth charging time period resulting in current flow generated by applying the voltage source V_DD to the load 20.

Also as illustrated in the simulated waveform of FIG. 5, in a discharging sequence, each of the switches 98, 96, 94, 92, 90, 88, 86, 84 and 82 are sequentially closed in that order, in the exemplary embodiment, charging the respective capacitors 98C, 96C, 94C, 92C, 90C, 88C, 86C, 84C and 82C in decreasing amounts, as an example, in 5 V intervals, from V_DD−5 to V_DD−45, with the exemplary ten stage circuit and V_DD=50, and equally sized decrements. Finally switch 102 is closed taking the output and the voltage across the load 20 from V_DD−45 to 0 in the exemplary embodiment. It will be understood that as used herein, ground is simply a common voltage below V_DD and need not be zero volts and could even be a negative voltage.

The simulation of FIG. 5 compares a waveform 110 for a single stage 50 V V_DD supply as exemplified by the circuit of FIG. 1 to the simulated waveform 112 created during the simulation of the operation of the circuit of FIG. 4.

In generating FIG. 5, a simulation of the circuit of FIG. 4 was modeled to simulate a 10 step voltage drive for a 50 V switched driving a load 20 equal to a 0.8 μF capacitive load. The large capacitors for the 5 V steps C5V-C45V, are capacitors 82C (C5V), 84C (C10V), 86C (C15V), 88C (C20V), 90C (C25V), 92C (C30V), 94C (C35V), 96C (C40V) and 98C (C45V) and were assumed to be 1 F for simulation purposes only. The nodes have voltages from 5V-45V as noted in FIG. 4, corresponding to capacitors 82C, 84C, 86C, 88C, 90C, 92C, 94C, 96C and 98C, were initialized to the corresponding voltage using an .ic statement in a Spice simulator. The switches 82, 84, 86, 88, 90, 92, 94, 96, 98, 100 and 102 were assumed to be ideal switches. The results of this simulation were compared with a single 50 V step linear drive to determine energy savings. Current through the load 20 was simulated for the sequential closure of each of the switches 82, 84, 86, 88, 90, 92, 94, 96, 98 and 100 in that order during the respective charging time periods shown in FIG. 5, and charge recovery for each of the capacitors 98C, 96C, 94C, 92C, 90C, 88C, 86C, 84C and 82C was also simulated for each of the respective discharging time periods associated with the closure sequentially of the switches 98, 96, 94, 92, 90, 88, 86, 84, 82 and 102 in that order. The average power dissipation can be approximated by looking at the energy lost by the 50 V supply with ground return since there is no charge recovery for the 50 V supply.

For a single stage voltage supply also simulated, the average current drawn was 2.667 amps. The average power dissipation was 133.35 W. The simulation also showed that the current drawn from the 50 V V_DD supply was 0.628 amps and power dissipation was 13.4 W, which matches very closely with the theoretical power dissipation savings for an n stage supply circuit with n=10 as equaling 133.35/13.4=9.95, which is very nearly equal to n=10.

It will also be understood that the drive circuit 10 or 80 or the like can be employed to provide a relatively linear ramp up and a relatively linear ramp down. It will be understood that in a portion of the drive circuit output to the capacitive load, such as an ink droplet production mechanism actuator, linearity is not at a premium, and the savings in power dissipation may overcome any lack of linearity.

Those skilled in the art will understand that voltage drive circuit, such as a capacitive load drive circuit and method of operation of the same, is disclosed and may include a multi-stage stacked charging circuit, such as the circuit of FIG. 2, electrically connected to the capacitive load 20, which may include a first capacitor, such as the capacitor C_BIG 54 electrically connected to the capacitive load 20 through a first switch 50 during a first charging time period, i.e., charging time period 62 of waveform 60 as shown in FIG. 3. The circuit may also include a voltage supply, such as V_DD 26, electrically connected to the capacitive load 20 through a second switch 22 during a second charging time period 64 as shown in FIG. 3. The first capacitor 54 may be electrically connected to the capacitive load 20 through the first switch 50 during a first discharging time period 68 as illustrated in FIG. 3. The system and method in an exemplary embodiment may comprise a third switch 24 electrically connecting the capacitive load 20 to ground during a second discharging time period 70 as illustrated in FIG. 3. The capacitive load 20 may comprise a piezoelectric element 130, such as illustrated in FIG. 6 which may comprise an inkjet printer head 120 inkjet actuator.

The system and method by way of an exemplary embodiment may comprise an n-stage stacked charging circuit, such as the ten stage circuit of FIG. 4, which may comprise n−1 capacitors and a voltage supply, by way of example, the nine capacitors 82C, 84C, 86C, 88C, 90C, 92C, 94C, 96C and 98C and a supply voltage V_DD, each electrically connected in sequence to the capacitive load 20 through a respective first through nth switch, such as switches 82, 84, 86, 88, 90, 92, 94, 96, 98 and 100 during a respective first through nth charging time period, such as is illustrated by way of example in FIG. 5, for the respective closure of the switches 82, 84, 86, 88, 90, 92, 94, 96, 98 and 100; the n−1th capacitors, such as the exemplary capacitors 98C, 96C, 94C, 92C, 90C, 88C, 86C, 84C and 82C may each be sequentially electrically connected to the capacitive load 20 in reverse order during a first through n−1th discharging time period through the respective n−1th through first switches, as illustrated in FIG. 5 for the discharge time periods associated with the closure of each switch 98, 96, 94, 92, 90, 88, 86, 84 and 82 sequentially. The system and method may comprise an n+1th switch, such as, switch 102, electrically connecting the capacitive load 20 to a selected low voltage, such as, ground during an nth discharging period as is also illustrated in FIG. 5. The capacitive load 20 may comprise a piezoelectric element, such as piezoelectric transducer 130, illustrated by way of example in FIG. 6, which may comprise an inkjet printer head 120 inkjet actuator. FIG. 6 illustrates schematically the principal elements of a printer head ink jet 120, such as in an inkjet printer head, with which the present invention may be used. The inkjet printer head ink jet 120 typically includes a nozzle 122 fed by a feed channel 124, which may receive ink from a supply reservoir (not shown) through an ink supply passage 126. A piezoelectric transducer 130, which may be the capacitive load 20 illustrated in FIGS. 1, 2 and 4, or a part of that load, may be connected to the output of a drive circuit, such as those illustrated in FIGS. 1, 2 and 4 by a voltage supply connector 132 and to ground by a connector 134, appearing, as noted above, as a high capacitance load to the drive circuits as shown in FIGS. 1, 2 and 4.

In operation, the transducer 130 deforms, in some fashion as is understood in the art, such as, bends, expands, contracts, etc., as voltage is applied across the connectors 132 and 134 and either bends or bulges in the direction of the channel 124 or bulges out on both sides, including in the direction of the channel 124, serving to squeeze a droplet of ink out of the nozzle each time the transducer is so actuated. In some printer heads, the relaxation of the transducer, as voltage is removed, may also serve to suck ink into the channel 124 through the supply line 126. It will be understood also that the piezoelectric transducer 130 may force ink out of the ink jet droplet producing mechanism 120 but other means, such as squeezing the channel 124 or the nozzle 122 or both, and more than one piezoelectric element 130, may be used per droplet production mechanism 120.

FIG. 8 illustrates schematically and in block diagram form a stepped split drive voltage circuit 300 according to aspects of another embodiment of the present invention. This embodiment can also provide high linearity in addition to the significant power savings provided by the circuit illustrated in FIG. 4. The voltage supply circuit 300 may consist of an amplifier 302 having a positive input 304 to which may be connected a ramped input voltage 390 which may be modified in a level translator 382. The amplifier 302 has an output 310, which may be connected to a capacitive load 400. The amplifier 302 may be a floating low voltage amplifier. A feedback loop 320 connects the output 310 to a negative input 305 of the amplifier 302 through a resistor 322. A plurality of capacitor/switch arrangements including capacitor 330, switch 332 and capacitor 334, switch 336 and capacitor 338, switch 340 and capacitor 350, switch 352 and capacitor 354, switch 356 and capacitor 358, switch 360 are connected across the amplifier 302.

In operation, similarly to the circuit of FIG. 4, the amplifier 302 is stepped between rails selected by the voltages applied to the amplifier 302 determining the range of output of the amplifier 302 during each respective selected set of rails by the rail high voltage and rail low voltage. That is, when the switch 374 is closed, a selected low voltage such as ground or zero volts is applied to the V_SS input to the amplifier 302 through resistors 374R and 306R as the rail low voltage. At the same time, the switch 380 is closed, and the voltage supply 384 voltage of 10 volts is applied to the V_DD input to the amplifier 302 through resistors 382R and 370 as the rail high voltage. Thus, the output of the amplifier 302 in response to the ramping input 390, as applied to the load capacitor 400, is limited to the range of 0-10 volts. That is, the set of rails are respectively 0 volts and 10 volts.

When switches 332 and 352 are closed and all other switches remaining open (it being understood that throughout this discussion of FIG. 8, all other switches are open, including ones previously described as being closed, when a particular switch is or switches is/are said to be closed), the range of the output of the amplifier 302 is set between the 10 volts on capacitor 330 supplied to the V_SS Ramp input through resistors 332R and 306R and the 20 volts on capacitor 350 supplied to the V_DD Ramp input to the amplifier 302 through resistors 352R and 370. That is, when switches 332 and 352 are closed, the output of the amplifier 302 has rails of 10 volts and 20 volts.

Similarly, when switches 336 and 356 are closed, the range of the output of the amplifier 302 may be controlled to be between 20 volts and 30 volts. Similarly, closing switches 340 and 360 results in an output from the amplifier 302 in a range between rails of 30 volts and 40 volts. Connecting the voltage supply 366 of 50 volts to the V_DD Ramp input through switch 364 and resistors 364R and 370 and the 40 volts on capacitor 378 to the V_SS Ramp input through switch 376 and resistors 376R and 306R limits the output of the amplifier 302 between 40 and 50 volts.

Thus in operation, as the combinations of switches 374 and 380, 332 and 352, 336 and 356, 340 and 360, 376 and 364 as closed together, the output of the amplifier 302 is stepped up in ten volt increments and with rails of ten volts in difference, i.e., 0-10, 10-20, 20-30, 30-40 and 40-50 volts.

It will be understood that as the pairs of switches are sequentially closed in that order during the ramp down of the voltage on the load capacitor 400, the rails decrease sequentially from 50-40 volts, 40-30 volts, 30-20 volts, 20-10 volts and 10-0 volts.

Distinct from the adiabatic computing circuits, embodiments of the present invention, including adiabatic stepping and voltage control circuits, are used to control the output of a high capacitive load driver circuit such as a step voltage amplifier by defining the output range for each step. Also, distinct from adiabatic computing circuits, embodiments of the present invention are for an analog application with a portion or all of the output waveform requiring gain and linearity. Creating a floating rail according to aspects of embodiments of the present invention provides several advantages. In certain embodiments, there can be created an inductor based floating rail. Circuits, according to aspects of embodiments of the present invention, can generate a ramp that drives a drive circuit amplifier based upon the signal level, i.e., output signal range of the amplifier.

It should be apparent that the scope and content of the present disclosure are not limited to the above embodiments but should be considered in scope and content taking into account the manner in which the disclosed embodiments may be changed and modified without departing from the scope and spirit of the disclosed subject matter or of the accompanying claims, some of which changes and modifications have been noted above.

Claims

1. A capacitive load drive circuit comprising: an amplifier selectively connected to a plurality of n sequential intermediate rails wherein n is an integer greater than or equal to 2 and each of the plurality of n sequential intermediate rails has a rail high voltage V1 and a rail low voltage V2 with respective selected ranges having an increasing value of V1 during the ramp up and with the respective ranges having a decreasing value of V1 during the ramp down, each defining an output range of the amplifier.

2. The load drive circuit of claim 1 wherein the amplifier further comprises an operational amplifier.

3. The load drive circuit of claim 1 wherein the voltage V1-V2 is the same for each respective rail.

4. The load drive circuit of claim 1 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

5. The load drive circuit of claim 2 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

6. The load drive circuit of claim 3 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

7. A method of driving a capacitive load comprising: connecting an amplifier to a plurality of n sequential intermediate rails wherein n is an integer greater than or equal to 2 and each rail has a rail high voltage V1 and a rail low voltage V2 with respective selected ranges having an increasing value of V1 during a ramp up and with the respective ranges having a decreasing value of V1 during a ramp down, each rail defining a respective output range of the amplifier.

8. The method of claim 7 wherein the amplifier comprises an operational amplifier.

9. The method of claim 7 wherein the voltage V1-V2 is the same for each respective rail.

10. The method of claim 7 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

11. The method of claim 8 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

12. The method of claim 9 wherein each of the rails extends between a positive circuit high voltage and a negative circuit low voltage.

13. The method of claim 7 wherein the capacitive load comprises a piezoelectric element.

14. The method of claim 13 wherein the piezoelectric element comprises an inkjet printer head inkjet droplet producing mechanism actuator.

15. The capacitive load drive circuit of claim 1 wherein a capacitive load driven by the circuit comprises a piezoelectric element.

16. The capacitive load drive circuit of claim 14 wherein the piezoelectric element comprises an inkjet printer head inkjet droplet producing mechanism actuator.