STEPWISE RAMP VOLTAGE GENERATOR

Abstract

A stepwise voltage ramp generator includes a tank capacitor, a terminal of which is coupled to a reference potential to be charged with a voltage ramp. A transistor couples the tank capacitor to a supply line. A diode-connected transistor, biased with a bias current is coupled to the transistor to form a current mirror. A by-pass switch is electrically coupled in parallel to the diode-connected transistor, and is controlled by a PWM timing signal, the duty-cycle of which determines a mean slope of the generated voltage ramp.

Description

FIELD OF THE INVENTION

This invention relates in general to DC-DC voltage converters, and more particularly, to a soft-start circuit for a converter that generates a voltage ramp with a certain slope.

BACKGROUND OF THE INVENTION

A typical DC-DC converter is depicted in FIG. 1. When it is turned on, the output voltage VOUT on the hold capacitor Cout is practically null. The generator of PWM driving signals (PWM GENERATOR) of the half-bridge stage keeps the high-side transistor of the half-bridge saturated until an error signal VERROR, that is essentially a low-pass filtered replica of the difference between a reference voltage VREF and a scaled replica of the output voltage VOUT, decreases.

A tank capacitor Cout is charged through an inductance Lout, that is initially discharged, thus an uncontrolled overshoot of the current through the inductor Lout and a consequent uncontrolled overshoot of the output voltage VOUT with respect to the pre-established regulation value, determined by the voltage VREF, is generated.

The first effect may cause a breach of the specifications of maximum value of the current that can be absorbed from the line VIN or of the power consumption in the high-side of the half-bridge. The second effect may damage the circuits supplied by the regulator.

In order to address this, DC-DC regulators may include a so-called “soft-start” circuit, illustrated in FIG. 1, that drives the voltage VERROR with a pre-established voltage ramp. An exemplary embodiment of the soft-start circuit of FIG. 1 is depicted in FIG. 2. A voltage ramp generated by the generator RAMP GENERATOR is supplied to a clamp operational amplifier that makes the error voltage VERROR increase gradually. The duty-cycle of the PWM driving signal of the high-side transistor is gradually increased and thus overshoots of the current through the inductor Lout and of the voltage on the capacitor Cout may be limited.

The slope of the ramp is established as a function of the characteristics of the regulator and of the desired maximum current during the soft-start phase. Typically, the voltage ramp is generated by injecting a constant current through the tank capacitor. The slope is generally of about 1V/ms and this may be hard to obtain with a fully integrated architecture.

For example, U.S. Pat. No. 5,917,313 discloses a stepwise voltage ramp generator based on a switched capacitor circuit. U.S. Pat. No. 6,316,926 discloses a digital soft-start circuit for a DC-DC converter.

Other voltage ramp generators may, however, be desirable.

SUMMARY OF THE INVENTION

A stepwise voltage ramp generator having a simple architecture, fully integrable on a small silicon area, has now been found by the applicant.

The generator comprises a storage capacitor on which the voltage ramp is produced, and coupled to a supply line through a transistor connected to a diode-connected transistor biased with a certain current to form a current mirror. A by-pass switch driven by an externally generated PWM timing signal is electrically in parallel with the diode-connected transistor of the current mirror.

When the by-pass switch is open, the bias current through the diode is mirrored and injected through the tank capacitor, that is charged. When the by-pass switch is closed, the current mirror is by-passed and the voltage on the tank capacitor remains substantially constant. In this way, the mean slope of the voltage ramp that is produced may be determined by adjusting the duty-cycle of an externally generated PWM timing signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a typical architecture of a DC-DC converter, according to the prior art.

FIG. 2 depicts a typical “soft-start” circuit comprising a voltage ramp generator connected to a clamp circuit, according to the prior art.

FIG. 3 illustrates an exemplary embodiment of a stepwise voltage ramp generator, according to the present invention.

FIG. 4 is a time graph of the main signals of the generator of FIG. 3.

FIG. 5 depicts a digital circuit with an adjustable delay for generating a PWM signal with a certain duty-cycle using a PWM signal with a duty-cycle of 50%, according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An exemplary embodiment of the voltage ramp generator of this disclosure is depicted in FIG. 3. The tank capacitor Cramp is coupled to a supply line through a transistor that mirrors the current flowing through a diode-connected transistor. A by-pass switch is electrically coupled in parallel to the input transistor of the current mirror, thus the latter may be shorted or not depending on the logic state of a PWM timing signal Ck.

When the by-pass switch is off, the circuit mirrors a bias current Iramp through the tank capacitor Cramp. When the by-pass switch is on, current may not flow through the current mirror and a charge current may not be injected in the tank capacitor Cramp.

The graph of FIG. 4, of the main signals of the generator of FIG. 3, illustrates how the generator of this disclosure operates. The amplitude of the voltage steps Vstep depends on the capacitance Cramp, on the current n*Iramp delivered by the current mirror, wherein n is the mirror ratio, and on the duration Ton of the turn off intervals of the by-pass switch according to the following formula:

$V\mathrm{step}=\frac{n·I\mathrm{ramp}}{C\mathrm{ramp}}·T\mathrm{on}$

The mean slope of the voltage ramp is given by the ratio between the amplitude Vstep and the duration of a switching period T:

$\mathrm{Slew\_rate}=\frac{V\mathrm{step}}{T}=\frac{n·I\mathrm{ramp}}{C\mathrm{ramp}}·\frac{T\mathrm{on}}{T}=\frac{n·I\mathrm{ramp}}{C\mathrm{ramp}}·\mathrm{Duty\_cycle}$

thus it can be adjusted by adjusting the duty-cycle of the signal Ck.

The generator may not need a digital-to-analog converter, and can be realized using a current mirror, a capacitor and a transistor. The generator of this disclosure has the versatility of a digital architecture and the ability of implementing even tiny voltage steps without using complex hardware, such as a high resolution DAC.

Optionally, the generator may be equipped with a discharge transistor of the tank capacitor, depicted in FIG. 3, for discharging the capacitor before generating a new voltage ramp.

An exemplary logic circuit for generating a PWM timing signal Ck with a duty-cycle of 50% is depicted in FIG. 5. The logic circuit comprises a NOT logic gate, and an AND logic gate and of an adjustable delay block that determines the duration Ton of the active phase of the signal Ck.

The generator of this disclosure can be realized either in MOS or BJT technology. In the exemplary embodiment of FIG. 3, the current mirror comprises N-channel MOSFETs, but it is possible to use P-channel MOSFETs, inverting the sign of the supply voltage Vcc and the polarity of the signal Ck.

Claims

1-6. (canceled)

7. A stepwise voltage ramp generator comprising: a capacitor;at least one transistor to couple said capacitor to a supply line;a diode-connected transistor configured to be biased with a bias current and coupled to said at least one transistor to thereby form a current mirror; anda bypass switch coupled in parallel to said diode-connected transistor and configured to be controlled by a pulse width modulation (PWM) timing signal.

8. The stepwise voltage ramp generator of claim 7, wherein a slope of a voltage ramp on said capacitor comprises a mean slope.

9. The stepwise voltage ramp generator of claim 7, further comprising a discharge switch coupled in parallel with said capacitor and configured to be controlled by a discharge signal.

10. The stepwise voltage ramp generator of claim 7, wherein said capacitor, said supply line, said at least one transistor, said diode-controlled transistor, and said bypass switch are integrated on a semiconductor chip.

11. The stepwise voltage ramp generator of claim 10, wherein said diode-controlled transistor and said at least one transistor comprise N-channel MOSFETs.

12. The stepwise voltage ramp generator of claim 10, wherein said diode-controlled transistor and said at least one transistor comprise P-channel MOSFETs.

13. The stepwise voltage ramp generator of claim 10, further comprising a logic circuit and an adjustable delay circuit coupled thereto for generating the PWM timing signal from a system clock signal, said logic circuit and said adjustable delay circuit also being integrated on the semiconductor chip.

14. A stepwise voltage ramp generator integrated on a semiconductor chip and comprising: a capacitor;at least one transistor to couple said capacitor to a supply line;a diode-connected transistor configured to be biased with a bias current and coupled to said at least one transistor to thereby form a current mirror;a bypass switch coupled in parallel to said diode-connected transistor and configured to be controlled by a pulse width modulation (PWM) timing signal; anda discharge switch coupled in parallel with said capacitor and configured to be controlled by a discharge signal.

15. The stepwise voltage ramp generator of claim 14, further comprising a discharge switch coupled in parallel with said capacitor and configured to be controlled by a discharge signal.

16. The stepwise voltage ramp generator of claim 14, wherein said diode-connected transistor and said at least one transistor comprise N-channel MOSFETs.

17. The stepwise voltage ramp generator of claim 14, wherein said diode-connected transistor and said at least one transistor comprise P-channel MOSFETs.

18. The stepwise voltage ramp generator of claim 14, further comprising a logic circuit and an adjustable delay circuit coupled thereto for generating the PWM timing signal from a system clock signal.

19. A DC-DC converter comprising: a soft-start circuit comprising a stepwise voltage ramp generator;said stepwise voltage ramp generator comprising a capacitor,at least one transistor to couple said capacitor to a supply line,a diode-connected transistor configured to be biased with a bias current and coupled to said at least one transistor to thereby form a current mirror, anda bypass switch coupled in parallel to said diode-connected transistor and configured to be controlled by a pulse width modulation (PWM) timing signal.

20. The DC-DC converter of claim 19, wherein a slope of a voltage ramp on said capacitor comprises a mean slope.

21. The DC-DC converter of claim 19, wherein said stepwise voltage ramp generator further comprises a discharge switch coupled in parallel with said capacitor and configured to be controlled by a discharge signal.

22. The DC-DC converter of claim 19, wherein said stepwise voltage ramp generator is integrated on a semiconductor chip.

23. The DC-DC converter of claim 22 wherein said stepwise voltage ramp generator further comprises a logic circuit and an adjustable delay circuit coupled thereto for generating the PWM timing signal from a system clock signal.

24. A method of making a stepwise voltage ramp generator comprising: coupling a capacitor to a supply line with at least one transistor;coupling a diode-connected transistor configured to be biased with a bias current to the at least one transistor to thereby form a current mirror; andcoupling a bypass switch in parallel with the diode-connected transistor and configured to be controlled by a pulse width modulation (PWM) timing signal.

25. The method of claim 24, wherein a slope of a voltage ramp on said capacitor comprises a mean slope.

26. The method of claim 24, further comprising coupling a discharge switch in parallel with the capacitor and configured to be controlled by a discharge signal.

27. The method of claim 24, wherein the capacitor, the supply line, the at least one transistor, the diode-connected transistor, and the bypass switch are integrated on a semiconductor chip.

28. The method of claim 27, wherein the diode-connected transistor and the at least one transistor comprise N-channel MOSFETs.

29. The method of claim 27, wherein the diode-connected transistor and the at least one transistor comprise P-channel MOSFETs.

30. The method of claim 27, further comprising coupling a logic circuit and an adjustable delay circuit to the bypass switch for generating the PWM timing signal from a system clock signal, the logic circuit and the adjustable delay circuit also being integrated on the semiconductor chip.