Patent Application
20250149102
The present disclosure relates to the field of semiconductor and Complementary Metal Oxide Semiconductor (CMOS) hybrid integrated circuit technology, and particularly to a Resistive Random Access Memory (RRAM) storage array circuit with a CMOS device.
With the development of artificial intelligence and deep learning technologies, artificial neural networks are widely used in fields such as natural language processing, image recognition, autonomous driving, and graph neural networks, etc. However, an increasing network size causes a large amount of energy to be consumed for data transfer between a memory and a conventional computing device such as a CPU or a GPU, which is referred to as the von Norman bottleneck. The computation that occupies the most important part of the artificial neural network algorithm is the Vector Matrix Multiplication (VMM) computation. The process-in-memory based on the non-volatile memory means that weight values are stored in non-volatile memory units, and analog vector matrix multiplication computation is performed on the array, thereby avoiding frequent data transfer between the memory and the computing units. Accordingly, the process-in-memory based on the non-volatile memory is considered as a promising way to break through the von Neumann bottleneck.
At present, a non-volatile memory device such as a Resistive Random Access Memory (RRAM), a Phase Change Random Access Memory (PCRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FeRAM), and a Ferroelectric Field Effect Transistor (FeFET), etc., stores a weight value in a conductivity value of the device after the weight value is written. The devices are arranged in an array, and a voltage is inputted from one end as an input of the vector matrix multiplication. In the array, through the computation based on the Ohm's law and Kirchhoff's law, a current is obtained at the other end of the array, which is a summation result of the vector matrix multiplication, and the summation result is generally read out by using an analog-to-digital converter (ADC).
In the above-mentioned multiple novel non-volatile memories, the dual-port non-volatile memory is widely concerned and studied due to a higher theoretical density and a reduced process cost caused by a simple structure thereof. In the actual applications, the dual-port memory needs the formation of a storage array to implement a high-density structure and high-speed read/write. In the existing method, a 1-transistor-1 resistor (1T1R) array is mainly formed, and an N-type transistor is generally used in the mainstream method. However, in actual use, on the one hand, since a power supply Vdd at an advanced node is lower, a maximum gate voltage that can be applied to the transistor is limited, and on the other hand, a non-zero source voltage of the N-type transistor further reduces the gate-source voltage of the transistor when the N-type transistor has a source resistor. Accordingly, there exists a problem that a driving current is insufficient during the operation of the dual-port memory at the advanced node, thereby limiting a further reduction of a device size and limiting the improvement of the density of the storage array.
In view of the above, the present disclosure provides a storage array to address the problems of voltage limitation in the existing storage circuits, resulting in insufficient driving current, limiting the miniaturization development of the device and the increasement of the density of the storage array.
In the present disclosure, a storage array is provided, including memory cells arranged in a matrix array, each memory cell comprising two memories, one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor; a source of the P-channel field effect transistor is connected to a drain of a N-channel field effect transistor, a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor, the two memories are respectively configured to be connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor.
Optionally, the memory cell comprises a first N-channel field effect transistor, a first P-channel field effect transistor, and a second N-channel field effect transistor connected in sequence; gates of the first N-channel field-effect transistor, the second N-channel field-effect transistor, and the first P-channel field-effect transistor are configured to be connected to different word lines respectively, a source of the first N-channel field-effect transistor and a source of the second N-channel field-effect transistor are connected to different source lines respectively.
Optionally, a source line is configured to be connected to a positive voltage VDD, a saturation current of the first P-channel field effect transistor is represented as follows:
where
and Vtp represent inherent parameters of the first P-channel field effect transistor, Vsg represents a source-gate voltage of the first P-channel field effect transistor, Vs represents a source voltage of the first P-channel field effect transistor.
Optionally, the memories includes a first memory and a second memory, the first memory is configured to be connected to the source of the first P-channel field effect transistor, and the second memory is configured to be connected to the source of the second N-channel field effect transistor.
Optionally, the storage array includes M×N memory cells, where M represents the number of rows, N represents the number of columns, the word lines comprise a word line N connected to gates of the N-channel field effect transistors and a word line P connected to a gate of the P-channel field effect transistor; memory cells in the same row are configured to share the word line N and a bit line, and memory cells in the same column are configured to share the word line P and a source line.
Optionally, the storage array includes a storage mode, a write-1 mode, a write-0 mode, and a read mode; in the storage mode, each memory cell is configured to be in a non-operating state and maintain original data thereof, in the write-1 mode and the write-0 mode, specified memory cells are configured to be in a state-1 and a state-0 respectively, wherein voltages of the specified memory cells are less than a preset voltage VDD; in the read mode, a source line of a memory cell is configured to be connected to a read voltage to allow a read current to reach a bit line through the memory cell and read a corresponding state of the memory cell from the bit line.
Optionally, in the storage mode, all the word lines N, the bit lines, and the source lines are configured to be connected to GND, and the word line P is configured to be connected to the preset voltage VDD; the P-channel field effect transistor and the N-channel field effect transistors are configured to be in an off state.
Optionally, in the write-1 mode, the word line N is configured to be connected to the preset voltage VDD, and the word line P is configured to be connected to the GND; after a target memory cell is strobed, a source line of the target memory cell is configured to be connected to a preset write-1 voltage, a target bit line of the target memory cell is configured to be connected to the GND, the rest of the bit lines are configured to be connected to the write-1 voltage, and the target memory cell is configured to be written to the state-1.
Optionally, in the write-0 mode, the word line N is configured to be connected to the preset voltage VDD, the word line P and the source line are configured to be connected to the GND; after a target memory cell is strobed, a bit line of the target memory cell is configured to be connected to a preset write-0 voltage, source lines of other memory cells are configured to be connected to the preset write-0 voltage, a write current flows from the bit line through the target memory cell to the source line, and the target memory cell is configured to be written to the state-0.
Optionally, in the read mode, the word line N is configured to be connected to the preset voltage VDD, and the source line is configured to be connected to the read voltage; after a target memory cell is strobed, a read current flows from the source line through the target memory cell to the bit line, and a corresponding state of the memory cell is read from the bit line.
By using the above-mentioned storage array, a memory cell includes two memories, one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor; a source of the P-channel field effect transistor is connected to a drain of a N-channel field effect transistor; a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor, accordingly a drive capability of a circuit when a high level is inputted can be increased, thereby solving the driving problem and contributing to further improving the density of the storage array.
In order to achieve the above and related purposes, one or more aspects of the present disclosure include limitations described in detail later. Some exemplary aspects of the present disclosure are described in detail in the following description and the accompanying drawings. However, these aspects indicate merely some of the various modes in which the principle of the present disclosure may be used.
In addition, the present disclosure is intended to include all these aspects and equivalents thereof.
The other purposes and results of the present disclosure will become clearer and easier to understand by reference to the description below in conjunction with the accompanying drawings and with more comprehensive understanding of the present disclosure. In the accompanying picture:
In the following description, for the purpose of illustration, many specific details are described in order to provide a comprehensive understanding of one or more embodiments. However, it is obvious that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, well-known structures and devices are shown in a block diagram form.
In a current N-type transistor storage array, a maximum gate voltage that can be applied to a transistor in the storage array is limited, and when the N-type transistor has a source resistor, a non-zero source voltage further reduces a gate-source voltage of the transistor. Therefore, there exists a problem that a driving current is insufficient during the operation of the dual-port memory at an advanced node. In order to address the above problem, the present disclosure provides a storage array, in which a memory cell includes two memories, and one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor. A source of the P-channel field effect transistor is connected to a drain of the N-channel field effect transistor, and a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor. Accordingly, a storage device can be driven by two N-channel metal oxide semiconductor (NMOS) devices in parallel, thereby increasing a drive capability of a circuit when a high level is inputted, solving the driving problem, which contributes to further improving the density of the storage array.
In the description of the present disclosure, a line connected to a gate of a transistor is referred to as a Word Line (WL), a line connected to a source of the transistors is referred to as a Source Line (SL), and a line connected to one end of a device is referred to as a Bit Line (BL).
In order to detail the storage array in the present disclosure, the specific embodiments of the present disclosure will be elaborated below with reference to the accompanying drawings.
As shown in
Specifically, in the structure shown in
A gate of the first N-channel field effect transistor is connected to a word line WL0, a gate of the first P-channel field-effect transistor is connected to a word line WL1, and a gate of the second N-channel field-effect transistor is connected to a word line WL2. The source lines include a source line SL0 connected to the source of the first N-channel field effect transistor and a source line SL1 connected to a drain of the second N-channel field effect transistor. The memories include a first memory connected to the source of the P-channel field effect transistor and a second memory connected to the source of the N-channel field effect transistor. The first memory is connected to a bit line BL0, and the second memory is connected to a bit line BL1.
In addition, in the present disclosure, it is equivalent to that one PMOS in the center is connected to two 1T1R units, the conduction of the field effect transistor can be controlled by signals on the WL0, the WL1, and the WL2, and operating voltages applied on the SL and the BL can achieve reading and writing of the memories in the memory cell.
For a PMOS serving as a gating device, a source line is connected to a positive voltage VDD, so that the positive voltage can be effectively transmitted. In this case, a saturation current of the first P-channel field effect transistor is represented as follows:
where
and Vtp represent inherent parameters of the first P-channel field effect transistor, Vsg represents the source-gate voltage of the first P-channel field effect transistor, Vs represents the source voltage of the first P-channel field effect transistor. Accordingly, when PMOS transmits the positive voltage, since Vsg is affected by a voltage at the other end, the PMOS gate-source voltage drop can reach VDD. For the NMOS, the maximum PMOS gate-source voltage drop is only VDD−I*R, where a typical value of I*R is equal to 0.7V. In this case, the saturation current of the PMOS device is significantly greater than that of an NMOS device with the same size. In other words, a divided voltage of the PMOS device is much smaller than that of the NMOS device when the same current flows through the PMOS device and the NMOS device.
In the memory cell shown in
In a specific implementation mode of the present disclosure, the storage array has four operating modes: a storage mode, a write-1 mode, a write-0 mode, and a read mode. In the storage mode, each memory cell does not operate and maintains its own original data. In the write-1 mode and the write-0 mode, specified memory cells are respectively in a state-1 and a state-0, and voltages of the specified memory cells are less than a preset voltage VDD. In the read mode, the source lines of the memory cells are connected to a read voltage, so that a read current reaches the bit lines through the memory cells, and corresponding states of the memory cells are read from the bit lines.
Specifically, in the storage mode, all word lines N, bit lines, and source lines are connected to the GND, and the word lines P are connected to the preset voltage VDD. Both the P-channel field effect transistors and the N-channel field effect transistors are in an off state. In the write-1 mode, the word line N is connected to the preset voltage VDD, and the word line P is connected to the GND. After a target memory cell is strobed, a source line of the target memory cell is connected to a preset write-1 voltage, a target bit line of the target memory cell is connected to the GND, the rest of the bit lines are connected to the write-1 voltage, and then the target memory cell is written to the state-1. In the write-0 mode, the word line N is connected to the preset voltage VDD, the word line P and the source line are connected to the GND. After the target memory cell is strobed, a bit line of the target memory cell is connected to the preset write-0 voltage, source lines of other memory cells are connected to the preset write-0 voltage, and the write current flows from the bit lines through the target memory cell to the source line, so that the target memory cell is written to the state-0. In the read mode, the word line N is connected to the preset voltage VDD, and the source line is connected to the read voltage. After the target memory cell is strobed, the read current flows from the source line through the target memory cell to the bit line, and a corresponding state of the memory cell is read from the bit line.
As a specific example,
With reference to
Specifically, in the non-operating state, all WLNs, BLs, and SLs are connected to the GND, and all WLPs are connected to the VDD. In this case, all transistors are in an off state, and the array does not operate.
Write-1 mode: for the (0, 0) memory cell, WLN0 and WLN1 are connected to the VDD; WLP and BL0 are connected to the GND; SL0, SL1 and BL1 are connected to the write-1 voltage, and SLIs of other memory cells are connected to the write-1 voltage. The connections of other lines are the same as that in the non-operating state. In this case, all MOSs in the (0, 0) memory cell are turned on, the write current flows from SL0 and SL1 through a target memory to BL0, and no current flows through other memories, and the target memory is written to 1.
Read mode: for the (0, 0) memory cell, the WLN0 is connected to the VDD and the SL0 is connected to the read voltage, and the connections of other lines are the same as that in the non-operating state. In this case, the NMOS on the left side in the (0, 0) memory cell is turned on, and the read current flows from the SL0 through the target memory to the BL0, and a corresponding state of the target memory can be read from the BL0.
Write-0 mode: for the (0, 0) memory cell, WLN0 and WLN1 are connected to the VDD, WLP is connected to the GND, SL0, SL1, and BL1 are connected to the GND, BL0 is connected to the write-0 voltage, SL0s of other memory cells are connected to the write-0 voltage, and connections of other lines are the same as that in the non-operating state. In this case, all MOSs in the (0, 0) memory cell are turned on, the write current flows from the BL0 through the target memory to the SL0 and the SL1, and no current flows through other memories, and the target memory is written to 0.
It should be noted that the aforementioned description of the present disclosure only explains a method for operating a single memory cell in the array once, and only one row and one column of memory cells are strobed each time. A person of ordinary knowledge in the art should understand that the operation method may be easily extended to multiple rows and multiple columns of memory cells, so that read and write operations can be performed on multiple rows and multiple columns of units in parallel, thereby increasing a data throughput of the array.
According to the aforementioned storage array of the present disclosure, a single memory cell includes two memories, one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor. The source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor, the drain of the P-channel field-effect transistor is connected to the source of the N-channel field-effect transistor, and accordingly, the memories can be driven by two NMOS devices in parallel, thereby increasing the drive capability when a high level is inputted into the circuit, solving the drive problem, and contributing to further improving the density of the storage array.
It should be further noted that in the present disclosure, relationship terms such as the first and the second are merely used for distinguishing one entity or operation from another, and do not definitely require or imply that there is any such actual relationship or sequence between these entities or operations. Furthermore, the terms “include”, “comprise” or any other variant thereof are intended to cover non-exclusive inclusion such that a process, method, article or device that includes a series of elements includes not only those elements but also other elements that are not explicitly listed, or includes elements inherent in such a process, method, article or device. In the absence of more restrictions, an element defined by the statement “including a . . . ” does not exclude other same elements existing in the process, method, article, or device that includes the element.
The above description of embodiments in the present disclosure enables a person skilled in the art to implement or use the present disclosure. It is obvious for those skilled in the art to make various modifications to these embodiments, and the general principle defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments shown herein, but is intended to conform to the widest scope consistent with the principle and novel features disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310736845.6 | Jun 2023 | CN | national |
The present application is a US national stage application of PCT international application PCT/CN2023/108867, filed on Jul. 24, 2023, which claims priority to Chinese Patent Application with No. 202310736845.6, entitled “Storage Array”, and filed on Jun. 20, 2023, the content of which is expressly incorporated herein by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/108867 | 7/24/2023 | WO |
