The present invention relates to a memory data access method and a memory.
Error Correction Code (ECC) is used to detect and correct the incorrect data. It has been shown that numerous algorithms can support ECC, such as the common Hamming code, in which 8-bit data needs 4 parity bits and 64-bit data needs 7 parity bits. Thus, a proper algorithm may be selected according to the data length and the number of the data bits which need detection and correction.
For example, as to different Double Data Rate(DDR) structures (DDR1/2/3), the data prefetching length for typical stream in-and-out data reading is 32-bit, 64-bit, 128-bit, and the like. A reasonable and compromising solution is to use 7 parity bits or 8 parity bits for a 64-bit data (according to different ECC algorithms), as shown in
Nevertheless, as the presence of the Data Mask (DM), it is not easy for the DRAM to realize detection and correction functions. That is to say, when external data are written to a storage unit, since one or more Bytes may be masked off, the data previously stored in the storage unit will not be overwritten. In this way, the ECC encoding process will not generate parity bits successfully, as shown in
According to a first aspect of the invention, there is provided a memory error correction method, mainly for solving the problem that due to the presence of a data mask in the existing ECC encoding process, the encoding cannot smoothly proceed and thus the parity bits cannot be generated, or the area of the storage array needs to be increased even if the parity bits are generated.
The technical solutions of the present invention are as follows:
A memory error correction method, comprising the following steps:
According to a preferred embodiment of the first aspect of the present invention, when the above external data is 64-bit Hamming code, the parity bit is 7-bit, and the flag bit is 1-bit that is used as the 65th bit in a 65-bit data string.
According to a preferred embodiment of the first aspect of the present invention, if only 1-bit data is incorrect in the above step 2, no error correction is needed when the incorrect data is a flag bit or a parity bit; when the incorrect data is not a flag bit or a parity bit, whether a data mask is present or absent shall be judged based on the flag bit; if the data mask is absent, the parity bit is used to perform error correction on the external data, and if the data mask is present, error correction is not performed.
According to a preferred embodiment of the first aspect of the present invention, if two-bit or more data error is present in the above step 2, error correction is not performed.
According to a second aspect of the present invention, there is provided a memory data access method, characterized in that the method comprises the following steps:
According to a preferred embodiment of the second aspect of the present invention, the generated flag bit is stored as an independent part.
According to a preferred embodiment of the second aspect of the present invention, a parity bit for flag bit is generated for the generated flag bit, and the parity bit for flag bit and the flag bit together are stored.
According to a preferred embodiment of the second aspect of the present invention, after the flag bit and the parity bit for flag bit are read out, the parity bit for flag bit is used to detect and correct the flag bit.
According to a preferred embodiment of the second aspect of the present invention, the algorithm for generating a parity bit and the algorithm for generating a parity bit for flag bit are the same.
According to a preferred embodiment of the second aspect of the present invention, the flag bit is stored either as a data bit or as a parity bit.
According to a preferred embodiment of the second aspect of the present invention, if the flag bit expresses the absence of a data mask, the flag bit is removed from the data bit or from the parity bit prior to detection and correction on the data.
According to a third aspect of the invention, there is provided a memory, comprising:
According to a preferred embodiment of the third aspect of the present invention, the flag bit is stored in the storage unit as an independent part.
According to a preferred embodiment of the third aspect of the present invention, the flag bit generation unit generates a parity bit for flag bit for the flag bit, and the parity bit for flag bit and the flag bit together are stored in the storage unit.
According to a preferred embodiment of the third aspect of the present invention, a flag bit correction unit is further comprised, which uses the parity bit for flag bit to detect and correct the flag bit after the flag bit and the parity bit for flag bit are read out from the storage unit.
According to a preferred embodiment of the third aspect of the present invention, the algorithm for generating a parity bit and the algorithm for generating a parity bit for flag bit are the same.
According to a preferred embodiment of the third aspect of the present invention, the flag bit is stored in the storage unit either as a data bit or as a parity bit.
According to a preferred embodiment of the third aspect of the present invention, if the flag bit expresses the absence of a data mask, the correction unit removes the flag bit from the data bit or from the parity bit before detecting and correcting the data.
According to a preferred embodiment of the third aspect of the present invention, Hamming Code is used to generate a parity bit.
According to a preferred embodiment of the third aspect of the present invention, the memory is a dynamic random access memory.
The advantage of the present invention lies in that:
Whether a data mask is present or absent is judged by using a flag bit, and the memory data access method provided by the present invention can reduce the possibility of memory error when a data mask is present.
Furthermore, the present invention is suitable for various memory products in which a data mask is present, such as DRAM, SRAM, Flash, and the like.
A better understanding of the present invention will be obtained with reference to the drawings. It should be understood that the drawings depict merely for an illustrative purpose and should not be deemed as limitations on the present invention.
With reference to
Firstly, the 64-bit external data are directly written (see A in
Secondly, 7 parity bits or 8 parity bits (see B in
Thirdly, the new 64-bit data and the 7 parity bits or 8 parity bits are written to the storage array and completely substitute for the previously information stored in the storage array (see C in
With reference to
Firstly, the 64-bit data and 7 parity bits or 8 parity bits are read out from the storage array (see C in
Secondly, the parity bits will decode and judge whether there are errors in the data according to a give rule. If there is an error, the parity bits will judge which bit is error and correct the incorrect data (see B in
Thirdly, the decoded data is read out (see A in
With reference to
Firstly, the 56-bit data of the external 64-bit data are written to the storage array (see A in
Secondly, the parity bits are still generated from the external 64-bit data (see B in
Thirdly, in the storage array, the 56-bit data of the 64-bit data are substituted by the external data written into the storage array, and the remaining 8-bit data still keep their original information. At this time, the parity bits are totally error parity bits for the 64-bit data (56-bit external data plus 8-bit original data) in the storage array (see C in
Therefore, it desperately needs a method that can judge whether a data mask is present or absent when data is read out.
Hereinafter, the present invention will be described in detail with reference to
The concept of the method is to detect whether DM occurs, if DM occurs, invalidation of the parity bit is indicated and decoding and correction are not performed. The detection of whether DM occurs is performed based on the flag bit, which expresses whether a data mask is present or absent in the data.
Hamming code is taken as an example in the following examples. Nevertheless, it should be understood that for a storage, given the error rate and correction cost, the common ECC is a code that can detect two bits and correct one bit. Thus, as to the Hamming code in the embodiments of the present invention, the correction method of the present invention can correct one-bit error. Nevertheless, this does not mean the exclusion of other ECCs that can correct two-bit or more error, i.e., the present invention is also suitable for the situations where two-bit or more data are incorrect. That is to say, other algorithms, such as parity check, etc, can be used to generate parity bits.
For Hamming code, 64-bit data needs 7 parity bits to achieve the functions of detecting and correcting one-bit incorrect data. Thus, a flag bit can serve as one data bit in a 65-bit data string, and the flag bit will expresses whether DM occurs, as shown in
In the example of
As described above, as a preferred embodiment according to the method of the present invention, the flag bit can be stored either as a data bit or as a parity bit. When the flag bit is stored either as a data bit or as a parity bit, if the flag bit expresses the absence of a data mask, the flag bit is removed from the data bit or from the parity bit prior to detection and correction on the data; if the flag bit expresses the presence of a data mask, when the flag bit is stored as a data bit, the flag bit is removed from the data bit but detection and correction are not performed on the data, and then the data is directly outputted, and when the flag bit is stored as a parity bit, no processing is performed on data and the data is directly outputted.
Furthermore, according to another preferred embodiment of the method of the present invention, the generated flag bit can be stored as an independent part, i.e., it can be stored as an individual part dependent of the data and the parity bit. When the flag bit is stored as an independent part, it is preferable to generate for the flag bit a parity bit for flag bit, which is used to detect and correct the flag bit, in order to improve reliability of the flag bit. The parity bit for flag bit and the flag bit together are stored. In this regard, after the flag bit and the parity bit for flag bit are read out, the parity bit for flag bit is used to detect and correct the flag bit, and subsequently whether a data mask is present or absent is judged based on the flag bit that has been detected and corrected.
Preferably, the algorithm for generating a parity bit and the algorithm for generating a parity bit for flag bit are the same.
The parity bit generation unit 102 generates for the data to be stored a parity bit, which is stored to the storage unit 101 and used to detect and correct the data. The flag bit generation unit 103 generates for the data to be stored a flag bit, which expresses whether a data mask is present or absent in the data to be stored and is stored to the storage unit 101. The data is stored into the storage unit 101 via the writing unit 100.
The reading unit 104 reads out the stored data, flag bit and parity bit from the storage unit 101. If the flag bit expresses the presence of the data mask, the correction unit 105 performs no detection or correction on the read data, and the data is directly outputted from the memory 10; if the flag bit expresses the absence of the data mask, the correction unit 105 detects and corrects the read data, and then the detected and corrected data is outputted from the memory 10.
According to a preferred embodiment of the present invention, the flag bit can be stored as an independent part in the storage unit 101, i.e., it can be stored as an individual part dependent of the data and the parity bit. In this regard, preferably, the flag bit generation unit 103 can generate for the flag bit a parity bit for flag bit, which is used to detect and correct the flag bit. The parity bit for flag bit and the flag bit together are stored in the storage unit 101.
The memory 10 can further comprise a flag bit correction unit 106. After the reading unit 104 reads out the data, the parity bit, the flag bit, and the parity bit for flag bit from the storage unit 101, the flag bit and the parity bit for flag bit are sent to the flag bit correction unit 106, and the data and the parity bit are sent to the correction unit 105. The flag bit correction unit 106 uses the parity bit for flag bit to detect and correct the flag bit, and then the flag bit correction unit 106 sends the detected and corrected flag bit to the correction unit 105 for determining whether a data mask is present or absent based on the flag bit.
Preferably, the algorithm for generating a parity bit and the algorithm for generating a parity bit for flag bit are the same.
According to another preferred embodiment of the present invention, the flag unit can also be stored in the storage unit 101 either as a data bit or as a parity bit. At this time, after the reading unit 104 reads out the stored data, flag bit and parity bit from the storage unit 101, the data, the flag bit and the parity bit are sent to the correction unit 105. If the flag bit expresses the absence of a data mask, the correction unit 105 removes the flag bit from the data bit or from the parity bit prior to detection and correction on the data, then detection and correction are performed on the data, and the detected and corrected data are outputted from the memory. If the flag bit expresses the presence of a data mask, when the flag bit is stored as a data bit, the correction unit 105 removes the flag bits from the data bit but performs no detection and correction on the data, and then the data is directly outputted from the memory 10; when the flag bit is stored as a parity bit, the correction unit 105 performs no processing on the data, and the data is directly outputted from the memory 10.
According to an embodiment of the present invention, Hamming Code is used to generate a parity bit for the data to be stored.
According to an embodiment of the present invention, the memory is a dynamic random access memory.
While the above illustrate some embodiments of the present invention, it should be realized that the embodiments of the present invention are not limited to these above. Various modifications to the present invention can be made without departing from the scope of the invention.
Number | Date | Country | Kind |
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201310088811.7 | Mar 2013 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2014/073667 | 3/19/2014 | WO | 00 |