Patent Application
20250211448
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0187516, filed on Dec. 20, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concepts relate to electronic devices, and more particularly to, storage devices, operating methods of controllers, and systems that are configured to protect storage devices from malicious attackers and enhancing the security of the storage devices.
Semiconductor memory devices may be classified into a volatile type such as dynamic random access memory (DRAM) and static random access memory (SRAM), and a non-volatile type such as electrically erasable programmable read only memory (EEPROM), ferroelectric random access memory (FRAM), phase changer random access memory (PRAM), magnetic random access memory (MRAM), and flash memory. Volatile memory devices lose data stored therein when power is turned off, while non-volatile memory devices retain data stored therein even when power is turned off.
Devices that use non-volatile memory include, for example, MP3 players, digital cameras, cellular phones, camcorders, flash cards, and solid state disks (SSDs), but are not limited thereto. The number of devices using non-volatile memory as a storage device has increased, and along with this, the capacity of non-volatile memory has also rapidly increased.
A debugging device may execute an authentication program to perform a debugging operation on a storage device including non-volatile memory. For example, the debugging device may request Secure Joint Test Action Group (JTAG) authentication from a storage device. However, when the authentication program is hijacked by a malicious attacker, secret information stored in the storage device may be leaked. Therefore, research is underway to increase the security of storage devices.
The inventive concepts provide storage devices, operating methods of a controller, and systems configured to protect storage devices from malicious attackers and enhance security of the storage devices, even when authentication program are hijacked.
According to some example embodiments, there is provided a storage device comprising a one-time programmable (OTP) memory configured to store a hash value; a non-volatile memory configured to store token history information including a history of a number of times of use of at least one token; and a memory controller configured to receive temporary authentication information, the temporary authentication information including a temporary token comprising a token identifier and a maximum count indicating a maximum number of times the temporary token is permitted to be used, a public key of an authentication server, a temporary public key and a temporary private key corresponding to the storage device, and a temporary digital signature generated for the temporary public key and the temporary token, the temporary digital signature generated based on a private key of the authentication server paired with the public key, verify the public key based on the hash value, check whether each of the temporary token and the temporary public key is valid by verifying the temporary digital signature, based on the verified public key and a digital signature algorithm, and determine whether to use the temporary public key, based on the temporary token that is valid and the token history information.
According to some example embodiments, there is provided an operating method of a controller. The operating method comprising receiving temporary authentication information embedded in a computing device, the temporary authentication information including a public key of an authentication server and a temporary public key for the controller, a temporary token comprising a device identifier that specifies the controller, a maximum count, and a token identifier, and a temporary digital signature generated based on a private key paired with the public key of the authentication server, the temporary public key, and the temporary token; verifying the temporary authentication information based on a digital signature algorithm and token history information including a history of a number of times of use of at least one token; and performing debugging of a Secure Joint Test Action Group (JTAG) by performing a challenge-response protocol through the challenge-response protocol based on results of the verifying.
According to some example embodiments, there is provided a system comprising a computing device and a semiconductor device. The computing device is configured to execute an authentication program including temporary authentication information. The temporary authentication information including a temporary token comprising a token identifier and a maximum count indicating a maximum number of times the temporary token is permitted to be used, a public key of an authentication server, a temporary public key and a temporary private key corresponding to the semiconductor device, and a temporary digital signature generated for the temporary public key and the temporary token, the temporary digital signature generated based on a private key of the authentication server paired with the public key. The semiconductor device is configured to store a hash value and token history information including a history of a number of times of use of at least one token, and perform a Secure JTAG authentication based on the token history information, the hash value, and the temporary digital signature.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, some example embodiments will be described with reference to the accompanying drawings.
Referring to
The semiconductor device 110 may perform debug authentication on the computing device 120 that is authenticated and may communicate with the authenticated computing device 120 for a debugging operation. According to some example embodiments, debug authentication methods include a password authentication and a challenge-response protocol. The challenge-response protocol uses a public key cryptosystem.
In some example embodiments, the semiconductor device 110 may be implemented as a storage device. The semiconductor device 110 may include a memory controller 111, a non-volatile memory 112, and a one-time programmable (OTP) memory 113.
In some example embodiments, when the memory controller 111 receives a debugging request signal from the computing device 120, power may be supplied to the memory controller 111 for a debugging operation. The memory controller 111 may receive a debugging request signal from the computing device 120 through a Joint Test Action Group (JTAG) interface. The memory controller 111 may receive a JTAG signal through a plurality of pins. For example, the memory controller 111 may receive a test-data-in (TDI) signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal through a TDI pin, a TCK pin, a TRST pin, and a TMS pin. A test-data-out (TDO) signal processed by the memory controller 111 may be output to the computing device 120 through a TDO pin.
In some example embodiments, the memory controller 111 may receive temporary authentication information from the computing device 120. The memory controller 111 may verify a public key included in the temporary authentication information based on a hash value stored in the OTP memory 113. Once the public key is verified, the memory controller 111 may verify a temporary digital signature included in the temporary authentication information based on the verified public key and a digital signature algorithm to check the validity of each of a temporary token and a temporary public key that are included in the temporary authentication information. In some example embodiments, when the temporary token and the temporary public key are valid, the memory controller 111 may determine whether to proceed with a challenge-response protocol based on the verified temporary token and token history information stored in the non-volatile memory 112.
The non-volatile memory 112 may include a plurality of memory cells. In some example embodiments, the memory cells may be NAND flash memory cells. However, the inventive concepts are not limited thereto, and in some example embodiments, the memory cells may be resistive memory cells such as resistive random access memory (ReRAM) cells, phase change random access memory (PRAM) cells, or magnetic random access memory (MRAM) cells. The non-volatile memory 112 may store the token history information. The token history information may refer to information on the history of at least one token, for example, the use history of at least one token.
The OTP memory 113 may store at least one hash value.
The computing device 120 may be referred to as a debugging device or debugger. The computing device 120 may receive a public key and a private key of the authentication server 130 from the authentication server 130. The computing device 120 may execute an authentication program 121 to generate a public key of the authentication server 130 and generate a digital signature using a random number and a private key of the authentication server 130. In some example embodiments, the computing device 120 may receive from the authentication server 130, a temporary public key, a temporary private key, a temporary digital signature, and a temporary token for the semiconductor device 110. In some example embodiments, when the computing device 120 and the authentication server 130 are able to communicate with each other, the computing device 120 may receive temporary authentication information including a public key, a temporary public key, a temporary token, and a temporary digital signature from the authentication server 130 and may execute the authentication program 121 to transfer the temporary authentication information to the semiconductor device 110. In some example embodiments, when the computing device 120 and the authentication server 130 are unable to communicate with each other, the computing device 120 may embed temporary authentication information into the authentication program 121. The computing device 120 may receive a random number from the semiconductor device 110, generate a digital signature based on the random number and a temporary private key, and transmit or send the digital signature to the semiconductor device 110. The computing device 120 may perform a challenge-response protocol together with the semiconductor device 110 to perform Secure JTAG debugging through the challenge-response protocol. Secure JTAG may refer to a device security mechanism that enables the computing device 120 to perform JTAG communication only when it is possible to authenticate the computing device 120 using secret information through the challenge-response protocol. For example, in the challenge-response protocol used in Secure JTAG, techniques using passwords, symmetric key cryptography, and public key cryptography may be possible, and techniques using public key cryptography may be the most secure.
The authentication server 130 may generate a public key and a private key. The authentication server 130 may generate a temporary public key and a temporary private key for each of semiconductor devices 110. The temporary public key and the temporary private key may be unique information for each of semiconductor devices 110. For example, when an identifier of the semiconductor device 110 is changed, the temporary public key and the temporary private key generated for the semiconductor device 110 may also be changed. The authentication server 130 may generate a temporary token for each of semiconductor devices 110. The temporary token may include an identifier of the semiconductor device 110, a maximum count, and an identifier of a token. For example, the maximum count may refer to the maximum number of times the temporary token may be used in the semiconductor device 110. The authentication server 130 may generate a temporary digital signature corresponding to the semiconductor device 110, based on a private key, a temporary public key, a temporary token, and a digital signature algorithm. The authentication server 130 may include hardware such as a hardware security module (HSM). The HSM may be an enhanced tamper-proof hardware device configured to protect encryption processes by generating, protecting, and managing keys used to encrypt and decrypt data and generating digital signatures and certificates. The HSM may be tested, verified, and certified according to high-level security standards including FIPS 140-2 and Common Criteria. The HSM may generate a random number using hardware noise as a source.
According to some example embodiments, the security of different semiconductor devices 110 may be enhanced and secured even when the authentication program 121 is hijacked, and threats from computing devices 120 running the hijacked authentication program 121 may be removed and limited.
Referring to
For Secure JTAG authentication in environments in which communication is restricted, the computing device 120 may receive, from the authentication server 130, temporary authentication information TAI on the semiconductor device 110 that is a device with which the computing device 120 is to communicate, and may embed the temporary authentication information TAI therein (S150).
In some example embodiments, communication between the computing device 120 and the authentication server 130 may be impossible, not possible, or reduced. In some example embodiments, when communication between the computing device 120 and the authentication server 130 may not be possible or when communication is reduced, the computing device 120 may embed, into the authentication program 121, temporary authentication information TAI on each of semiconductor devices 110.
Referring to
According to some example embodiments, security is enhanced by embedding temporary authentication information in an environment in which it is difficult for the authentication server 130 and the authentication program 121 to communicate with each other during a Secure JTAG authentication operation.
Referring to
The memory controller 111 may verify a temporary digital signature SIG_t, based on the verified public key PK and a digital signature algorithm (S320). For example, the memory controller 111 may verify the temporary digital signature SIG_t according to the digital signature algorithm using the value of the verified public key PK to check whether values of a temporary token TOKEN_t and a temporary public key PK_t are valid. In some example embodiments, the digital signature algorithm may be one of an RSA encryption algorithm, an ECDSA, and PQC, but example embodiments are not limited thereto. In operation S320, when the temporary digital signature SIG_t is invalid, the values of the temporary token TOKEN_t and the temporary public key PK_t are invalid. Thus, the debug authentication protocol stops and the memory controller 111 may reject the Secure JTAG authentication. In operation S320, when the temporary digital signature SIG_t is valid, the values of the temporary token TOKEN_t and the temporary public key PK_t are valid, and thus, operation S330 is performed.
The memory controller 111 may determine, based on token history information and the temporary token TOKEN_t, whether to use the temporary public key PK_t that is currently received (S330). For example, the memory controller 111 may check the remaining number of uses of the currently received temporary token TOKEN_t by referring to a token history of token history information stored in the non-volatile memory 112. In some example embodiments, when the remaining number of uses is not zero, the memory controller 111 may determine to use the currently received temporary public key PK_t. In some example embodiments, when the remaining number of uses is zero, the memory controller 111 may determine not to use the currently received temporary public key PK_t and reject the Secure JTAG authentication, and the debug authentication protocol may stop.
Referring to
The token history information TOKEN_history may include information about stored tokens and information about a use count USE COUNT indicating the current number of times of use of each token. The information about stored tokens may include, for example, a device identifier DEVICE ID, a maximum count MAX COUNT, and a token identifier TOKEN ID. The maximum count MAX COUNT may refer to the maximum number of times each token may be used in a device. For example, the first token, the second token, and the third token are stored in the non-volatile memory 112, and thus, the device identifiers DEVICE ID of the first token, the second token, and the third token may be the same (for example, ‘1’). The maximum counts MAX COUNT of the first token, second token, and third token may be ‘5’, ‘3’, and ‘2’, respectively. The token identifiers TOKEN ID of the first token, second token, and third token may be ‘AAAAA’, ‘BBBBBB’, and ‘CCCCCC’, respectively.
In some example embodiments, a temporary token having the same identifier as the identifier of any one of the tokens stored in the token history information TOKEN_history may be provided to the semiconductor device 110.
In some example embodiments, the memory controller 111 may check whether the use count USE COUNT of a corresponding token exceeds the maximum count MAX COUNT of the corresponding token, and based on results of the checking, the memory controller 111 may perform an authentication process through a Secure JTAG public key cryptography-based challenge-response protocol using a temporary public key PK_t or may reject a Secure JTAG authentication. The semiconductor device 110 protects the token history information TOKEN_history to use the token history information TOKEN_history when verifying the number of times a temporary public key PK_t has been used. For example, the memory controller 111 may encrypt the token history information TOKEN_history to prevent attackers from understanding or modifying the token history information TOKEN_history and may apply a restriction method to the token history information TOKEN_history to prevent attackers from abusing the token history information TOKEN_history, even when the token history information TOKEN_history is modified.
According to some example embodiments, even when the authentication program 121 for Secure JTAG containing secret information is stolen in a situation in which the computing device 120 is unable to access the authentication server 130, the security of the semiconductor device 110 may be guaranteed.
Referring to
The memory controller 111 may search token history information TOKEN_history for a token corresponding to the first temporary token TOKEN_t_1 by using the token identifier TOKEN ID of the first temporary token TOKEN_t_1. For example, because a token identifier TOKEN ID of a second token stored at an address 1 of the token history information TOKEN_history is the same as the token identifier TOKEN ID of the first temporary token TOKEN_t_1, the second token stored at the address 1 of the token history information TOKEN_history may be found.
The memory controller 111 may determine whether a use count USE COUNT of the found token is less than a maximum count MAX COUNT of the found token. Alternatively, in some example embodiments, the memory controller 111 may determine whether the use count USE COUNT of the found token is equal to the maximum count MAX COUNT of the found token. For example, the use count USE COUNT of the second token may be equal to the maximum count MAX COUNT of the second token. In some example embodiments, the memory controller 111 may reject a Secure JTAG authentication.
Referring to
Referring to
Unlike in the example embodiments shown in
According to some example embodiments, the security of the semiconductor device 110 may be enhanced, and resources of the non-volatile memory 112 may be saved.
Referring to
In some example embodiments, operation S2000 may include operation S310, operation S320, and operation S330.
Referring to
The system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b. Alternatively or additionally, in some example embodiments, the system 1000 may include at least one of an image capturing device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supplying device 1470, and a connecting interface 1480.
The main processor 1100 may control the operations of the system 1000. Alternatively or additionally, in some example embodiments, the main processor 1100 may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, and/or an application processor.
The main processor 1100 may include at least one central processing unit (CPU) core 1110 and further include a controller 1120 configured to control the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. In some example embodiments, the main processor 1100 may further include an accelerator 1130, which may include a dedicated circuit for a high-speed data operation, such as, but not limited to, an artificial intelligence (AI) data operation. For example, the accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and/or be implemented as a chip that is physically separated from the other components of the main processor 1100.
In some example embodiments, the main processor 1100 may be corresponding to the computing device 120 of
The memories 1200a and 1200b may be used as main memory devices of the system 1000. Each of the memories 1200a and 1200b may include a volatile memory, such as, but not limited to, static random access memory (SRAM) and/or dynamic random access memory (DRAM), and/or a non-volatile memory, such as, but not limited to, a flash memory, phase-change RAM (PRAM), and/or resistive random access memory (RRAM). In some example embodiments, the memories 1200a and 1200b may be implemented in the same package as the main processor 1100.
The storage devices 1300a and 1300b may serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and may have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may respectively include storage controllers 1310a and 1310b and flash memories 1320a and 1320b and be configured to store data via the control of the storage controllers 1310a and 1310b. Although the flash memories 1320a and 1320b may include vertical NAND (V-NAND) flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) structure, the flash memories 1320a and 1320b may include other types of non-volatile memories (NVMs), such as PRAM and/or RRAM.
The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and be included in the system 1000 and/or implemented in the same package as the main processor 1100. Alternatively, or additionally, in some example embodiments, the storage devices 1300a and 1300b may have types of SSDs or memory cards and may be removably combined with other components of the system 1000 through an interface, such as a connecting interface 1480 that is described below. The storage devices 1300a and 1300b may be devices to which a standard protocol, such as, but not limited to, UFS, eMMC, NVMe, and the like may be applied, without being limited in this regard.
In some example embodiments, the storage devices 1300a and 1300b may be corresponding to the semiconductor device 110 of
The image capturing device 1410 may capture still images and/or moving images. The image capturing device 1410 may include, but not be limited to, a camera, a camcorder, and/or a webcam. The user input device 1420 may receive various types of data input by a user of the system 1000 and may include, but not be limited to, a touch pad, a keypad, a keyboard, a mouse, and a microphone. The sensor 1430 may detect various types of physical quantities, which may be obtained from the outside of the system 1000, and convert the detected physical quantities into electric signals. For example, the sensor 1430 may include, but not be limited to, a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor. The communication device 1440 may transmit and/or receive signals between other devices outside the system 1000, according to various communication protocols. The communication device 1440 may include, but not be limited to, an antenna, a transceiver, and/or a modem.
The display 1450 and the speaker 1460 may serve as output devices configured to respectively output visual information and auditory information to the user of the system 1000. The power supplying device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and/or an external power source and supply the converted power to each of components of the system 1000. The connecting interface 1480 may provide connection between the system 1000 and an external device, which may be connected to the system 1000 and capable of transmitting and/or receiving data to and/or from the system 1000. The connecting interface 1480 may be implemented by using various interface schemes, such as, but not limited to, ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, Fire Wire, a USB interface, a SD card interface, an MMC interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a CF card interface.
Referring to
The storage device 2200 may include storage media configured to store data in response to requests from the host 2100. For example, the storage device 2200 may include at least one of an SSD, an embedded memory, and a detachable external memory. When the storage device 2200 is the SSD, the storage device 2200 may be a device that conforms to an NVMe standard, for example. Alternatively, or additionally, in some example embodiments, when the storage device 2200 is an embedded memory or an external memory, the storage device 2200 may be a device that conforms to a UFS standard or an eMMC standard. Each of the host 2100 and the storage device 2200 may generate a packet according to an adopted standard protocol and transmit the packet.
When the NVM 2220 of the storage device 2200 may include a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. Alternatively, or additionally, in some example embodiments, the storage device 2200 may include various other types of non-volatile memories. For example, the storage device 2200 may include, but not be limited to, MRAM, spin-transfer torque MRAM (STT-MRAM), conductive bridging RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, and RRAM.
In some example embodiments, the storage device 2200 may be corresponding to the semiconductor device 110 of
According to some example embodiments, the host controller 2110 and the host memory 2120 may be implemented as separate semiconductor chips. Alternatively or additionally, in some example embodiments, the host controller 2110 and the host memory 2120 may be integrated into the same semiconductor chip. For example, the host controller 2110 may include any one of a plurality of modules included in an application processor. For another example, the application processor may be implemented as a System on Chip (SoC). Alternatively or additionally, in some example embodiments, the host memory 2120 may be an embedded memory included in the application processor or a non-volatile memory or a memory module, which may be outside the application processor.
The host controller 2110 may manage an operation of storing data (e.g., write data) of a buffer region of the host memory 2120 in the non-volatile memory 2220 and/or storing data (e.g., read data) of the non-volatile memory 2220 in the buffer region.
The storage controller 2210 may include a host interface 2211, a memory interface 2212, and a CPU 2213. In an embodiment, the storage controller 2210 may further include a flash translation layer (FTL) 2214, a packet manager 2215, a buffer memory 2216, an ECC engine 2217, and an advanced encryption standard (AES) engine 2218. The storage controller 2210 may further include a working memory (not shown) in which the FTL 2214 is loaded. The CPU 2213 may execute the FTL 2214 to control write and read operations on the NVM 2220.
The host interface 2211 may transmit, send, transfer and/or receive packets to and/or from the host 2100. A packet transmitted, transferred, or sent from the host 2100 to the host interface 2211 may include a command and/or data to be written the non-volatile memory 2220. A packet transmitted, transferred, or sent from the host interface 2211 to the host 2100 may include a response to the command and/or data read from the non-volatile memory 2220. The memory interface 2212 may transmit, transfer, or send data to be written to the non-volatile memory 2220 and/or receive data read from the non-volatile memory 2220. The memory interface 2212 may be configured to comply with one or more standard protocols, such as, but not limited to, Toggle and/or open NAND flash interface (ONFI).
The FTL 2214 may perform various functions, such as, but not limited to, an address mapping operation, a wear-leveling operation, and a garbage collection operation. The address mapping operation may refer to an operation of converting a logical address received from the host 2100 into a physical address used to physically store data in the non-volatile memory 2220. The wear-leveling operation may refer to a technique for preventing excessive deterioration of a specific block by allowing blocks of the non-volatile memory 2220 to be uniformly used. For example, the wear-leveling operation may be implemented using a firmware technique that balances erase counts of physical blocks. The garbage collection operation may refer to a technique for ensuring usable capacity in the non-volatile memory 2220 by erasing an existing block after copying valid data of the existing block to a new block.
The packet manager 2215 may generate a packet according to a protocol of an interface, which interfaces with the host 2100, and/or parse various types of information from the packet received from the host 2100. Alternatively, or additionally, in some example embodiments, the buffer memory 2216 may temporarily store data to be written to the NVM 2220 and/or data to be read from the NVM 2220. Although, in some example embodiments, the buffer memory 2216 may be a component included in the storage controllers 2210, the buffer memory 2216 may be outside the storage controllers 2210.
The ECC engine 2217 may perform error detection and correction operations on read data read from the NVM 2220. For example, the ECC engine 2217 may generate parity bits for write data to be written to the NVM 2220, and the generated parity bits may be stored in the NVM 2220 together with write data. During the reading of data from the NVM 2220, the ECC engine 2217 may correct an error in the read data by using the parity bits read from the NVM 2220 along with the read data, and output error-corrected read data.
The AES engine 2218 may perform, by using a symmetric-key algorithm, at least one of an encryption operation and a decryption operation on data input to the storage controllers 2210.
It is apparent to those skilled in the art that the example embodiments of the present inventive concepts may be modified or changed in various ways without departing from the scope or technical spirit of the inventive concept. Thus, such modifications or changes made within the scope of the following claims and equivalents thereof are included in the scope of the present inventive concepts.
While the present inventive concepts have been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0187516 | Dec 2023 | KR | national |
