Patent Application
20140226233
The field relates generally to storage devices, and more particularly to generation of write signals in storage devices.
Disk-based storage devices such as hard disk drives (HDDs) are commonly used to provide non-volatile data storage in a wide variety of different types of data processing systems.
In a typical HDD, data is recorded on tracks of a magnetic storage disk using a write signal comprising multiple write pulses. The write signal is generated by a write driver that is coupled to a write head of the HDD via a transmission line. In order to record a given data bit, the write driver generates a write pulse that transitions from a negative write current to a positive write current, or vice-versa.
However, writing data to the storage disk can be challenging when utilizing conventional write pulses, particularly at high data rates on the order of 1 Gigabit per second (Gb/s) or more. For example, impedance mismatches between the write driver, the transmission line and the write head often cause write pulse reflections that distort the desired shape of the write pulse waveform at the write head. Such impedance mismatches become significantly more pronounced at high data rates, and can adversely impact on-track recording performance in terms of recorded data fidelity as well as off-track recording performance due to issues such as adjacent track erasure and far track erasure. Similar problems can arise when writing data to other types of storage media.
In one embodiment, an HDD or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising a write pulse, and reflection compensation circuitry coupled to or otherwise associated with the write driver and configured to provide one or more reflection compensation pulses in the write pulse.
By way of example only, the reflection compensation circuitry may be configured to generate a given one of the reflection compensation pulses as a negative-going current pulse having a substantially zero steady-state current. The reflection compensation circuitry may be further configured to superimpose the given reflection compensation pulse on the write pulse by combining the negative-going current pulse having the substantially zero steady-state current with a positive steady-state write current of the write pulse so as to produce a modified write pulse having the negative-going current pulse superimposed on the positive steady-state write current.
Other embodiments of the invention include but are not limited to methods, apparatus, systems, processing devices, integrated circuits and computer-readable storage media having computer program code embodied therein.
Embodiments of the invention will be illustrated herein in conjunction with exemplary disk-based storage devices, write drivers and associated reflection compensation circuitry. It should be understood, however, that these and other embodiments of the invention are more generally applicable to any storage device in which improved recording performance is desired. Additional embodiments may be implemented using components other than those specifically shown and described in conjunction with the illustrative embodiments.
Data is read from and written to the storage disk 110 via a read/write head 130 that is mounted on a positioning arm 140. It is to be appreciated that the head 130 is shown only generally in
The term “control circuitry” as used herein is therefore intended to be broadly construed so as to encompass, by way of example and without limitation, drive electronics, signal processing electronics, and associated processing and memory circuitry, and may encompass additional or alternative elements utilized to control positioning of a read/write head relative to a storage surface of a storage disk in a storage device. A connector 160 is used to connect the storage device 100 to a host computer or other related processing device.
It is to be appreciated that, although
A given read/write head as that term is broadly used herein may be implemented in the form of a combination of separate read and write heads. More particularly, the term “read/write” as used herein is intended to be construed broadly as read and/or write, such that a read/write head may comprise a read head only, a write head only, a single head used for both reading and writing, or a combination of separate read and write heads. A given read/write head such as read/write head 130 may therefore include both a read head and a write head. Such heads may comprise, for example, write heads with wrap-around or side-shielded main poles, or any other types of heads suitable for recording and/or reading data on a storage disk. Read/write head 130 when performing write operations may be referred to herein as simply a write head.
Also, the storage device 100 as illustrated in
The outer zones of the storage disk 110 provide a higher data transfer rate than the inner zones. This is in part due to the fact that the storage disk in the present embodiment, once accelerated to rotate at operational speed, spins at a constant angular or radial speed regardless of the positioning of the read/write head, but the tracks of the inner zones have smaller circumference than those of the outer zones. Thus, when the read/write head is positioned over one of the tracks of an outer zone, it covers a greater linear distance along the disk surface for a given 360° turn of the storage disk than when it is positioned over one of the tracks of an inner zone. Such an arrangement is referred to as having constant angular velocity (CAV), since each 360° turn of the storage disk takes the same amount of time, although it should be understood that CAV operation is not a requirement of embodiments of the invention.
Areal and linear bit densities are generally constant across the entire storage surface of the storage disk 110, which results in higher data transfer rates at the outer zones. Accordingly, the outermost annular zone 230-0 of the storage disk has a higher average data transfer rate than the innermost annular zone 230-M of the storage disk. The average data transfer rates may differ between the innermost and outermost annular zones in a given embodiment by more than a factor of two. As one example embodiment, provided by way of illustration only, the outermost annular zone may have a data transfer rate of approximately 2.3 Gb/s, while the innermost annular zone has a data transfer rate of approximately 1.0 Gb/s. In such an implementation, the HDD may more particularly have a total storage capacity of 500 Gigabytes (GB) and a spindle speed of 7200 revolutions per minute (RPM), with the data transfer rates ranging, as noted above, from about 2.3 Gb/s for the outermost zone to about 1.0 Gb/s for the innermost zone.
The storage disk 110 may be assumed to include a timing pattern formed on its storage surface. Such a timing pattern may comprise one or more sets of servo address marks (SAMs) or other types of servo marks formed in particular sectors in a conventional manner.
The particular data transfer rates and other features referred to in the embodiment described above are presented for purposes of illustration only, and should not be construed as limiting in any way. A wide variety of other data transfer rates and storage disk configurations may be used in other embodiments.
Embodiments of the invention will be described below in conjunction with
The bus 306 may comprise, for example, one or more interconnect fabrics. Such fabrics may be implemented in the present embodiment as Advanced eXtensible Interface (AXI) fabrics, described in greater detail in, for example, the Advanced Microcontroller Bus Architecture (AMBA) AXI v2.0 Specification, which is incorporated by reference herein. The bus may also be used to support communications between other system components, such as between the SOC 304 and the preamplifier 308. It should be understood that AXI interconnects are not required, and that a wide variety of other types of bus configurations may be used in embodiments of the invention.
The processor 300, memory 302, SOC 304 and preamplifier 308 may be viewed as collectively comprising one possible example of “control circuitry” as that term is utilized herein. Numerous alternative arrangements of control circuitry may be used in other embodiments, and such arrangements may include only a subset of the components 300, 302, 304 and 308, or portions of one or more of these components. For example, the SOC 304 itself may be viewed as an example of “control circuitry.” The control circuitry of the storage device 100 in the embodiment as shown in
It should be noted that certain operations of the SOC 304 in the storage device 100 of
The external memory 302 may comprise electronic memory such as random access memory (RAM) or read-only memory (ROM), in any combination. In the present embodiment, it is assumed without limitation that the external memory 302 is implemented at least in part as a double data rate (DDR) synchronous dynamic RAM (SDRAM), although a wide variety of other types of memory may be used in other embodiments. The memory 302 is an example of what is more generally referred to herein as a “computer-readable storage medium.” Such a medium may also be writable.
Although the SOC 304 in the present embodiment is assumed to be implemented on a single integrated circuit, that integrated circuit may further comprise portions of the processor 300, memory 302, bus 306 and preamplifier 308. Alternatively, portions of the processor 300, memory 302, bus 306 and preamplifier 308 may be implemented at least in part in the form of one or more additional integrated circuits, such as otherwise conventional integrated circuits designed for use in an HDD and suitably modified to implement reflection compensation circuitry for providing one or more reflection compensation pulses for combination with respective write pulses of a write signal as disclosed herein.
An example of an SOC integrated circuit that may be modified for use in embodiments of the invention is disclosed in U.S. Pat. No. 7,872,825, entitled “Data Storage Drive with Reduced Power Consumption,” which is commonly assigned herewith and incorporated by reference herein.
Other types of integrated circuits that may be used to implement processor, memory or other storage device components of a given embodiment include, for example, a microprocessor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other integrated circuit device.
In an embodiment comprising an integrated circuit implementation, multiple integrated circuit dies may be formed in a repeated pattern on a surface of a wafer. Each such die may include reflection compensation circuitry as described herein, and may include other structures or circuits. The dies are cut or diced from the wafer, then packaged as integrated circuits. One skilled in the art would know how to dice wafers and package dies to produce packaged integrated circuits. Integrated circuits so manufactured are considered embodiments of the invention.
Although shown as part of the storage device 100 in the present embodiment, one or both of the processor 300 and memory 302 may be implemented at least in part within an associated processing device, such as a host computer or server in which the storage device is installed. Accordingly, elements 300 and 302 in the
Referring now more particularly to the preamplifier 308 of the storage device 100, the preamplifier in this embodiment comprises reflection compensation circuitry 320 and associated write drivers 322. The reflection compensation circuitry 320 comprises a delay control module 324 and a compensation pulse driver 326. The reflection compensation circuitry 320 is configured to provide one or more reflection compensation pulses in each of a plurality of write pulses of a write signal generated by a given one of the write drivers 322. Although multiple write drivers are present in this embodiment, other embodiments may include only a single write driver.
A given write driver 322 in the present embodiment may comprise multiple distinct data paths, such as a high side data path and a low side data path, although different numbers of data paths may be used in other embodiments. It should be noted in this regard that the term “data path” as used herein is intended to be broadly construed, so as to encompass, for example, CMOS circuitry or other types of circuitry through which a data signal passes in preamplifier 308 or another storage device component.
Also, the term “write driver” is intended to encompass any type of driver circuitry that may be used to deliver or otherwise provide one or more write signals to the write head of the storage device 100. By way of example, a given one of the write drivers 322 may comprise an X side and a Y side, each comprising both high side and low side drivers, where the X and Y sides are driven on opposite write cycles. Numerous alternative arrangements of circuitry are possible in other write driver embodiments.
Although illustratively shown in
In each of these figures, a single write pulse is shown, suitable for use in writing a single data bit to the storage medium 110, and the write pulse current in milliamperes (mA) is plotted as a function of time in nanoseconds (ns).
A given exemplary write pulse of a write signal as illustrated in
Referring initially to
The inclusion of the superimposed reflection compensation pulse 504 allows mismatch-related reflections of the write pulse to be at least partially canceled out, thereby reducing distortion of the desired write pulse waveform and improving on-track and off-track recording performance, particularly at high data rates. As will be appreciated by those skilled in the art, the parameters of the reflection compensation pulse will be selected based on implementation-specific factors such as, for example, a length and impedance of a transmission line that couples a given write driver to a write head, the output impedance of the write driver and the input impedance of the write head.
The reflection compensation pulse 504 in
More particularly, in the present embodiment, the reflection compensation pulse is a negative-going current pulse having a substantially zero steady-state current. The reflection compensation pulse is superimposed on the write pulse by combining the negative-going current pulse having the substantially zero steady-state current with a positive steady-state write current Iw of the write pulse so as to produce a modified write pulse having the negative-going current pulse superimposed on the positive steady-state write current.
In the
It should also be understood that
The given write driver 322-1 may be viewed as representing only a portion of a high side or low side data path in an embodiment comprising multiple write data paths. At least a portion of each such data path may comprise separate steady-state and overshoot paths, which include respective circuitry blocks for steady-state and overshoot write pulse waveshaping. Thus, for example, write driver 322-1 may comprise separate steady-state and overshoot drivers, as would be appreciated by those skilled in the art. Also, the portion of reflection compensation circuitry 322 shown is implemented outside of the write driver 322-1 in this embodiment, but as noted above, in other embodiments may be implemented at least in part using circuitry that is internal to the write driver 322-1.
As shown in
The write signal generated by the write driver 322-1 is also applied as an input to the delay control module 324-1. The delay control module 324-1 is an example of what is more generally referred to herein as a “controllable delay element.” The compensation pulse driver 326-1 has an input coupled to an output of the delay control module 324-1 and an output coupled to a second input of the signal combiner 602-1. The delay control module 324-1 is configured to operate in conjunction with the compensation pulse driver 326-1 to establish a delay time of an initial transition of a given one of the reflection compensation pulses relative to an initial transition of the write pulse. For example, the established delay time in some implementations may be approximately twice the signal propagation time between the write driver 322-1 and the write head 130W.
The signal combiner 602-1 superimposes the given reflection compensation pulse on a corresponding write pulse of the write signal generated by the write driver, and supplies the resulting modified write pulse to write head 130W via a transmission line 604-1. The transmission line is also referred to in the figure as a “T-line.” The modified write pulse is also referred to herein as a write pulse that is provided with one or more reflection compensation pulses. Such a write pulse as modified in the manner described so as to incorporate one or more reflection compensation pulses may be considered part of a write signal that is generated by a write driver for delivery to the write head 130W, as the term “write signal” is intended to be broadly construed herein.
The given reflection compensation pulse is also referred to in the context of
The output of the signal combiner 602-1 is coupled via a transmission line 604-1 to the write head 130W. As illustrated in
As a more particular example, the resistor R in the
For the exemplary R and C values given above, and assuming a steady-state current Iw of 50 mA, an OS amplitude of 50 mA, an OS duration of 0.1 ns, and main pulse rise and fall times of 0.1 and 0.05 ns, respectively, possible values for the RCP amplitude, RCP duration, RCP rise and fall times and RCP delay as illustrated in
The use of finite input impedance for the transmission line 604-1 as established by the resistor-capacitor circuitry 625 allows the reflection compensation pulse 608 to be generated at significantly lower amplitude than would otherwise be required and without a positive or negative steady-state component, thereby reducing the amount of power required to generate the reflection compensation pulse.
Referring again to
One or more of the embodiments of the invention provide significant improvements in disk-based storage devices as well as other types of storage devices. For example, by utilizing write signals having write pulses with superimposed reflection compensation pulses, mismatch-related reflections of the write pulse are at least partially canceled out. This can significantly reduce distortion of the desired write pulse waveform and thereby improve on-track and off-track recording performance, particularly at high data rates.
It is to be appreciated that the particular circuitry arrangements, write signal waveforms and control signal configurations shown in
As mentioned previously, the storage device configuration can be varied in other embodiments of the invention. For example, the storage device may comprise a hybrid HDD which includes a flash memory in addition to one or more storage disks.
It should also be understood that the particular storage disk configuration and recording mechanism can be varied in other embodiments of the invention. For example, a variety of recording techniques including shingled magnetic recording (SMR), bit-patterned media (BPM), heat-assisted magnetic recording (HAMR) and microwave-assisted magnetic recording (MAMR) can be used in one or more embodiments of the invention. Accordingly, embodiments of the invention are not limited with regard to the particular types of storage media that are used in a given storage device.
Multiple storage devices 100-1 through 100-N possibly of various different types may be incorporated into a virtual storage system 800 as illustrated in
Again, it should be emphasized that the above-described embodiments of the invention are intended to be illustrative only. For example, other embodiments can use different types and arrangements of storage media, write heads, control circuitry, preamplifiers, write drivers, reflection compensation circuitry and other storage device elements for implementing the described write signal generation functionality. Also, the particular manner in which one or more reflection compensation pulses are superimposed on or otherwise provided in each of a plurality of write pulses, as well as the various parameters and waveforms used for the reflection compensation pulses, may be varied in other embodiments. These and numerous other alternative embodiments within the scope of the following claims will be apparent to those skilled in the art.
