Patent Application
20090275291
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-118998, filed on Apr. 30, 2008, the entire contents of which are incorporated herein by reference.
1. Field
The present invention relates to a storage device.
2. Description of the Related Art
In a conventional technology, to test an interface of a storage device, the storage device is connected to a host for test (or a chip for test having functions equivalent to those of a host for test, etc.), and data is actually transmitted and received between the host and the storage device (see, for example,
There are other conventional technologies for such a test. With one conventional technology, a switching unit that connects or disconnects a transmitting unit and a receiving unit of an interface is provided in a device and is controlled to perform a test. With another conventional technology, a circuit for testing is provided inside an interface to connect the transmitting unit and the receiving unit together to perform a test. With still another conventional technology, an interface of a display is tested (see, for example, Japanese Laid-open Patent Publication Nos. H6-28272, S62-66356, 2001-282569, and H7-121397).
With the conventional technologies explained above, it is not easy to test the interface of a storage device.
For example, by connecting the storage device to a host for test, the interface cannot be tested without a host for test. Besides, if the speed of the interface increases, for example, a test cannot be performed with a previous-generation host, and a next-generation host is required. This results in increased cost.
It is an object of the present invention to at least partially solve the problems in the conventional technology.
According to an aspect of an embodiment, a storage device includes: a transmission controller that controls, in response to a test instruction to operate in test mode for testing whether data is normally transmitted and received when a signal is output from a transmission interface and input to a reception interface, transmission of test data set for the test mode according to a protocol set for the test mode, the transmission interface for data transmission and the reception interface for data reception that, when electrically connected to the transmission interface, receives the signal from the transmission interface being interfaces connected to an external device; a reception controller that controls, in response to the test instruction, reception of the test data transmitted under control of the transmission controller according to the protocol set for the test mode; and a verifying unit that verifies whether the test data transmitted under control of the transmission controller matches the test data received under control of the reception controller.
Additional objects and advantages of the invention (embodiment) will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Exemplary embodiments of the present invention are described in detail below with reference to the accompanying drawings.
First, the principle of a storage device according to a first embodiment is explained.
In the storage device according to the first embodiment, Serial Advance Technology Attachment (SATA) is assumed, which is a high-speed serial interface, as an example of the interface. The storage device according to the first embodiment includes, as depicted in
Meanwhile, as depicted in
Under such connection, the storage device according to the first embodiment conducts a test to check whether data transmission and reception is correctly performed. Specifically, upon receiving an instruction for operation in test mode, the storage device controls transmission of test data set for test mode according to a protocol set for the test mode. The reason why transmission is controlled according to the protocol set for the test mode will be explained in detail further below.
Upon receiving an instruction for operation in the test mode, the storage device controls reception of the transmitted test data according to the protocol set for the test mode. The reason why reception is controlled according to the protocol set for the test mode will be explained in detail further below.
In this manner, as depicted in
In this manner, in the storage device according to the first embodiment, the interface is tested by using the scheme of directly connecting the reception interface and the transmission interface together through electrical connection with a cable, for example. With this, the interface can be easily tested.
As described below, it is assumed in the first embodiment that all data patterns of the test data are stored inside of the controller and data comparison is also performed inside of the controller. However, this is not meant to be restrictive. As described in detail later in a second embodiment, for the storage device, a configuration can be selected as appropriate such that test data stored in any one of the controller, the buffer, and the storage medium is transmitted from the transmission interface and the received test data is compared in any one of the controller, the buffer, and the storage medium.
As explained above, in the storage device according to the first embodiment, test data is transmitted and received according to the protocol set for the test mode. Specifically, in the storage device according to the first embodiment, an initialization process and a data transmission and reception process for the test mode are set. With reference to
First, initialization of the Serial ATA is explained. In the Serial ATA, at the time of power-up, the storage device (device) performs a process “OOB Sequence” of initializing a Phy layer with a host.
Specifically, as depicted in
In either one of
Meanwhile, when the transmitting unit and the receiving unit are directly connected together through electrical connection with a cable, for example, as in the storage device according to the first embodiment, the storage device cannot correctly complete “OOB Sequence”. The reason is that when the transmitting unit of the storage device transmits “COMINIT”, as depicted in
For this reason, the storage device according to the first embodiment provides test mode inside of the Phy layer, thereby omitting (bypassing) “OOB Sequence” to make a transition to “Phy ready state”.
Next, Serial ATA data transmission and reception is explained. In Serial ATA, at the time of normal data transmission and reception, the storage device or host performs a process depicted in
Specifically explained, with reference to
Although not shown in
The data transmission and reception process depicted in
First, the process on the data transmission side is explained with reference to
Subsequently, the transmitting unit determines whether “R_RDY” has been received (Step S103). When it is determined that “R_RDY” has not been received (No at Step S103), the process control returns to Step S102. On the other hand, when it is determined that “R_RDY” has been received (Yes at Step S103), the transmitting unit transmits “SOF” (Step S104), and then transmits “DATA” (Step S105).
The transmitting unit then transmits “CRC” (Step S106), transmits “EOF” (Step S107), and then transmits “WTRM” (Step S108).
Subsequently, the transmitting unit determines whether “R_OK” has been received (Step S109). When it is determined that “R_OK” has not been received (No at Step S109), the process control returns to Step S108. On the other hand, when it is determined that “R_OK” has been received (Yes at Step S109), the transmitting unit normally ends the process.
Next, the process on the data reception side is explained with reference to
When it is determined that reception is ready (Yes at Step S202), the receiving unit transmits “R_RDY” (Step S203). The receiving unit then determines whether “SOF” has been received (Step S204). When it is determined that “SOF” has not been received (No at Step S204), the process control returns to Step S203.
On the other hand, when it is determined that “SOF” has been received (Yes at Step S204), the receiving unit acquires “DATA” (Step S205). The receiving unit then determines whether “EOF” has been received (Step S206).
When it is determined that “EOF” has been received (Yes at Step S206), the receiving unit verifies “CRC” (Step S207), transmits “R_OK” (Step S208), and then normally ends the process.
Meanwhile, when the transmitting unit and the receiving unit are directly connected together through electrical connection with a cable, for example, as in the storage device according to the first embodiment (when data is transmitted and received in a self-contained manner), the storage device cannot transmit and receive data through a normal process. The reason is that, when data is transmitted and received in a self-contained manner, the storage device becomes a data transmission side and a data reception side by itself. Thus, for example, as depicted in
For this reason, the storage device according to the first embodiment is provided with test mode, thereby allowing data transmission and reception by itself. In the test mode, as depicted in
However, since the storage device according to the first embodiment neither performs a handshake between “X_RDY” and “R_RDY” in the test mode nor transmits “SOF”, the storage device cannot determine a “DATA” intake start position when receiving “DATA”. To get around this, in one possible scheme, the intake start position is determined by setting the head data as a specific data pattern, but flexibility of the test pattern is decreased. To solve this problem, the storage device according to the first embodiment performs a verifying process as will be explained in detail later.
Next, the configuration of the storage device according to the first embodiment is explained with reference to
As depicted in
The controller 20 includes, as depicted in
The interface-protocol controller 21 controls an interface protocol with the host. Specifically, at the time of reception of write data, the interface-protocol controller 21 transmits data received from the host to the buffer controller 22. At the time of transmission of read data, the interface-protocol controller 21 transmits data received from the buffer controller 22 to the host.
Upon receiving an instruction for operation in the test mode, the interface-protocol controller 21 according to the first embodiment controls transmission of test data set for the test mode according to a protocol set for the test mode. Specifically, the interface-protocol controller 21 transmits test data stored in an internal memory at an arbitrary location inside of the controller 20 according to the protocol set for the test mode. Upon receiving an instruction, the interface-protocol controller 21 controls reception of the transmitted test data according to the protocol set for the test mode.
The buffer controller 22 controls read and write of data stored in the buffer 30. Specifically, at the time of reception of write data, the buffer controller 22 once writes data received from the interface-protocol controller 21 in the buffer 30, reads the data at an appropriate timing from the buffer 30, and then transmits the data to the disk-format controller 23. At the time of transmission of read data, the buffer controller 22 once writes data received from the disk-format controller 23, reads the data at an appropriate timing from the buffer 30, and then transmits the data to the interface-protocol controller 21.
The size of the buffer 30 is generally 16 megabytes, which corresponds to 32 kilo-sectors with 512 bytes being as one sector (16×1024×1024/512=32768).
The disk-format controller 23 controls read and write of data stored in the storage medium 40. Specifically, at the time of reception of write data, the disk-format controller 23 transmits data received from the buffer controller 22 to the RDC 50. At the time of transmission of read data, the disk-format controller 23 transmits data received from the RDC 50 to the buffer controller 22.
The ECC calculator 24 generates and verifies ECC for preventing data error (data corruption) stored in the storage medium 40. Specifically, at the time of reception of write data, the ECC calculator 24 generates ECC code based on data received from the disk-format controller 23. The generated ECC code is stored in the storage medium 40 via the disk-format controller 23. At the time of transmission of read data, the ECC calculator 24 receives data and ECC code from the disk-format controller 23. Furthermore, the ECC calculator 24 calculates ECC code for the received data, compares the calculated ECC code and the received ECC code (stored in the storage medium 40 at the time of write) with each other, and then corrects the data as required.
The RDC 50 includes a write-system circuit and a read-system circuit. Specifically, the RDC 50 (write system) encodes data received from the disk-format controller 23 to code suitable for magnetic storage (Run-Length Limited Coding: RLL), and corrects interruption between bits occurring on the storage medium 40. The RDC 50 (read system) converts a read signal received from the HDIC 60 to a digital value for decoding through analog-digital conversion and Partial Response Maximum Likelihood (PRML) signal processing technology.
The HDIC 60 includes a write-system circuit and a read-system circuit. Specifically, the HDIC 60 (write system) converts “1” or “0” of a digital signal in a current direction so as to write data in the storage medium 40, and then causes the conversion result to a write head. The HDIC 60 (read system) amplifies (approximately 100-fold) a read signal (approximately 1 millivolt) converted by a read head to an electrical signal.
The storage device 10 according to the first embodiment includes, as depicted in
As depicted in
Specifically, the storage device 10 according to the first embodiment has arbitrary test patterns stored in the internal register 21d inside of the controller 20. The test-pattern length is restricted by the size of the internal register 21d. Here, 8 DWord (1 DWord=32 bits) is assumed.
The storage device 10 according to the first embodiment stores in an arbitrary location of the controller 20 (for example, the internal memory 21f) repeated data with the same patterns as the test patterns stored in the internal register 21d for one sector (128 DWords). The storage device 10 is set so as to repeatedly transmit data from the location in the controller 20 where data with the same patterns as the test patterns is stored. At this time, the data length to be transmitted from the controller 20 may be any number of sectors as long as only the sectors storing the test patterns are transmitted. Being set so at to repeatedly transmit data, the storage device 10 can increase accuracy in data comparison by the comparator 21e.
Furthermore, in the storage device 10 according to the first embodiment, as depicted in
The comparator 21e verifies whether the transmitted test data is consistent with or matches the received test data. Specifically, the comparator 21e compares the test data stored in the internal register 21d and the test data received in the transport layer 21c with each other to verify whether they match.
The operation of the comparator 21e is described in detail below with reference to
For example, the comparator 21e verifies consistency of the test data through the process depicted in
The data coming next to “Data0” is “Data1”. Therefore, after receiving “Data0”, the comparator 21e waits for reception of “Data1”. Then, when receiving “Data1”, the comparator 21e causes the state to make a transition from “UNLOCK01” to “UNLOCK02”, and then waits for reception of “Data2”. On the other hand, when the data received next is not “Data1”, the comparator 21e causes the state to make a transition from “UNLOCK01” to UNLOCK00” as depicted in
Here, there may be two reasons why “Data1” cannot be received (reasons for a state transition from “UNLOCK01” to “UNLOCK00”). One reason is that “Data1” has not been correctly transmitted and received. The other reason is that a state transition of “UNLOCK00” to “UNLOCK01” erroneously occurs due to influences, such as noise, to begin with. Since the latter reason is possible, the comparator 21e does not leave an error log at this point in time, as depicted in
Meanwhile, the comparator 21e repeats the process explained above and, when the received data is changed in two cycles such that “Data0”→“Data1”→ . . . →“Data7”→“Data0”→“Data1”→ . . . →“Data7”, causes the state to make a transition to “LOCK”. In this manner, the comparator 21e in the first embodiment does not cause the state to make a transition to “LOCK” unless performing comparison on the received data in two cycles. With this, accuracy in data comparison can be increased. That is, the comparator 21e in the first embodiment can reduce the possibility of erroneously determining by chance, although the test data has not been transmitted, that the test data has been correctly received due to influences, such as noise, to almost zero. This is because it is thought to be unlikely to erroneously detect by chance that data of any test pattern has been received consecutively for 16 DWords.
After the state becomes “LOCK”, the comparator 21e determines a test error when the reception data becomes a pattern other than “Data0”→“Data1”→ . . . →“Data7”, and leaves an error log, as depicted in
In this manner, upon completion of the test, when the state is “LOCK” and no error log is present, the comparator 21e determines that the test has been successful. On the other hand, upon completion of the test, when the state is “UNLOCK” or an error log is present, the comparator 21e determines that the test has failed.
As described above, according to the first embodiment, when the reception I/F and the transmission I/F are electrically connected together through a cable, for example, in response to an instruction for test mode, transmission of test data as well as reception of the transmitted test data is controlled according to a protocol set for the test mode. The comparator verifies whether the transmitted test data matches the received test data. Thus, a test on the interface unit can be easily performed.
Modifications of the first embodiment are described below with reference to
According to the first embodiment, the storage device is configured to store all data patterns of the test data in the controller and performs data comparison by the comparator also in the controller. Besides, the storage device is assumed to have a memory with a size sufficient to store all data patterns in the controller (the internal memory 21f is sufficiently large). However, this is by way of example only and not limiting. For example, the storage device may not necessarily have a memory in the controller that is sufficiently large to store all data patterns of the test data. In this case, as depicted in
The storage device may be configured to not only perform data comparison in the controller but also perform data comparison in the buffer. In this case, the storage device controls transmission of the test data stored in the controller and also controls reception of the test data to the buffer. That is, for example, the storage device is set in a manner such that, after data comparison is performed by the comparator in the controller (after determining whether the test has been successful or failed), the storage device transmits the data to the buffer and writes the data in the buffer. Then, the storage device additionally performs data comparison on the data on the buffer. For example,
Further, the storage device may be configured to not only perform data comparison in the controller but also perform data comparison on the storage medium. In this case, the storage device controls transmission of the test data stored in the controller and also controls reception of the test data to the storage medium. That is, for example, the storage device is set in a manner such that, after data comparison is performed by the comparator in the controller (after determining whether the test has been successful or failed), the storage device transmits the data to the storage medium and writes the data in the storage medium. Then, the storage device additionally performs data comparison on the data on the storage medium. For example,
According to the first embodiment, the storage device is configured to store all data patterns of the test data in the controller and perform data comparison by the comparator also in the controller. However, this is by way of example only and not limiting. That is, the storage device may control transmission of the test data stored in the buffer and may also control reception of the test data to the buffer. For example, as depicted in
Still further, the storage device may control transmission of the test data stored in the buffer and may also control reception of the test data at the controller. For example, as depicted in
Still further, the storage device may control transmission of the test data stored in the buffer and may also control reception of the test data to the storage medium. For example, as depicted in
According to the first embodiment, the storage device is configured to store all data patterns of the test data in the controller and perform data comparison by the comparator also in the controller. However, this is by way of example only and not limiting. That is, the storage device may control transmission of the test data stored in the storage medium and may also control reception of the test data to the storage medium. For example, as depicted in
Still further, the storage device may control transmission of the test data stored in the storage medium and may also control reception of the test data at the buffer. For example, as depicted in
Still further, the storage device may control transmission of the test data stored in the storage medium and may also control reception of the test data at the controller. For example, as depicted in
In the first embodiment, the reception I/F and the transmission I/F are described as being directly connected together through electrical connection with, for example, a cable; however, they may be directly connected together with a jig on a printed board.
Of the processes described above, all or part of the processes explained as being performed automatically can be performed manually, or all or part of the processes explained as being performed manually can be performed automatically with a known method. The processing procedures, the control procedures, specific names, and information including various data and parameters described above and illustrated in the drawings can be changed as required unless otherwise specified.
The constituent elements described above are functionally conceptual, and need not be physically configured as illustrated. In other words, the specific mode of dispersion and integration of the constituent elements is not limited to the ones illustrated in the drawings, and the constituent elements, as a whole or in part, can be divided or integrated either functionally or physically based on various types of loads or use conditions. All or any part of the processing functions performed by the devices can be realized by a CPU and a program analyzed and executed by the CPU, or can be realized as hardware by wired logic.
Still further, the test program explained in the embodiments can be distributed via a network, such as the Internet. The program can also be stored in a computer-readable storage medium, such as hard disk, flexible disk (FD), compact-disk read only memory (CD-ROM), magneto-optical disk (MO), and digital versatile disk (DVD), and read by the computer therefrom to be executed.
As set forth hereinabove, according to an embodiment, a test on an interface can be easily performed.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present invention(s) has(have) been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-118998 | Apr 2008 | JP | national |
