Patent Application
20240264871
The Non-Volatile Memory Express® (NVMe®) Specification describes a system for accesses to data storage systems through a Peripheral Component Interconnect Express (PCIe) port. NVMe® is described for example, in NVM Express® Base Specification, Revision 1.3c (2018), as well as predecessors, successors, and proprietary variations thereof, which are incorporated by reference in their entirety. NVMe® allows a host device to specify regions of storage as separate namespaces. A namespace can be an addressable domain in a non-volatile memory having a selected number of storage blocks that have been formatted for block access. A namespace can include an addressable portion of a media in a solid state drive (SSD), or a multi-device memory space that spans multiple SSDs or other data storage devices. A namespace ID (NSID) can be a unique identifier for an associated namespace. A host device can access a particular non-volatile memory by specifying an NSID, a controller ID and an associated logical address for the block or blocks (e.g., logical block addresses (LBAs)).
Distributed block storage systems provide block device functionality to applications by presenting logical block devices that are stored in segments scattered across a large pool of remote storage devices. To use these logical block devices, applications determine the location of the segments to access. A computing platform can access a storage device using a fabric or network. Various storage protocols exist that enable access to storage devices using a network or fabric. For example, the Non-volatile Memory Express over Fabrics (NVMe-oF) specification is designed to enable access to remote NVMe compatible solid state drives (SSDs). For example, NVMe-oF is described at least in NVM Express Base Specification Revision 1.4 (2019). NVMe-oF compatible devices provide high performance NVMe storage drives to remote systems accessible over a network or fabric.
In 2018, a specification involving TCP transport (e.g., TP-8000 NVMe-oF™ TCP Transport Binding) was released for NVMe-oF. The purpose of T-8000 is to re-use existing networking infrastructure because legacy network interface controllers (NICs) and switches may not support remote direct memory access (RDMA) related protocols. With TCP transport support, re-use of existing network infrastructures can take place to ease the transition from iSCSI to NVMe-oF. Accordingly, there are several well-known transport layer protocols (e.g., RDMA, FC, and TCP) defined and supported by NVMe-oF. Developers can implement an NVMe-oF target or initiator using one or more different transports according to the specification to present an NVMe subsystem to remote hosts (initiators).
NVMe-oF over TCP can allow communications over the Internet whereas NVMe-oF over RDMA or FC are used in a data center and are limited in distance. However, in some cases, NVMe-oF over TCP can be slower with less determinate transit time. Software and hardware solutions can improve the NVMe-oF TCP transport performance in user space. Software solutions including leveraging user space TCP/IP stack, Data Plane Development Kit (DPDK), Storage Performance Development Kit (SPDK). Hardware offloading allows leveraging some offloading methods (e.g., field programmable gate arrays (FPGAs), or offloading operations which are conducted by CPU cores into an RDMA core) in order to save the CPU resources for other important tasks in order to improve the performance of applications.
Some data centers may have a target performance determinism, such as to meet contractual requirements or as a competitive differentiator. Providing the desired performance determinism (e.g., 99.99 percentile latency, with consistent throughput and central processor unit (CPU) utilization) for distributed systems applications in this environment may be a challenge. In many cases, the networking interface is one of the primary contributors to indeterminant performance (e.g., latency and tail latency), as it can become a bottleneck to application performance on a server. Tail latency can refer to a percentage of response times from a system, out of all of responses to the input/output (I/O) requests it serves, that take the longest in comparison to the bulk of its response times. Tail latency can refer to worst-case latencies seen at very low probability. Tail latency can also be measured from a cumulative probability distribution and it can have the lowest latency X such that latency >X occurs with probability no more than 10−15.
Various embodiments attempt to reduce latency and tail latency of NVMe-oF over TCP transactions using an application device queue feature available to a network interfaces and a busy polling scheme that reduces system calls and context switches. Various embodiments provide dedicated and isolated queues to store received packets from a network interface to user space or dedicated and isolated queues for packets that are to be transmitted by a network interface. Various embodiments use an Application Device Queue (ADQ) of a network interface as the isolated queues.
TCP connections on a configured traffic class (TC) can be allocated to isolated queues, and the queue identifier of a queue can be determined by the underlying kernel in a manner to achieve uniqueness of associated application. For example, if an application has allocated 4 queues, then the queue identifier (e.g., NAPI_ID) allocated by the kernel can be from 400, 401, 402, to 403 and the queue identifier for each connection can be randomly distributed by the kernel with fairness. For example, if there are 200 connections on 4 queues, and the kernel tries load balance among the 4 queues, 50 connections can be allocated for each queue identifier. However, connections can be allocated on a weighted basis so that connections are not evenly distributed. For example, connection placement may be weighted by factors such as service level agreement (SLA), workload of a polling group, activity or inactivity level of a core, and so forth. Connections with the same queue identifier on the socket can be distributed to the same polling group. A polling group can be executed on a dedicated CPU core (e.g., thread), thus the connections with the same queue identifier can be executed by the same CPU core to avoid resource contention among different CPUs handling the same connections. A polling group can detect events of all connections associated with the polling group. A polling mode can be applied that allows an application to poll for data in user space without switching to kernel mode to reduce context switches and system calls from kernel space to user space.
In some examples, after an NVMe-oF TCP target starts, a service listener operates on different service portals (e.g., TCP socket (e.g., <IP address, port>)) and when a new socket connection is added between a transmitter and a target, the connection can be allocated to a queue and queue identifier (e.g., NAPI_ID).
Various embodiments can be applied to any other storage applications based on SPDK acceleration framework, e.g., Internet Small Computer Systems Interface (iSCSI), Network File System (NFS). Various embodiments can be applied to memory pool transactions or any queueing of work requests (e.g., function as a service (FaaS)).
TCP transport acceptor 206 can be registered as a non-timer poller on a thread of core 0. In some examples, TCP transport acceptor 206 can be deployed on a thread on core 1. TCP transport acceptor 206 can be determined to run on a specified CPU core with a policy determined by an application. TCP transport acceptor 206 can listen on a portal (e.g., through spdk_sock_accept function) managed by the transport. When there is an incoming socket connection event, a new TCP connection with the socket information can be created (e.g., spdk_sock), and such connection can be managed by a dedicated non-timer poller (e.g., TCP transport polling group 204-0). For an incoming socket connection, the application can issue getsockopt system call for Linux to obtain hardware queue identifier information (e.g., NAPI_ID). TCP transport acceptor 206 can map connections which have the same queue identifier (e.g., NAPI_ID) to the same TCP transport polling group. Some embodiments use a round robin (RR) scheme to select a CPU core for processing a received packet, and sends an async message through event call to let the dedicated thread to add the TCP connection to its polling group. In some examples, weighted round robin allocation can be used using factors such as SLA, workload of a polling group, activity or inactivity level of a core, and so forth.
For n hardware queues allocated for an NVMe-oF target, supposing the NAPI_ID ranges from A, A+1, . . . , A+n−1, e.g., there are n different queues. When TCP transport acceptor 206 accepts a connection, it will check the NAPI_ID of the connections, and select a polling group which serves the same NAPI_ID connections. If no such polling group is found, then TCP transport acceptor 206 will choose a polling group that serves a lower number of connections, and mark the polling group that serves such NAPI_ID connection. ADQ can accelerate processing of multiple connections by the same CPU core by grouping connections together under the same NAPI_ID and avoid locking or stalling from contention for queue accesses (e.g., read or write).
The following is an example pseudo code to assign a priority to a connection and determine a queue identifier for the connection. A polling group can be assigned to a connection because the polling group is associated with the queue identifier.
Performing listenfd causes attention to <ipaddress, port> for a new file descriptor. Performing setsockopt sets a priority for this new file descriptor. Calling getsockopt obtains a queue identifier (NAPI_ID) on the “new_fd”. Different new_fd represent an active connection that can be used on this connection with read/write. If a connection is to be mapped to a polling group, then the file descriptor (fd) of the connection can be managed by a group polling. If the polling group is managed by eventfd mechanisms, then the fd will be added into the epoll group via epoll_ctl function. When the connection is ready to close, it will be removed from the epoll group also via epoll_ctl but with different parameters.
TCP transport acceptor 206 maintains a global mapping list maintains the mapping for the relationship between NAPI_ID and polling groups. The following shows a pseudo code representation for adding or removing a connection to a polling group.
In this example, TCP transport polling group 204-0 can execute on a thread of core 0 whereas TCP transport polling group 204-1 can execute on a thread of core 1. A thread can be an instance of a program executed by a CPU core. When a TCP connection is added to a corresponding TCP polling group, the socket owned by this connection is added to the socket polling group. For example, an epoll related operation (e.g., epoll_ctl) in Linux can be used to add the socket information into the socket polling group and a socket group polling can be used. For example, epoll_wait can be used to check the READ data event for a connection. In a polling group, if a read event is detected for a socket file descriptor (fd), the NVMe/TCP PDU (packet data unit) protocol parsing module can issue a read system call to read the contents on this fd in order to identify the PDU. For example, if a protocol parsing module determines a NVMe command is in a PDU (e.g., a PDU with NVME_TCP_PDU_TYPE_IC_REQ type in SPDK), then a protocol parsing module can conduct the NVMe command operation according to the NVMe-oF protocol. When a TCP connection is closed detected by the state of the owned socket, this connection is removed from the socket polling group and no longer be polled by the group.
A polling group can be executed on a dedicated CPU core. A polling group can manage the life cycle of all the TCP socket-based connections in a group, e.g., handle the I/Os on each socket-based connection including read or write I/Os; monitoring the data in event on each socket descriptor from the network; and terminating the socket for any error cases (e.g., the network connection is broken). In the same polling group, to detect incoming data on one or more connections, an epoll scheme can be used to detect a read event of the one or more connections to determine which connection is active or not. For example, epoll is a Linux kernel system call for a scalable I/O event notification mechanism. In some examples, instead of epoll, FreeBSD's kqueue can be used. TCP transport polling group 204-0 or 204-1 can delay interrupts to an application for received packets if the application is alert/alive due to invoking busy polling. For example, the following steps can take place during polling: 0) create an epoll event group via (epoll_create function in Linux) and 1) call epoll_wait function to determine which connection has incoming data.
For received packets, a driver copies packet to a host memory (e.g., direct memory access (DMA)), writes descriptor to host memory but during busy polling, the driver does not issue interrupts to an application and the application does not enter sleep state in busy polling. For example, the driver can defer interrupt enablement while application busy polls. An application can stay awake proactively busy polling queues to see if work has arrived. A polling mode allows an application polls for data and remain active in user space and not switch to kernel mode and not cause context switching. In some cases, an interrupt causes switch from user space to kernel space to handle interrupts, which causes context switch from user space to kernel space and disrupts application and reduces I/O processing speed.
An application can perform packet processing in connection with 3GPP Radio Access Network (RAN) and Core Network (CN), Transport Network (TN) from Broadband Forum and Internet Engineering Task Force (IETF), ITU-T (GSTR-TN5G), IEEE (NGFI 1914), and so forth. Packet processing can include using Network Function Virtualization (NFV), software-defined networking (SDN), virtualized network function (VNF), Evolved Packet Core (EPC), or 5G network slicing. Some example implementations of NFV are described in European Telecommunications Standards Institute (ETSI) specifications or Open Source NFV Management and Orchestration (MANO) from ETSI's Open Source Mano (OSM) group. VNF can include a service chain or sequence of virtualized tasks executed on generic configurable hardware such as firewalls, domain name system (DNS), caching or network address translation (NAT) and can run in virtual execution environments. VNFs can be linked together as a service chain. In some examples, EPC is a 3GPP-specified core architecture at least for Long Term Evolution (LTE) access. 5G network slicing can provide for multiplexing of virtualized and independent logical networks on the same physical network infrastructure.
A packet can include a header and payload. A header can be a media access control (MAC) source and destination addresses, EtherType, Internet Protocol (IP) source and destination addresses, IP protocol, Transmission Control Protocol (TCP) port numbers, virtual local area network (VLAN) or Multi-Protocol Label Switching (MPLS) tags.
To transmit responses to NVMe commands, for an NVMe-oF application on the target side, a polling group can: a) read the data on the connection and compose the related NVMe commands and cause the backend NVMe subsystems to execute those commands asynchronously; b) when the NVMe commands are finished by the backend NVMe subsystem, compose the response PDU according to the results of the NVMe commands, and use the write related operations to write the data on the socket connection.
According to various embodiments, an ADQ can be dedicated to a single polling group for an NVMe-oF communication using TCP by allocating connections to a polling group based on identifier (e.g., NAPI_ID). Applications can reduce the context switching to achieve lower latency of packet receipt using TCP as a transport layer. For example, for N queues and a queue is assigned a unique NAPI_ID, then all the NAPI_IDs compose a set containing N different NAPI_IDs. A thread running a polling group is allocated a subset of N different NAPI_IDs, so that a polling group exclusively uses a queue or queues for one or more NAPI_IDs and no other polling group accesses the queue or queues so that TCP connections having the same NAPI_IDs are processed by the same thread. An application can determine which hardware queues are allocated to a NAPI_ID through the attribute on Sock_FD (e.g., getsockopt with “SO_INCOMING_NAPI_ID” in Linux). In this example, polling groups 500-1 and 500-2 are shown. Polling group 500-1 can be allocated use of an ADQ whereas polling group 500-2 can be allocated use of two ADQs.
Before starting an application, socket init module 602 calls “setsockopt” POSIX API in Linux to set a priority on a listener socket to cause the storage application to use the configured isolated queue(s). Acceptor logic module 604 can obtain a NAPI_ID of the TCP connection through getsockopt (e.g., through SO_INCOMING_NAPI_ID in Linux if it is supported). The NAPI_ID can represent an assigned hardware queue for a TCP connection. For example, if the application uses a traffic class with 3 hardware queues, then the incoming TCP connections accepted by the listener socket have three different NAPI_IDs, e.g., 789, 790 and 791. These NAPI_IDs can be used by the TCP connection scheduler 606 to construct a NAPI_ID based scheduling. In some examples, TCP connection scheduler 606 can apply a round robin scheme to dispatch the connections fairly to threads without considering the NAPI_ID belonging to a TCP connection. In some examples, TCP connection scheduler 606 can apply a NAPI_ID based to schedule a connection by searching for an existing polling group that polls for that NAPI_ID. If such a polling group exists, TCP connection scheduler 606 identifies the I/O thread that executes this existing polling group and dispatches the connection to this thread. If there is no assigned I/O thread, TCP connection scheduler 606 identifies an I/O thread which has a least number of connections, and launches a new polling group to monitor the NAPI_ID on the identified thread. An I/O thread that executes a polling group can obtain “data in” indicators (received packets) by monitoring a queue in a network interface card (NIC) with ADQ or isolated queues. The ADQ or queue can be allocated to a particular NAPI_ID. The polling group can also conduct reads/writes on a connection in an asynchronous manner for data to be transmitted from a NIC with ADQ using an allocated queue. The polling group can apply epoll techniques to poll for I/O activity.
In some examples, for read operation handling, during a round, a connection can prepare at most one read task. Read operations for a Sock_FD can be merged and one system call made to submit the I/O (e.g., using io_submit via libaio engine or io_uring_submit via liburing engine). A group based I/O submission can save system call overhead. For example, if there are write operations on 32 connections, I/O writes on the connections can be collected and issued as one io_submit (e.g., using libaio library). In this manner, 31 system calls in a round can be avoided. When the I/O operations on read tasks are submitted, the kernel can be queried to provide I/Os.
In some examples, for a write operation handling, in a round, a connection can prepare at most one write task. Write operations for a Sock_FD can be merged and one system call made to submit the I/O (e.g., using io_submit via libaio engine or io_uring_submit via liburing engine). A group based I/O submission can save system call overhead. For example, if there are write operations on 64 connections, I/O writes on the connections can be collected and issued as one io_submit (e.g., using libaio library). In this manner, 63 system calls in a round can be avoided. When the I/O operations on write tasks are submitted, some functions (e.g., “io_uring_peek_cqe” in liburing library in Linux) can be called to query whether the kernel has completed the I/Os requested by the application in user space.
At 804, the storage application associates a queue with one or more connection(s). For example, the storage application can associate any new TCP connection with a queue identifier (e.g., NAPI_ID). In addition, any terminated socket connection can be removed from being associated with a queue identifier. One or more queues and corresponding queue identifiers can be allocated for use by connection(s).
At 806, a polling group is allocated for connection(s) associated with the same queue identifier. In some examples, a polling group can be executed on a dedicated CPU core that does not execute another polling group. In some examples, a polling group can use an epoll scheme to detect the I/O events for connections associated with the same queue identifier.
At 808, a network interface can allocate connections to dedicated one or more queues. For example, the network interface can apply traffic class (TC) filtering to map the application's TCP connections to the dedicated one or more queues.
At 810, the polling group polls for receipt of any packet or transmission of any packet by an application. A polling scheme can be applied where an application does not enter sleep state and the application polls for receipt of any new packet or transmission of any packet. A driver can defer interrupts while the application polls. The packets can be received in a one or more queues dedicated to the connection or provided for transmission using one or more queues dedicated to the connection. To transmit responses to NVMe commands, the polling group can compose a response PDU according to the results of the NVMe commands, and use the write related operations to write the data on the socket connection for transmission.
In one example, system 900 includes interface 912 coupled to processor 910, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem 920 or graphics interface components 940, or accelerators 942. Interface 912 represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface 940 interfaces to graphics components for providing a visual display to a user of system 900. In one example, graphics interface 940 can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface 940 generates a display based on data stored in memory 930 or based on operations executed by processor 910 or both. In one example, graphics interface 940 generates a display based on data stored in memory 930 or based on operations executed by processor 910 or both.
Accelerators 942 can be programmable or fixed function offload engines that can be accessed or used by a processor 910. For example, an accelerator among accelerators 942 can provide compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services. In some embodiments, in addition or alternatively, an accelerator among accelerators 942 provides field select controller capabilities as described herein. In some cases, accelerators 942 can be integrated into a CPU or connected to CPU by various devices (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, accelerators 942 can include a single or multi-core processor, graphics processing unit, logical execution unit single or multi-level cache, functional units usable to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs). Accelerators 942 can provide multiple neural networks, CPUs, processor cores, general purpose graphics processing units, or graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI model can use or include any or a combination of a reinforcement learning scheme, Q-learning scheme, deep-Q learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural network, recurrent combinatorial neural network, or other AI or ML model. Multiple neural networks, processor cores, or graphics processing units can be made available for use by AI or ML models.
Memory subsystem 920 represents the main memory of system 900 and provides storage for code to be executed by processor 910, or data values to be used in executing a routine. Memory subsystem 920 can include one or more memory devices 930 such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory 930 stores and hosts, among other things, operating system (OS) 932 to provide a software platform for execution of instructions in system 900. Additionally, applications 934 can execute on the software platform of OS 932 from memory 930. Applications 934 represent programs that have their own operational logic to perform execution of one or more functions. Processes 936 represent agents or routines that provide auxiliary functions to OS 932 or one or more applications 934 or a combination. OS 932, applications 934, and processes 936 provide software logic to provide functions for system 900. In one example, memory subsystem 920 includes memory controller 922, which is a memory controller to generate and issue commands to memory 930. It will be understood that memory controller 922 could be a physical part of processor 910 or a physical part of interface 912. For example, memory controller 922 can be an integrated memory controller, integrated onto a circuit with processor 910.
While not specifically illustrated, it will be understood that system 900 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a Hyper Transport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).
In one example, system 900 includes interface 914, which can be coupled to interface 912. In one example, interface 914 represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface 914. Network interface 950 provides system 900 the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 950 can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface 950 can transmit data to a device that is in the same data center or rack or a remote device, which can include sending data stored in memory. Network interface 950 can receive data from a remote device, which can include storing received data into memory. Various embodiments can be used in connection with network interface 950, processor 910, and memory subsystem 920.
In one example, system 900 includes one or more input/output (I/O) interface(s) 960. I/O interface 960 can include one or more interface components through which a user interacts with system 900 (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface 970 can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system 900. A dependent connection is one where system 900 provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.
In one example, system 900 includes storage subsystem 980 to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage 980 can overlap with components of memory subsystem 920. Storage subsystem 980 includes storage device(s) 984, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage 984 holds code or instructions and data 986 in a persistent state (e.g., the value is retained despite interruption of power to system 900). Storage 984 can be generically considered to be a “memory,” although memory 930 is typically the executing or operating memory to provide instructions to processor 910. Whereas storage 984 is nonvolatile, memory 930 can include volatile memory. In one example, storage subsystem 980 includes controller 982 to interface with storage 984. In one example controller 982 is a physical part of interface 914 or processor 910 or can include circuits or logic in both processor 910 and interface 914.
A volatile memory is memory whose state (and therefore the data stored in it) is indeterminate if power is interrupted to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain state. One example of dynamic volatile memory incudes DRAM (Dynamic Random Access Memory), or some variant such as Synchronous DRAM (SDRAM). Another example of volatile memory includes cache or static random access memory (SRAM). A memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR3 (Double Data Rate version 3, original release by JEDEC (Joint Electronic Device Engineering Council) on Jun. 27, 2007). DDR4 (DDR version 4, initial specification published in September 2012 by JEDEC), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version3, JESD209-3B, August 2013 by JEDEC), LPDDR4) LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WI02 (Wide Input/output version 2, JESD229-2 originally published by JEDEC in August 2014, HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013, LPDDR5 (currently in discussion by JEDEC), HBM2 (HBM version 2), currently in discussion by JEDEC, or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.
A non-volatile memory (NVM) device is a memory whose state is determinate even if power is interrupted to the device. In one embodiment, the NVM device can comprise a block addressable memory device, such as NAND technologies, or more specifically, multi-threshold level NAND flash memory (for example, Single-Level Cell (“SLC”), Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), or some other NAND). A NVM device can also comprise a byte-addressable write-in-place three dimensional cross point memory device, or other byte addressable write-in-place NVM device (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM) or phase change memory with a switch (PCMS), Intel® Optane™ memory, NVM devices that use chalcogenide phase change material (for example, chalcogenide glass), resistive memory including metal oxide base, oxygen vacancy base and Conductive Bridge Random Access Memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), magneto resistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory.
A power source (not depicted) provides power to the components of system 900. More specifically, power source typically interfaces to one or multiple power supplies in system 900 to provide power to the components of system 900. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.
In an example, system 900 can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed interconnects can be used such as PCIe, Ethernet, or optical interconnects (or a combination thereof).
Embodiments herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers such as those employed in a data center and/or server farm environment. The servers used in data centers and server farms comprise arrayed server configurations such as rack-based servers or blade servers. These servers are interconnected in communication via various network provisions, such as partitioning sets of servers into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private Intranet. For example, cloud hosting facilities may typically employ large data centers with a multitude of servers. A blade comprises a separate computing platform that is configured to perform server-type functions, that is, a “server on a card.” Accordingly, a blade includes components common to conventional servers, including a main printed circuit board (main board) providing internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted to the board.
In an example, system 900 can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed interconnects can be used such as: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), User Datagram Protocol (UDP), quick User Datagram Protocol (UDP) Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data can be copied or stored to virtualized storage nodes using a protocol such as NVMe over Fabrics (NVMe-oF) or NVMe.
Processors 1004 can be any a combination of a: processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allow programming of network interface 1000. For example, processors 1004 can provide for allocation or deallocation of intermediate queues. For example, a “smart network interface” can provide packet processing capabilities in the network interface using processors 1004.
Packet allocator 1024 can provide distribution of received packets for processing by multiple CPUs or cores using timeslot allocation described herein or RSS. When packet allocator 1024 uses RSS, packet allocator 1024 can calculate a hash or make another determination based on contents of a received packet to determine which CPU or core is to process a packet.
Interrupt coalesce 1022 can perform interrupt moderation whereby network interface interrupt coalesce 1022 waits for multiple packets to arrive, or for a time-out to expire, before generating an interrupt to host system to process received packet(s). Receive Segment Coalescing (RSC) can be performed by network interface 1000 whereby portions of incoming packets are combined into segments of a packet. Network interface 1000 provides this coalesced packet to an application.
Direct memory access (DMA) engine 1026 can copy a packet header, packet payload, and/or descriptor directly from host memory to the network interface or vice versa, instead of copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer.
Memory 1010 can be any type of volatile or non-volatile memory device and can store any queue or instructions used to program network interface 1000. Transmit queue 1006 can include data or references to data for transmission by network interface. Receive queue 1008 can include data or references to data that was received by network interface from a network. Descriptor queues 1020 can include descriptors that reference data or packets in transmit queue 1006 or receive queue 1008. Bus interface 1012 can provide an interface with host device (not depicted). For example, bus interface 1012 can be compatible with peripheral connect Peripheral Component Interconnect (PCI), PCI Express, PCI-x, Serial ATA (SATA), and/or Universal Serial Bus (USB) compatible interface (although other interconnection standards may be used).
Multiple of the computing racks 1102 may be interconnected via their ToR switches 1104 (e.g., to a pod-level switch or data center switch), as illustrated by connections to a network 1120. In some embodiments, groups of computing racks 1102 are managed as separate pods via pod manager(s) 1106. In one embodiment, a single pod manager is used to manage racks in the pod. Alternatively, distributed pod managers may be used for pod management operations.
Environment 1100 further includes a management interface 1122 that is used to manage various aspects of the environment. This includes managing rack configuration, with corresponding parameters stored as rack configuration data 1124.
In some examples, network interface and other embodiments described herein can be used in connection with a base station (e.g., 3G, 4G, 5G and so forth), macro base station (e.g., 5G networks), picostation (e.g., an IEEE 802.11 compatible access point), nanostation (e.g., for Point-to-MultiPoint (PtMP) applications), on-premises data centers, off-premises data centers, edge network elements, fog network elements, and/or hybrid data centers (e.g., data center that use virtualization, cloud and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).
Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation. A processor can be one or more combination of a hardware state machine, digital control logic, central processing unit, or any hardware, firmware and/or software elements.
Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.
According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.
One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
The appearances of the phrase “one example” or “an example” are not necessarily all referring to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element. Division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.
Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
The terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “asserted” used herein with reference to a signal denote a state of the signal, in which the signal is active, and which can be achieved by applying any logic level either logic 0 or logic 1 to the signal. The terms “follow” or “after” can refer to immediately following or following after some other event or events. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or removed depending on the particular applications. Any combination of changes can be used and one of ordinary skill in the art with the benefit of this disclosure would understand the many variations, modifications, and alternative embodiments thereof.
Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present. Additionally, conjunctive language such as the phrase “at least one of X, Y, and Z,” unless specifically stated otherwise, should also be understood to mean X, Y, Z, or any combination thereof, including “X, Y, and/or Z.”
Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An embodiment of the devices, systems, and methods may include any one or more, and any combination of, the examples described below.
Example 1 includes a computer-implemented method comprising: assigning a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers, wherein the one or more particular queue identifiers are associated with one or more queues that can be accessed solely using the polling group and no other polling group.
Example 2 includes any example, and includes allocating the polling group to execute on a central processing unit (CPU) core that runs no other polling group.
Example 3 includes any example, and includes allocating a second polling group to execute on a second central processing unit (CPU) core, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed solely using the second polling group.
Example 4 includes any example, and includes allocating a new connection to a queue identifier and allocating a polling group for the queue identifier of the new connection.
Example 5 includes any example, and includes based on termination of a connection, de-allocating the terminated connection from its queue identifier and de-allocating a polling group from polling for input/output operations associated with the terminated connection.
Example 6 includes any example, wherein the one or more queues include at least one queue allocated by a network interface for exclusive access by software and the software comprises the polling group.
Example 7 includes any example, wherein the polling group performs a busy polling mode and defers interrupts to identify at least one input or output operation until after busy polling mode ends.
Example 8 includes any example, wherein the storage transactions comprise Non-volatile Memory Express over Fabrics using a transport layer comprising one of: Transmission Control Protocol (TCP), InfiniBand, FibreChannel, or User Datagram Protocol (UDP).
Example 9 includes any example, and includes a non-transitory computer-readable medium, comprising instructions that if executed by one or more processors, cause the one or more processors to: execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers, wherein the one or more particular queue identifiers are associated with one or more queues that can be accessed using the polling group and no other polling group.
Example 10 includes any example, wherein the polling group is to execute on a processor that runs no other polling group.
Example 11 includes any example, and includes instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed by the second polling group but are not accessible by the polling group.
Example 12 includes any example, and includes instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: allocate a new connection to a queue identifier and allocate a polling group for the queue identifier of the new connection.
Example 13 includes any example, and includes instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: based on termination of a connection, de-allocate the terminated connection from its queue identifier and de-allocate a polling group from polling for input/output operations associated with the terminated connection.
Example 14 includes any example, wherein the one or more queues include at least one Application Device Queue (ADQ) accessible to a network interface.
Example 15 includes any example, wherein the polling group performs a busy polling mode and defers interrupts to report input/output transactions until after busy polling mode ends.
Example 16 includes any example, wherein the storage transactions comprise Non-volatile Memory Express over Fabrics using a transport layer comprising one of: Transmission Control Protocol (TCP), InfiniBand, FibreChannel, or User Datagram Protocol (UDP).
Example 17 includes any example, and includes an apparatus comprising: a network interface; a cache; and at least one central processing unit (CPU) processor coupled to the network interface and the cache, the at least one CPU processor configured to: execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers, wherein the one or more particular queue identifiers are associated with one or more queues that can be accessed using the polling group and no other polling group.
Example 18 includes any example, wherein the polling group is to execute on a processor that runs no other polling group.
Example 19 includes any example, wherein the at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group but are not accessible by the polling group.
Example 20 includes any example, wherein the one or more queues include at least one queue allocated by a network interface for exclusive access by software and the software comprises the polling group.
This application is a continuation of prior co-pending U.S. patent application Ser. No. 16/849,915, filed Apr. 15, 2020 and titled “STORAGE TRANSACTIONS WITH PREDICTABLE LATENCY”. The aforesaid prior Patent Application is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16849915 | Apr 2020 | US |
| Child | 18618912 | US |
