Not applicable.
Not applicable.
This invention relates generally to computer networks and more particularly to dispersing error encoded data.
Computing devices are known to communicate data, process data, and/or store data. Such computing devices range from wireless smart phones, laptops, tablets, personal computers (PC), work stations, and video game devices, to data centers that support millions of web searches, stock trades, or on-line purchases every day. In general, a computing device includes a central processing unit (CPU), a memory system, user input/output interfaces, peripheral device interfaces, and an interconnecting bus structure.
As is further known, a computer may effectively extend its CPU by using “cloud computing” to perform one or more computing functions (e.g., a service, an application, an algorithm, an arithmetic logic function, etc.) on behalf of the computer. Further, for large services, applications, and/or functions, cloud computing may be performed by multiple cloud computing resources in a distributed manner to improve the response time for completion of the service, application, and/or function. For example, Hadoop is an open source software framework that supports distributed applications enabling application execution by thousands of computers.
In addition to cloud computing, a computer may use “cloud storage” as part of its memory system. As is known, cloud storage enables a user, via its computer, to store files, applications, etc. on an Internet storage system. The Internet storage system may include a RAID (redundant array of independent disks) system and/or a dispersed storage system that uses an error correction scheme to encode data for storage.
The DSN memory 22 includes a plurality of storage units 36 that may be located at geographically different sites (e.g., one in Chicago, one in Milwaukee, etc.), at a common site, or a combination thereof. For example, if the DSN memory 22 includes eight storage units 36, each storage unit is located at a different site. As another example, if the DSN memory 22 includes eight storage units 36, all eight storage units are located at the same site. As yet another example, if the DSN memory 22 includes eight storage units 36, a first pair of storage units are at a first common site, a second pair of storage units are at a second common site, a third pair of storage units are at a third common site, and a fourth pair of storage units are at a fourth common site. Note that a DSN memory 22 may include more or less than eight storage units 36. Further note that each storage unit 36 includes a computing core (as shown in
Each of the computing devices 12-16, the managing unit 18, and the integrity processing unit 20 include a computing core 26, which includes network interfaces 30-33. Computing devices 12-16 may each be a portable computing device and/or a fixed computing device. A portable computing device may be a social networking device, a gaming device, a cell phone, a smart phone, a digital assistant, a digital music player, a digital video player, a laptop computer, a handheld computer, a tablet, a video game controller, and/or any other portable device that includes a computing core. A fixed computing device may be a computer (PC), a computer server, a cable set-top box, a satellite receiver, a television set, a printer, a fax machine, home entertainment equipment, a video game console, and/or any type of home or office computing equipment. Note that each of the managing unit 18 and the integrity processing unit 20 may be separate computing devices, may be a common computing device, and/or may be integrated into one or more of the computing devices 12-16 and/or into one or more of the storage units 36.
Each interface 30, 32, and 33 includes software and hardware to support one or more communication links via the network 24 indirectly and/or directly. For example, interface 30 supports a communication link (e.g., wired, wireless, direct, via a LAN, via the network 24, etc.) between computing devices 14 and 16. As another example, interface 32 supports communication links (e.g., a wired connection, a wireless connection, a LAN connection, and/or any other type of connection to/from the network 24) between computing devices 12 & 16 and the DSN memory 22. As yet another example, interface 33 supports a communication link for each of the managing unit 18 and the integrity processing unit 20 to the network 24.
Computing devices 12 and 16 include a dispersed storage (DS) client module 34, which enables the computing device to dispersed storage error encode and decode data as subsequently described with reference to one or more of
In operation, the managing unit 18 performs DS management services. For example, the managing unit 18 establishes distributed data storage parameters (e.g., vault creation, distributed storage parameters, security parameters, billing information, user profile information, etc.) for computing devices 12-14 individually or as part of a group of user devices. As a specific example, the managing unit 18 coordinates creation of a vault (e.g., a virtual memory block associated with a portion of an overall namespace of the DSN) within the DSTN memory 22 for a user device, a group of devices, or for public access and establishes per vault dispersed storage (DS) error encoding parameters for a vault. The managing unit 18 facilitates storage of DS error encoding parameters for each vault by updating registry information of the DSN 10, where the registry information may be stored in the DSN memory 22, a computing device 12-16, the managing unit 18, and/or the integrity processing unit 20.
The DSN managing unit 18 creates and stores user profile information (e.g., an access control list (ACL)) in local memory and/or within memory of the DSN memory 22. The user profile information includes authentication information, permissions, and/or the security parameters. The security parameters may include encryption/decryption scheme, one or more encryption keys, key generation scheme, and/or data encoding/decoding scheme.
The DSN managing unit 18 creates billing information for a particular user, a user group, a vault access, public vault access, etc. For instance, the DSTN managing unit 18 tracks the number of times a user accesses a non-public vault and/or public vaults, which can be used to generate per-access billing information. In another instance, the DSTN managing unit 18 tracks the amount of data stored and/or retrieved by a user device and/or a user group, which can be used to generate per-data-amount billing information.
As another example, the managing unit 18 performs network operations, network administration, and/or network maintenance. Network operations includes authenticating user data allocation requests (e.g., read and/or write requests), managing creation of vaults, establishing authentication credentials for user devices, adding/deleting components (e.g., user devices, storage units, and/or computing devices with a DS client module 34) to/from the DSN 10, and/or establishing authentication credentials for the storage units 36. Network administration includes monitoring devices and/or units for failures, maintaining vault information, determining device and/or unit activation status, determining device and/or unit loading, and/or determining any other system level operation that affects the performance level of the DSN 10. Network maintenance includes facilitating replacing, upgrading, repairing, and/or expanding a device and/or unit of the DSN 10.
The integrity processing unit 20 performs rebuilding of ‘bad’ or missing encoded data slices. At a high level, the integrity processing unit 20 performs rebuilding by periodically attempting to retrieve/list encoded data slices, and/or slice names of the encoded data slices, from the DSN memory 22. For retrieved encoded slices, they are checked for errors due to data corruption, outdated version, etc. If a slice includes an error, it is flagged as a ‘bad’ slice. For encoded data slices that were not received and/or not listed, they are flagged as missing slices. Bad and/or missing slices are subsequently rebuilt using other retrieved encoded data slices that are deemed to be good slices to produce rebuilt slices. The rebuilt slices are stored in the DSTN memory 22.
The DSN interface module 76 functions to mimic a conventional operating system (OS) file system interface (e.g., network file system (NFS), flash file system (FFS), disk file system (DFS), file transfer protocol (FTP), web-based distributed authoring and versioning (WebDAV), etc.) and/or a block memory interface (e.g., small computer system interface (SCSI), internet small computer system interface (iSCSI), etc.). The DSN interface module 76 and/or the network interface module 70 may function as one or more of the interface 30-33 of
In the present example, Cauchy Reed-Solomon has been selected as the encoding function (a generic example is shown in
The computing device 12 or 16 then disperse storage error encodes a data segment using the selected encoding function (e.g., Cauchy Reed-Solomon) to produce a set of encoded data slices.
Returning to the discussion of
As a result of encoding, the computing device 12 or 16 produces a plurality of sets of encoded data slices, which are provided with their respective slice names to the storage units for storage. As shown, the first set of encoded data slices includes EDS 1_1 through EDS 5_1 and the first set of slice names includes SN 1_1 through SN 5_1 and the last set of encoded data slices includes EDS 1_Y through EDS 5_Y and the last set of slice names includes SN 1_Y through SN 5_Y.
To recover a data segment from a decode threshold number of encoded data slices, the computing device uses a decoding function as shown in
In one embodiment, during a dispersed computation job, a data record may cross boundaries of a slice stream, and require reading from adjacent DST units. To limit potential harm, a DST may enforce restrictions regarding how much adjacent data a neighboring DST may read of its data. For example, if records are known to never exceed 1 MB, a DST may limit the ability of an adjacent DST to read more than 1 MB of data.
The DS processing unit 16 receives data 40 and/or a task request 38 and encodes data 40 to produce at least two groups of data slices 1-2 and produces at least two groups of partial tasks 1-2 associated with the task request 38. The data 40 may include a plurality of data records. The DST processing unit 16 may encode a data record of the plurality of data records to produce a last slice of a first group of data slices 1 and a first slice of a second group of data slices 2. A first group of partial tasks 1 may include a partial task associated with the data record. The DST processing unit 16 sends the at least two groups of data slices 1-2 and at least two groups of partial tasks 1-2 to a first DST execution unit 36 of the at least two DST execution units 36. The first DST execution unit 36 stores data slices 1 in the slice memory 700 of the first DST execution of 36 and stores the partial tasks 1 in the computing task memory 702 of the first DST execution unit 36.
The DT execution module 90 of the first DST execution unit 36 retrieves data slices 1 from the slice memory 700 and retrieves partial tasks 1 from the computing task memory 702. The DT execution module 90 determines whether the slice memory 700 contains every data slice required to execute partial tasks 1. When the DT execution module 90 determines that slice memory does not contain every data slice required to execute partial tasks 1, the DT execution module 90 identifies at least one other data slice. For example, the DT execution module identifies a first slice of the data slices 2 when a data record associated with a partial task 1 includes a last slice of the data slices 1 and the first slice of the data slices 2. The DT execution module 90 generates a slice request 734 to obtain the at least one other data slice from another DST execution unit 36. The slice request 734 includes one or more of a slice name associated with the at least one other data slice, a requesting entity identifier, a copy of the partial task 1, or an access credential (e.g., a signature, a signed copy of the partial task 1). The DT execution module sends the slice request 734 to the other DST execution unit 36.
The DT execution module 90 of the other DST execution unit 36 receives the slice request 734 and may authorize the slice request 734 based on the request. For example, the DT execution module 90 of the other DST execution of 36 verifies a signature of the slice request 734. When the request is authorized, the DT execution module 90 of the other DST execution of 36 facilitates sending the at least one other data slice to the DST execution unit 36. The DST execution 36 stores the at least one other data slice (e.g., data slice 2) in the slice memory 700. The DT execution module 90 may determine whether the slice memory 700 contains every data slice required to execute partial tasks 1. When the DT execution module 90 determines that slice memory 700 contains every data slice required to execute partial tasks 1, the DT execution module 90 executes one or more partial tasks of partial tasks 1 on data slices retrieved from the slice memory (e.g., data slices 1, data slices 2) to produce partial results 708. For example, the DT execution module 90 aggregates data slice 1 and data slice 2 to reproduce the data record and executes the one or more partial tasks on the data record to produce the partial results 708. The DT execution module outputs the partial results 708 to the DST processing unit 16 and/or the user device 14. Alternatively, or in addition to, the DT execution module 90 of the other DST execution unit 36 may perform a partial task 2 on a data slice 2 to produce partial results 708.
The method continues at step 746 where the processing module outputs the slice request to the other DST execution unit. The method continues at step 748 where the processing module receives the other data slice from the other DST execution unit. The method continues at step 750 where the processing module performs the partial task on the data slice and the other data slice to produce partial results. The performing may include one or more of aggregating at least a portion of the data slice and at least a portion of the other data slice to produce the data record and executing at least a portion of the associated partial task on the data record to produce the partial results.
The method described above in conjunction with the processing module can alternatively be performed by other modules of the dispersed storage network or by other computing devices. In addition, at least one memory section (e.g., a non-transitory computer readable storage medium) that stores operational instructions can, when executed by one or more processing modules of one or more computing devices of the dispersed storage network (DSN), cause the one or more computing devices to perform any or all of the method steps described above.
It is noted that terminologies as may be used herein such as bit stream, stream, signal sequence, etc. (or their equivalents) have been used interchangeably to describe digital information whose content corresponds to any of a number of desired types (e.g., data, video, speech, audio, etc. any of which may generally be referred to as ‘data’).
As may be used herein, the terms “substantially” and “approximately” provides an industry-accepted tolerance for its corresponding term and/or relativity between items. Such an industry-accepted tolerance ranges from less than one percent to fifty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. Such relativity between items ranges from a difference of a few percent to magnitude differences. As may also be used herein, the term(s) “configured to”, “operably coupled to”, “coupled to”, and/or “coupling” includes direct coupling between items and/or indirect coupling between items via an intervening item (e.g., an item includes, but is not limited to, a component, an element, a circuit, and/or a module) where, for an example of indirect coupling, the intervening item does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As may further be used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two items in the same manner as “coupled to”. As may even further be used herein, the term “configured to”, “operable to”, “coupled to”, or “operably coupled to” indicates that an item includes one or more of power connections, input(s), output(s), etc., to perform, when activated, one or more its corresponding functions and may further include inferred coupling to one or more other items. As may still further be used herein, the term “associated with”, includes direct and/or indirect coupling of separate items and/or one item being embedded within another item.
As may be used herein, the term “compares favorably”, indicates that a comparison between two or more items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1. As may be used herein, the term “compares unfavorably”, indicates that a comparison between two or more items, signals, etc., fails to provide the desired relationship.
As may also be used herein, the terms “processing module”, “processing circuit”, “processor”, and/or “processing unit” may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module, module, processing circuit, and/or processing unit may be, or further include, memory and/or an integrated memory element, which may be a single memory device, a plurality of memory devices, and/or embedded circuitry of another processing module, module, processing circuit, and/or processing unit. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. Note that if the processing module, module, processing circuit, and/or processing unit includes more than one processing device, the processing devices may be centrally located (e.g., directly coupled together via a wired and/or wireless bus structure) or may be distributedly located (e.g., cloud computing via indirect coupling via a local area network and/or a wide area network). Further note that if the processing module, module, processing circuit, and/or processing unit implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory element storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Still further note that, the memory element may store, and the processing module, module, processing circuit, and/or processing unit executes, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the Figures. Such a memory device or memory element can be included in an article of manufacture.
One or more embodiments have been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claims. Further, the boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality.
To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claims. One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
In addition, a flow diagram may include a “start” and/or “continue” indication. The “start” and “continue” indications reflect that the steps presented can optionally be incorporated in or otherwise used in conjunction with other routines. In this context, “start” indicates the beginning of the first step presented and may be preceded by other activities not specifically shown. Further, the “continue” indication reflects that the steps presented may be performed multiple times and/or may be succeeded by other activities not specifically shown. Further, while a flow diagram indicates a particular ordering of steps, other orderings are likewise possible provided that the principles of causality are maintained.
The one or more embodiments are used herein to illustrate one or more aspects, one or more features, one or more concepts, and/or one or more examples. A physical embodiment of an apparatus, an article of manufacture, a machine, and/or of a process may include one or more of the aspects, features, concepts, examples, etc. described with reference to one or more of the embodiments discussed herein. Further, from figure to figure, the embodiments may incorporate the same or similarly named functions, steps, modules, etc. that may use the same or different reference numbers and, as such, the functions, steps, modules, etc. may be the same or similar functions, steps, modules, etc. or different ones.
Unless specifically stated to the contra, signals to, from, and/or between elements in a figure of any of the figures presented herein may be analog or digital, continuous time or discrete time, and single-ended or differential. For instance, if a signal path is shown as a single-ended path, it also represents a differential signal path. Similarly, if a signal path is shown as a differential path, it also represents a single-ended signal path. While one or more particular architectures are described herein, other architectures can likewise be implemented that use one or more data buses not expressly shown, direct connectivity between elements, and/or indirect coupling between other elements as recognized by one of average skill in the art.
The term “module” is used in the description of one or more of the embodiments. A module implements one or more functions via a device such as a processor or other processing device or other hardware that may include or operate in association with a memory that stores operational instructions. A module may operate independently and/or in conjunction with software and/or firmware. As also used herein, a module may contain one or more sub-modules, each of which may be one or more modules.
As may further be used herein, a computer readable memory includes one or more memory elements. A memory element may be a separate memory device, multiple memory devices, or a set of memory locations within a memory device. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information. The memory device may be in a form a solid state memory, a hard drive memory, cloud memory, thumb drive, server memory, computing device memory, and/or other physical medium for storing digital information.
While particular combinations of various functions and features of the one or more embodiments have been expressly described herein, other combinations of these features and functions are likewise possible. The present disclosure is not limited by the particular examples disclosed herein and expressly incorporates these other combinations.
The present U.S. Utility patent application claims priority pursuant to 35 U.S.C. § 120 as a continuation of U.S. Utility application Ser. No. 16/858,839, entitled “STORAGE UNIT PARTIAL TASK PROCESSING”, filed Apr. 27, 2020, which is a continuation of U.S. Utility application Ser. No. 15/824,433, entitled “READS FOR DISPERSED COMPUTATION JOBS” filed Nov. 28, 2017, which is a continuation-in-part of U.S. Utility application Ser. No. 15/418,164, entitled “ENCRYPTING SEGMENTED DATA IN A DISTRIBUTED COMPUTING SYSTEM” filed Jan. 27, 2017, issued as U.S. Pat. No. 10,447,662 on Oct. 15, 2019, which is a continuation of U.S. Utility application Ser. No. 13/917,017, entitled “ENCRYPTING SEGMENTED DATA IN A DISTRIBUTED COMPUTING SYSTEM”, filed Jun. 13, 2013, issued as U.S. Pat. No. 9,674,155 on Jun. 6, 2017, which is a continuation-in-part of U.S. Utility application Ser. No. 13/707,428, entitled “DISTRIBUTED COMPUTING IN A DISTRIBUTED STORAGE AND TASK NETWORK”, filed Dec. 6, 2012, issued as U.S. Pat. No. 9,298,548 on Mar. 29, 2016, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 61/569,387, entitled “DISTRIBUTED STORAGE AND TASK PROCESSING”, filed Dec. 12, 2011, all of which are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility patent application for all purposes. U.S. Utility application Ser. No. 13/917,017 also claims priority pursuant to 35 U.S.C. § 119(e) to U.S. Provisional Application No. 61/679,007, entitled “TASK PROCESSING IN A DISTRIBUTED STORAGE AND TASK NETWORK”, filed Aug. 2, 2012, which is hereby incorporated herein by reference in its entirety and made part of the present U.S. Utility patent application for all purposes.
Number | Name | Date | Kind |
---|---|---|---|
4092732 | Ouchi | May 1978 | A |
5454101 | Mackay | Sep 1995 | A |
5485474 | Rabin | Jan 1996 | A |
5774643 | Lubbers | Jun 1998 | A |
5802364 | Senator | Sep 1998 | A |
5809285 | Hilland | Sep 1998 | A |
5890156 | Rekieta | Mar 1999 | A |
5987622 | Lo Verso | Nov 1999 | A |
5991414 | Garay | Nov 1999 | A |
6012159 | Fischer | Jan 2000 | A |
6058454 | Gerlach | May 2000 | A |
6128277 | Bruck | Oct 2000 | A |
6175571 | Haddock | Jan 2001 | B1 |
6192472 | Garay | Feb 2001 | B1 |
6256688 | Suetaka | Jul 2001 | B1 |
6272658 | Steele | Aug 2001 | B1 |
6301604 | Nojima | Oct 2001 | B1 |
6356949 | Katsandres | Mar 2002 | B1 |
6366995 | Vilkov | Apr 2002 | B1 |
6374336 | Peters | Apr 2002 | B1 |
6415373 | Peters | Jul 2002 | B1 |
6418539 | Walker | Jul 2002 | B1 |
6449688 | Peters | Sep 2002 | B1 |
6490353 | Tan | Dec 2002 | B1 |
6567948 | Steele | May 2003 | B2 |
6571282 | Bowman-Amuah | May 2003 | B1 |
6609223 | Wolfgang | Aug 2003 | B1 |
6718361 | Basani | Apr 2004 | B1 |
6760808 | Peters | Jul 2004 | B2 |
6785768 | Peters | Aug 2004 | B2 |
6785783 | Buckland | Aug 2004 | B2 |
6826711 | Moulton | Nov 2004 | B2 |
6879596 | Dooply | Apr 2005 | B1 |
7003688 | Pittelkow | Feb 2006 | B1 |
7024451 | Jorgenson | Apr 2006 | B2 |
7024609 | Wolfgang | Apr 2006 | B2 |
7080101 | Watson | Jul 2006 | B1 |
7103824 | Halford | Sep 2006 | B2 |
7103915 | Redlich | Sep 2006 | B2 |
7111115 | Peters | Sep 2006 | B2 |
7140044 | Redlich | Nov 2006 | B2 |
7146644 | Redlich | Dec 2006 | B2 |
7171493 | Shu | Jan 2007 | B2 |
7222133 | Raipurkar | May 2007 | B1 |
7240236 | Cutts | Jul 2007 | B2 |
7272613 | Sim | Sep 2007 | B2 |
7480909 | McKean et al. | Jan 2009 | B2 |
7636724 | de la Torre | Dec 2009 | B2 |
9848044 | Leggette | Dec 2017 | B2 |
9998538 | Kazi | Jun 2018 | B2 |
20010021186 | Ono | Sep 2001 | A1 |
20020062422 | Butterworth | May 2002 | A1 |
20020091975 | Redlich | Jul 2002 | A1 |
20020099959 | Redlich | Jul 2002 | A1 |
20020144153 | LeVine | Oct 2002 | A1 |
20020166079 | Ulrich | Nov 2002 | A1 |
20030018927 | Gadir | Jan 2003 | A1 |
20030037261 | Meffert | Feb 2003 | A1 |
20030065617 | Watkins | Apr 2003 | A1 |
20030084020 | Shu | May 2003 | A1 |
20030115364 | Shu | Jun 2003 | A1 |
20030163507 | Chang et al. | Aug 2003 | A1 |
20040024963 | Talagala | Feb 2004 | A1 |
20040052369 | Stebbings | Mar 2004 | A1 |
20040122917 | Menon | Jun 2004 | A1 |
20040215998 | Buxton | Oct 2004 | A1 |
20040228493 | Ma | Nov 2004 | A1 |
20050100022 | Ramprashad | May 2005 | A1 |
20050114594 | Corbett | May 2005 | A1 |
20050125593 | Karpoff | Jun 2005 | A1 |
20050131993 | Fatula, Jr. | Jun 2005 | A1 |
20050132070 | Redlich | Jun 2005 | A1 |
20050144382 | Schmisseur | Jun 2005 | A1 |
20050229069 | Hassner | Oct 2005 | A1 |
20060047907 | Shiga | Mar 2006 | A1 |
20060136448 | Cialini | Jun 2006 | A1 |
20060156059 | Kitamura | Jul 2006 | A1 |
20060224603 | Correll, Jr. | Oct 2006 | A1 |
20070030918 | Kobayashi | Feb 2007 | A1 |
20070050543 | Pomerantz | Mar 2007 | A1 |
20070079081 | Gladwin | Apr 2007 | A1 |
20070079082 | Gladwin | Apr 2007 | A1 |
20070079083 | Gladwin | Apr 2007 | A1 |
20070088970 | Buxton | Apr 2007 | A1 |
20070174192 | Gladwin | Jul 2007 | A1 |
20070214285 | Au | Sep 2007 | A1 |
20070234110 | Soran | Oct 2007 | A1 |
20070283167 | Venters, III | Dec 2007 | A1 |
20080115143 | Shimizu | May 2008 | A1 |
20080212776 | Motoyama | Sep 2008 | A1 |
20090041244 | Lee | Feb 2009 | A1 |
20090094251 | Gladwin | Apr 2009 | A1 |
20090094318 | Gladwin | Apr 2009 | A1 |
20090217385 | Teow | Aug 2009 | A1 |
20100023524 | Gladwin | Jan 2010 | A1 |
20100268877 | Resch | Oct 2010 | A1 |
20110029524 | Baptist | Feb 2011 | A1 |
20110071988 | Resch | Mar 2011 | A1 |
20110072321 | Dhuse | Mar 2011 | A1 |
20110138192 | Kocher | Jun 2011 | A1 |
20110185258 | Grube et al. | Jul 2011 | A1 |
20110264717 | Grube et al. | Oct 2011 | A1 |
20110314058 | Motwani | Dec 2011 | A1 |
20180083930 | Baptist | Mar 2018 | A1 |
20190012234 | Grube | Jan 2019 | A1 |
Number | Date | Country |
---|---|---|
1903750 | Mar 2008 | EP |
Entry |
---|
Chung; An Automatic Data Segmentation Method for 3D Measured Data Points; National Taiwan University; pp. 1-8; 1998. |
Communication pursuant to Article 94(3) EPC; EP Application No. 12856963.9; dated May 26, 2017; 9 pages. |
Editor: Valerie Illingworth for Market House Books, The Penguin Dictionary of Electronics, 1998, Penguin Group, Third Edition, Pertinent pp. 349 and 447. |
European Patent Office; Extended Search Report; EP Application No. 12856963.9; dated Jun. 23, 2015; 7 pgs. |
Harrison; Lightweight Directory Access Protocol (LDAP): Authentication Methods and Security Mechanisms; IETF Network Working Group; RFC 4513; Jun. 2006; pp. 1-32. |
International Business Machines; Response to EP communication dated May 26, 2017; dated Nov. 1, 2017; 5 pgs. |
International Search Report and Written Opinion; International Search Authority; International Application No. PCT/US12/68883; dated Feb. 26, 2013; 12 pgs. |
Kubiatowicz, et al.; OceanStore: An Architecture for Global-Scale Persistent Storage; Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2000); Nov. 2000; pp. 1-12. |
LEGG; Lightweight Directory Access Protocol (LDAP): Syntaxes and Matching Rules; IETF Network Working Group; RFC 4517; Jun. 2006; pp. 1-50. |
Plank, T1: Erasure Codes for Storage Applications; FAST2005, 4th Usenix Conference on File Storage Technologies; Dec. 13-16, 2005; pp. 1-74. |
Rabin; Efficient Dispersal of Information for Security, Load Balancing, and Fault Tolerance; Journal of the Association for Computer Machinery; vol. 36, No. 2; Apr. 1989; pp. 335-348. |
Satran, et al.; Internet Small Computer Systems Interface (iSCSI); IETF Network Working Group; RFC 3720; Apr. 2004; pp. 1-257. |
Sciberras; Lightweight Directory Access Protocol (LDAP): Schema for User Applications; IETF Network Working Group; RFC 4519; Jun. 2006; pp. 1-33. |
Sermersheim; Lightweight Directory Access Protocol (LDAP): The Protocol; IETF Network Working Group; RFC 1511; Jun. 2006; pp. 1-68. |
Shamir; How to Share a Secret; Communications of the ACM; vol. 22, No. 11; Nov. 1979; pp. 612-613. |
Smith; Lightweight Directory Access Protocol (LDAP): Uniform Resource Locator; IETF Network Working Group; RFC 4516; Jun. 2006; pp. 1-15. |
Smith; Lightweight Directory Access Protocol (LDAP): String Representation of Search Filters; IETF Network Working Group; RFC 4515; Jun. 2006; pp. 1-12. |
Wildi; Java iSCSi Initiator; Master Thesis; Department of Computer and Information Science, University of Konstanz; Feb. 2007; 60 pgs. |
Xin, et al.; Evaluation of Distributed Recovery in Large-Scale Storage Systems; 13th IEEE International Symposium on High Performance Distributed Computing; Jun. 2004; pp. 172-181. |
Zeilenga; Lightweight Directory Access Protocol (LDAP): Directory Information Models; IETF Network Working Group; RFC 4512; Jun. 2006; pp. 1-49. |
Zeilenga; Lightweight Directory Access Protocol (LDAP): Internationalized String Preparation; IETF Network Working Group; RFC 4518; Jun. 2006; pp. 1-14. |
Zeilenga; Lightweight Directory Access Protocol (LDAP): String Representation of Distinguished Names; IETF Network Working Group; RFC 4514; Jun. 2006; pp. 1-15. |
Zeilenga; Lightweight Directory Access Protocol (LDAP): Technical Specification Road Map; IETF Network Working Group; RFC 4510; Jun. 2006; pp. 1-8. |
Number | Date | Country | |
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20230025990 A1 | Jan 2023 | US |
Number | Date | Country | |
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61679007 | Aug 2012 | US | |
61569387 | Dec 2011 | US |
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Child | 13917017 | US |