Claims
- 1. A method for forming metallization for controlling stress voids on an integrated circuit comprising the steps of: providing a semiconductor substrate having integrated circuitry formed therein; and forming an alloy consisting of aluminum-copper-tungsten on the substrate.
- 2. The method of claim 1 wherein the step of forming the alloy further comprises depositing a homogeneous alloy consisting of aluminum-copper-tungsten onto the substrate.
- 3. The method of claim 1 wherein the step of forming the alloy further comprises depositing a homogeneous layer consisting of an aluminum-copper alloy onto the substrate, forming a layer consisting of tungsten on top of or within the homogeneous layer, and heating the homogeneous layer and the layer consisting of tungsten to diffuse tungsten into the aluminum-copper alloy to provide an aluminum-copper-tungsten alloy.
- 4. The method of claim 2 further comprising the step of patterning the homogeneous alloy after the deposition step using a reactive ion etch process.
- 5. The method of claim 2 wherein the deposition step comprises sputtering from target consisting of a homogeneous aluminum-copper-tungsten alloy.
- 6. A process for forming a metallization layer on semiconductor devices comprising the steps of:
- providing a substrate including semiconductor devices formed therein; and
- forming the metallization layer onto the substrate, wherein the metallization layer consists of an aluminum-copper-tungsten alloy.
- 7. The process of claim 6 wherein the step of forming the metallization layer includes forming the metallization layer wherein tungsten comprises less than 0.5 weight percent of the alloy.
- 8. The process of claim 6 wherein the step of forming the metallization layer includes forming the metallization layer wherein copper comprises less than 1.5 weight percent of the alloy and wherein tungsten comprises less than 0.5 percent of the alloy.
Parent Case Info
This is a division of application Ser. No. 08/430,105, filed Apr. 27, 1995, now U.S. Pat. No. 5,554,889, which is a continuation of Ser. No. 07/862,710, Apr. 3, 1992, abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (6)
Number |
Date |
Country |
62-240734 |
Oct 1987 |
JPX |
2240733 |
Oct 1987 |
JPX |
2240736 |
Oct 1987 |
JPX |
2240738 |
Oct 1987 |
JPX |
2240734 |
Oct 1987 |
JPX |
1124253 |
May 1989 |
JPX |
Non-Patent Literature Citations (5)
Entry |
I. Krafcsik et al. "Influence of Cu as an impurity in Al/Ti and Al/W thin-film reactions" Appl. Phys. Lett. 43(11) (Dec. 1983) pp. 1015-1017. |
Prevarskiy, et al. "Phase equilibria and crystal structures of compounds in the W-Cu-Al system" Russian Metallurgy (1983) No. 5 pp. 187-189 (abstract only). |
1-.mu.m EPIC process enhances TI's CMOS logic circuits, Electronics Design, June 26, 1986, p. 21. |
Donald S. Gardner et al., "Layered and Homogenous Films of Aluminum and Aluminum/Silicon with Titanium and Tungsten for Multilevel Interconnects", IEEE Transactios on Electron Devices, Feb. 1985, vol. ED-32, No. 2, pp. 174-183. |
J.M. Pimbley et al., VLSI Electronics Microstructure Science, Advanced CMOS Process Technology, 1989, vol. 19, pp. 66-73. |
Divisions (1)
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Number |
Date |
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Parent |
430105 |
Apr 1995 |
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Continuations (1)
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Number |
Date |
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Parent |
862710 |
Apr 1992 |
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