Claims
- 1. A fabrication method for a buried bit line, comprising:
forming a patterned mask layer on a substrate; forming a shallow doped region in the substrate not covered by the mask layer; forming a liner layer with a predetermined thickness on at least a side surface of the mask layer; and forming a deep doped region in the substrate not covered by the liner layer and the mask layer, wherein the shallow doped region and the deep doped region together serve as a buried bit line.
- 2. The method of claim 9, wherein the mask layer is formed with a photoresist material, polysilicon or a dielectric material.
- 3. The method of claim 11, wherein liner layer is reworked directly when deviations occur in a critical dimension after the liner layer is formed.
- 4. The method of claim 9, wherein the liner layer is formed by plasma enhanced chemical vapor deposition.
- 5. The method of claim 9, wherein the deep doped region is formed with an implantation energy of about 50 KeV to 120 KeV.
- 6. The method of claim 9, wherein the shallow doped region is formed with an implantation energy of about 40 KeV to 80 KeV.
- 7. The method of claim 9, wherein dopant concentrations in the deep doped region and in the shallow doped region are about the same.
- 8. A memory device, comprising:
a substrate; a gate, disposed on a part of the substrate; a gate oxide layer, disposed between the substrate and the gate; a shallow doped region, disposed in the substrate beside both sides of the gate; and a deep doped region, disposed in the substrate under a part of the shallow doped region, wherein the shallow doped region and the deep doped region together serve as a buried bit line of the memory device.
- 9. The memory device of claim 17, wherein forming the shallow doped region and the deep doped region further comprises:
forming a patterned mask layer on the substrate; performing a first doped region in the substrate not covered by the mask layer to form the shallow doped region; forming a liner layer with predetermined thickness on at least a side surface of the mask layer; and performing a second doped region in the substrate not covered by the liner layer and the mask layer to form a deep doped region.
- 10. The method of claim 18, wherein the mask layer is formed with a photoresist material, polysilicon, or a dielectric material.
- 11. The method of claim 18, wherein the liner layer comprises a high molecular weight material layer formed by plasma enhanced chemical vapor deposition.
- 12. The method of claim 18, wherein the deep doped region is formed with an implantation energy of about 50 KeV to 120 KeV and the shallow doped region is formed with an implantation energy of about 40 KeV to 80 KeV.
- 13. The method of claim 17, wherein dopant concentrations in the deep doped region and in the shallow doped region are about the same.
- 14. The method of claim 17, wherein a dopant concentration in the deep doped region is about 1021/cm3 to 1022/cm3.
- 15. The method of claim 17, wherein a dopant concentration in the shallow doped region is about 1021/cm3 to 1022/cm3.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 10/065,351 filed Oct. 08, 2002, which claims the priority benefit of U.S. provisional application serial No. 60/319,376, filed on Jul. 3, 2002.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60319376 |
Jul 2002 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
10065351 |
Oct 2002 |
US |
Child |
10708210 |
Feb 2004 |
US |