Patent Application
20250142837
The present disclosure relates generally to memory devices, and more particularly to structures having 1T1R architecture for resistive random-access memory (RRAM) devices and methods of forming the same.
One of the non-volatile memory (NVM) technologies utilized in advanced computing systems, like processing-in-memory (PIM) applications and machine learning (ML) applications, is a resistive random-access memory (RRAM) device that has one transistor-one resistor (1T1R) architecture. The RRAM device may make use of binary neural network (BNN)-based techniques to provide a high-density architecture with high parallel programming speed and low power consumption for advanced computing systems.
The 1T1R architecture of the RRAM device may include a single transistor (1T) coupled with a single RRAM cell (1R) in a crossbar three-dimensional (3D) configuration. The RRAM cell may utilize a resistive element to store data by changing its resistance states, representing binary values (0s and 1s), and the transistor may serve as an access element to read and write data to the RRAM cell.
In order to meet the growing needs of the semiconductor industry, structures having 1T1R architecture for resistive random-access memory (RRAM) devices providing for improved performance metrics and methods of forming the same are needed.
To achieve the foregoing and other aspects of the present disclosure, structures having 1T1R architecture for resistive random-access memory (RRAM) devices and methods of forming the same are presented.
According to an aspect of the present disclosure, a structure for a memory device is provided. The structure includes a memory cell and a transistor. The memory cell includes a first electrode and a second electrode. The transistor is adjacent to the memory cell. The transistor includes a gate electrode including an upper section and a lower section, a third electrode under the gate electrode, and the second electrode, wherein the second electrode is above the third electrode and laterally adjacent to the lower section of the gate electrode.
According to another aspect of the present disclosure, a structure for a memory device is provided. The structure includes an interlayer dielectric, a first memory cell, and a first transistor. The first memory cell is over the interlayer dielectric and the first transistor is partially in the interlayer dielectric. The first transistor includes a first electrode, a second electrode, and a gate electrode. The first electrode is in the interlayer dielectric and the second electrode is on the interlayer dielectric. The second electrode is a common electrode shared between the first transistor and the first memory cell. The gate electrode is partially in the interlayer dielectric and includes an upper section and a lower section. The second electrode is partially under the upper section of the gate electrode.
According to yet another aspect of the present disclosure, a method of forming a structure for a memory device is provided. The method includes forming an interlayer dielectric and forming a first electrode in the interlayer dielectric. A second electrode is formed on the interlayer dielectric. A gate electrode and a third electrode are formed partially in and on the interlayer dielectric, respectively. The gate electrode and the third electrode partially overlap the second electrode.
The embodiments of the present disclosure will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the disclosure.
Additionally, features in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the features in the drawings may be exaggerated relative to other features to help improve the understanding of the embodiments of the device. The same reference numerals in different drawings denote the same features, while similar reference numerals may, but do not necessarily, denote similar features.
The present disclosure relates to structures having one transistor-one resistor (1T1R) architecture for resistive random-access memory (RRAM) devices and methods of forming the same. Various embodiments of the present disclosure are now described in detail with accompanying drawings. It is noted that like and corresponding features are referred to by the use of the same reference numerals. The embodiments disclosed herein are exemplary, and not intended to be exhaustive or limiting to the disclosure.
The transistor 102 may be partially in an interlayer dielectric (ILD) 108 and the memory cell 104 may be over the ILD 108. The transistor 102 may include a gate electrode 106. The gate electrode 106 may include an upper section that is predominantly horizontal and a lower section that is predominantly vertical adjoining the upper section. For example, the gate electrode 106 may adopt a T-shaped structure. The lower section of the gate electrode 106 may include a lower portion in the ILD 108 and an upper portion above the ILD 108, and the upper portion may adjoin the upper section of the gate electrode 106. Alternatively, the gate electrode 106 may adopt a planar structure that is predominantly vertical, and the planar structure may include a lower portion in the ILD 108 and an upper portion above the ILD 108. The gate electrode 106 may include an electrically conductive material, for example, tantalum, hafnium, titanium, copper, silver, cobalt, or tungsten. Alternatively, the gate electrode 106 may include a combination of electrically conductive materials, for example, titanium and titanium nitride. The ILD 108 may include an electrically insulative material, for example, silicon oxide, carbon-doped silicon oxide, tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), or undoped silicate glass (USG).
The transistor 102 may further include an electrode 110 and an electrode 112. The electrode 110 and the electrode 112 may serve as source/drain electrodes of the transistor 102. As used herein, the term “source/drain electrode” may refer to an electrically conductive element that can function as either a source or a drain of a transistor. For example, the electrode 110 may function as a source and the electrode 112 may function as a drain of the transistor 102, or vice versa.
The electrode 110 may be arranged in the ILD 108 under the gate electrode 106 and the electrode 112 may be arranged on the ILD 108. The electrode 112 may be further arranged partially under the upper section of the gate electrode 106. For example, the upper section of the gate electrode 106 may partially overlap a corner of the electrode 112. Even though
The transistor 102 may yet further include a channel layer 114 and a dielectric layer 116 over the channel layer 114. The channel layer 114 may serve as a pathway for charge carriers to move between the electrode 110 and the electrode 112. The dielectric layer 116 may serve as a gate dielectric layer of the transistor 102. The channel layer 114 and the dielectric layer 116 may be conformal and continuous, including a lower portion in the ILD 108 and an upper portion above the ILD 108. The channel layer 114 and the dielectric layer 116 may separate the electrode 110 and the electrode 112 from the gate electrode 106.
The channel layer 114 may be at least completely under the gate electrode 106. The channel layer 114 may overlap at least a portion of the electrode 110, and further extend vertically to partially overlap the electrode 112. For example, the channel layer 114 may include end portions terminating over an upper surface of the electrode 112. The end portions of the channel layer 114 may laterally extend beyond the gate electrode 106, as illustrated. Alternatively, the channel layer 114 may be under the gate electrode 106 such that a side surface of the upper section of the gate electrode 106 may be substantially coplanar with a side surface of the channel layer 114 (not shown). The channel layer 114 may include an oxide semiconductor material, for example, zinc oxide, cadmium oxide, indium oxide, or indium gallium zinc oxide. Alternatively, the channel layer 114 may include amorphous silicon.
The dielectric layer 116 may at least overlap the channel layer 114 under the gate electrode 106. The dielectric layer 116 may further overlap the electrode 112. For example, the dielectric layer 116 may directly overlap a remaining portion of the electrode 112 not covered by the channel layer 114, and further directly overlap a side surface of the electrode 112 distal from the gate electrode 106. The dielectric layer 116 may additionally extend to overlie the ILD 108. The dielectric layer 116 may include an electrically insulative material, for example, tantalum oxide, titanium oxide, hafnium oxide, aluminum oxide, or silicon oxide.
Referring to
Referring back to
The memory cell 104 may further include another memory electrode 118 over the ILD 108. In particular, the memory electrode 118 may be arranged laterally adjacent to the gate electrode 106 and partially overlap a corner of the electrode 112 that is distal from the gate electrode 106. Even though
The dielectric layer 116 may additionally separate the memory electrode 118 from the electrode 112 and may serve as a common dielectric layer shared between the transistor 102 and the memory cell 104, i.e., the dielectric layer 116 may serve as a gate dielectric layer of the transistor 102 and also as a resistive layer of the memory cell 104.
Arranging the memory electrode 118 over the corner of the electrode 112 may advantageously improve the electrical performance of the memory cell 104. For example, the memory electrode 118 may overlap the corner of the electrode 112 where stronger electric fields may concentrate, and these higher electric fields may readily facilitate a pathway for the formation of one or more conductive filaments within the dielectric layer 116 to program the memory cell 104. The formation of one or more conductive filaments may be substantially confined in the region of the dielectric layer 116 around the corner of the electrode 112, thereby minimizing the variability of locations where the conductive filaments may form, as well as providing improved process stability.
The transistor 102 may serve as an access transistor to drive the memory cell 104. The structure 100 may be operated by electrically coupling the gate electrode 106 to one terminal 120 and the memory electrode 118 to another terminal 122. By applying appropriate electrical signals to the terminals 120, 122, the structure 100 may be operated. Moreover, when the transistor 102 is positioned in a BEOL region, the wiring between the memory cell 104 and the transistor 102 may be shortened. This leads to a decrease in the latency in the programming speed of the structure 100.
As used herein, “deposition techniques” refer to the process of applying a material over another material. Exemplary techniques for deposition include, but not limited to, spin-on coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), or atomic layer deposition (ALD).
Additionally, “patterning techniques” include deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described pattern, structure, or opening. Exemplary examples of techniques for patterning include, but not limited to, wet etch photolithographic processes, dry etch photolithographic processes, or direct patterning processes.
Another layer of electrically conductive material may be formed over the ILD 108 using a deposition technique, including a CVD process. The electrically conductive material may be subsequently patterned using a patterning technique, including lithography and etching processes, to form the electrode 112. Even though the electrode 112 may appear as two discrete structures in
The dielectric layer 116 may be formed over the channel layer 114 by depositing an electrically insulative material using a deposition technique, including a CVD process, and subsequently patterned using a patterning technique, including lithography and etching processes. The dielectric layer 116 may be conformal and continuous, and may at least overlap the channel layer 114 and the electrode 112.
The memory electrode 118 may be laterally adjacent to the gate electrode 106 and at least over the distal corner of the electrode 112 from the gate electrode 106. Even though the memory electrode 118 may appear as two discrete structures in
Processing continues with forming terminals electrically connected to the gate electrode 106 and the memory electrode 118 to provide electrical signals for the operation of the structure 100. The terminals may be synonymous with the terminals 120, 122 in
The structure 200 may include two (2) bit cells 226 each having a 1T1R architecture. Each bit cell 226 may include a transistor 102 and a memory cell 104. Each transistor 102 may include a gate electrode 228, an electrode 110, and an electrode 112. The gate electrodes 228 may be partially in an ILD 108. The gate electrodes 228 and the electrodes 112 of the transistors 102 may be separated and electrically isolated from each other.
An exemplary method of forming the gate electrodes 228 may include forming an opening 230 through an electrically conductive material, such as the gate electrode 106 in
Additionally, the gate electrodes 228 may be electrically coupled to terminals 232, 234 to drive their corresponding RRAM cells 104 in their respective bit cells 226. Similarly, the memory electrodes 118 may be separated and electrically isolated from each other, and electrically coupled to terminals 236, 238, serving as memory cells 104 of the structure 200. In an embodiment of the disclosure, the structure 200 may have a mirror symmetry through the opening 230 and the electrode 110.
The structure 300 has a 1T1R architecture that includes a transistor 102 and a memory cell 104. Unlike the structure 100 in
In this embodiment, the material and thickness of the resistive layer 332 may vary depending on the design and process requirements of the structure 300. For example, the material of the resistive layer 332 need not necessarily include the same electrically insulative material as the dielectric layer 116, and the thickness of the resistive layer 332 may be thicker or thinner than the collective thickness of the dielectric layer 116 and the channel layer 114, even though the resistive layer 332 is illustrated to be thinner. The resistive layer 332 may include an electrically insulative material, for example, tantalum oxide, titanium oxide, hafnium oxide, aluminum oxide, or silicon oxide. The resistive layer 332 may be formed before or after the formation of the channel layer 114 and the dielectric layer 116 using a deposition technique, including a CVD process, and subsequently patterned using a patterning technique, including lithography and etching processes.
The structure 400 has a 1T1R architecture that includes a transistor 102 and a memory cell 404. Unlike the structure 100 in
The memory electrode 434 and the resistive layer 436 may be formed by a multi-step process. An exemplary method of forming the memory electrode 434 and the resistive layer 436 is described herein. An electrically conductive material may be deposited using a deposition technique, including a CVD process, and subsequently patterned using a patterning technique, including lithography and etching processes, to form the memory electrode 434. Thereafter, an electrically insulative material may be deposited using a deposition technique, including a CVD process, and subsequently patterned using a patterning technique, including lithography and etching processes, to form the resistive layer 436. The electrode 110 may be formed using similar processes as that of the memory electrode 434. The ILD 108 may be formed during or after forming the memory cell 404 using a deposition technique, including a CVD process.
Alternatively, the electrically conductive material of the memory electrode 434, the electrically insulative material of the resistive layer 436, and the electrically conductive material of the electrode 110 may be sequentially deposited using a deposition technique and a patterning technique may be performed to form the memory electrode 434, the resistive layer 436, and the electrode 110 concurrently.
The electrode 110, the resistive layer 436, and the memory electrode 434 may include similar widths between their respective side surfaces. For example, the side surfaces of the electrode 110, the resistive layer 436, and the memory electrode 434 may be substantially coplanar with each other on opposite sides of the memory cell 404.
As presented above, various embodiments of structures having 1T1R architecture for RRAM devices and methods of forming the same are presented. The RRAM devices may be arranged in a BEOL area of a semiconductor device and may include at least one bit cell having a transistor coupled to an RRAM cell. The RRAM device may include a common conductive element shared between the transistor and the RRAM cell as a transistor electrode and a memory electrode, respectively. The transistor may be an access transistor to drive the RRAM cell, and the RRAM cell may be capable of forming localized conductive links in a resistive layer between two memory electrodes. At least one electrode may include a corner and the corner may advantageously improve the device performance and reduce the device-to-device variability by substantially confining the formation of the conductive link to a region in the dielectric liner subjected to relatively stronger electrical fields.
The terms “top”, “bottom”, “over”, “under”, and the like in the description and the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the devices described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Additionally, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed by interposing the first and second features, such that the first and second features may not be in direct contact.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of features is not necessarily limited to those features but may include other features not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in an embodiment” herein do not necessarily all refer to the same embodiment.
In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”.
Furthermore, approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “approximately”, “about,” or “substantially” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value. In other instances, the approximating language may correspond to within normal tolerances of the semiconductor industry. For example, “substantially coplanar” means substantially in a same plane within normal tolerances of the semiconductor industry, and “substantially perpendicular” means at an angle of 90 degrees plus or minus a normal tolerance of the semiconductor industry.
While several exemplary embodiments have been presented in the above-detailed description of the device, it should be appreciated that a number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above-detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of features and methods of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.
