SUB-HARMONIC FREQUENCY CONVERSION DEVICE

Abstract

A sub-harmonic frequency conversion device includes: a voltage controlled oscillator for generating first to eighth oscillation frequency (LO) signals having a constant phase difference; a first mixer for performing a switching operation to mix the first to fourth LO signals having a phase difference of 90° and input signals, and outputting first IF signals; and a second mixer for performing a switching operation to mix the fifth to eighth LO signals having a phase difference of 90° and the input signals, and outputting second IF signals. Accordingly, the sub-harmonic frequency conversion device can use the low-frequency LO signal, and the power consumption can be reduced. In addition, because the mixers are implemented using a symmetric structure of the MOS transistors, the circuit configuration can be easily implemented.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIGS. 1 and 2 are waveform diagram illustrating a process of generating an LO signal according to the related art;

FIG. 3 is a schematic diagram of a conventional frequency conversion device using the LO signal shown in FIG. 1 or 2;

FIG. 4 is a block diagram of a frequency conversion device according to an embodiment of the present invention;

FIG. 5 is a detailed block diagram of the frequency conversion device according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a first mixer shown in FIG. 5;

FIG. 7 is a circuit diagram of a second mixer shown in FIG. 5; and

FIGS. 8A and 8B are graphs showing a simulation result of the frequency conversion device according to the present invention.

Claims

1. A sub-harmonic frequency conversion device comprising: a voltage controlled oscillator for generating first to eighth oscillation frequency (LO) signals having a constant phase difference;a first mixer for performing a switching operation to mix the first to fourth LO signals having a phase difference of 90° and input signals, and outputting first IF signals; anda second mixer for performing a switching operation to mix the fifth to eighth LO signals having a phase difference of 90° and the input signals, and outputting second IF signals.

2. The sub-harmonic frequency conversion device according to claim 1, wherein the first mixer is a passive mixer.

3. The sub-harmonic frequency conversion device according to claim 1, wherein the second mixer is a passive mixer.

4. The sub-harmonic frequency conversion device according to claim 2, wherein the first mixer includes:a first switching unit for switching on/off a positive input signal according to the first to fourth LO signals provided from the voltage controlled oscillator; anda second switching unit, connected in parallel to the first switching unit, for switching on/off a negative input signal according to the first to fourth LO signals provided from the voltage controlled oscillator.

5. The sub-harmonic frequency conversion device according to claim 3, wherein the second mixer includes:a third switching unit for switching on/off a positive input signal according to the fifth to eighth LO signals provided from the voltage controlled oscillator; anda fourth switching unit, connected in parallel to the third switching unit, for switching on/off a negative input signal according to the fifth to eighth LO signals provided from the voltage controlled oscillator.

6. The sub-harmonic frequency conversion device according to claim 4, wherein the first switching unit includes MOS transistors (M1 to M8);the positive input signal is applied to drains of the MOS transistors (M1, M3, M5, M7);any one of the first to fourth LO signals is applied to gates of the MOS transistors (M1, M7);an LO signal having a phase difference of 90° with respect to the LO signal applied to the gates of the MOS transistors (M1, M7) is applied to gates of the MOS transistors (M2, M6);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M1, M7) is applied to gates of the MOS transistors (M4, M5);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M2, M6) is applied to gates of the MOS transistors (M3, M8);a source of the MOS transistor (M1) is connected to a drain of the MOS transistor (M2);a source of the MOS transistor (M3) is connected to a drain of the MOS transistor (M4);a source of the MOS transistor (M5) is connected to a drain of the MOS transistor (M6); anda source of the MOS transistor (M7) is connected to a drain of the MOS transistor (M8).

7. The sub-carrier frequency conversion device according to claim 6, wherein the second switching unit includes MOS transistors (M21 to M28);the negative input signal is applied to drains of the MOS transistors (M21, M23, M25, M27);an LO signal identical to the LO signal applied to the gates of the MOS transistors (M1, M7) of the first switching unit is applied to gates of the MOS transistors (M21, M27);an LO signal having a phase difference of 90° with respect to the LO signal applied to the gates of the MOS transistors (M21, M27) is applied to gates of the MOS transistors (M26, M28);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M21, M27) is applied to gates of the MOS transistors (M24, M25);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M26, M28) is applied to gates of the MOS transistors (M22, M23);a source of the MOS transistor (M21) is connected to a drain of the MOS transistor (M22);a source of the MOS transistor (M23) is connected to a drain of the MOS transistor (M24);a source of the MOS transistor (M25) is connected to a drain of the MOS transistor (M26); anda source of the MOS transistor (M27) is connected to a drain of the MOS transistor (M28).

8. The sub-harmonic frequency conversion device according to claim 5, wherein the third switching unit includes MOS transistors (M31 to M38);the positive input signal is applied to drains of the MOS transistors (M31, M33, M35, M37);any one of the fifth to eighth LO signals is applied to gates of the MOS transistors (M31, M37);an LO signal having a phase difference of 90° with respect to the LO signal applied to the gates of the MOS transistors (M31, M37) is applied to gates of the MOS transistors (M32, M36);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M31, M37) is applied to gates of the MOS transistors (M34, M35);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M32, M36) is applied to gates of the MOS transistors (M33, M38);a source of the MOS transistor (M31) is connected to a drain of the MOS transistor (M32);a source of the MOS transistor (M33) is connected to a drain of the MOS transistor (M34);a source of the MOS transistor (M35) is connected to a drain of the MOS transistor (M36); anda source of the MOS transistor (M37) is connected to a drain of the MOS transistor (M38).

9. The sub-carrier frequency conversion device according to claim 8, wherein the fourth switching unit includes MOS transistors (M41 to M48);the negative input signal is applied to drains of the MOS transistors (M41, M43, M45, M47);an LO signal identical to the LO signal applied to the gates of the MOS transistors (M41, M47) of the third switching unit is applied to gates of the MOS transistors (M41, M47);an LO signal having a phase difference of 90° with respect to the LO signal applied to the gates of the MOS transistors (M41, M47) is applied to gates of the MOS transistors (M46, M48);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M41, M47) is applied to gates of the MOS transistors (M44, M45);an LO signal having a phase difference of 180° with respect to the LO signal applied to the gates of the MOS transistors (M46, M48) is applied to gates of the MOS transistors (M42, M43);a source of the MOS transistor (M41) is connected to a drain of the MOS transistor (M42);a source of the MOS transistor (M43) is connected to a drain of the MOS transistor (M44);a source of the MOS transistor (M45) is connected to a drain of the MOS transistor (M46); anda source of the MOS transistor (M47) is connected to a drain of the MOS transistor (M48).