Claims
- 1. A method of protecting an integrated circuit from over voltage, the method comprising:
accepting a voltage from a power supply input to the integrated circuit; accepting a pad voltage from an external voltage source; comparing the power supply voltage to a predetermined value; and using the pad voltage to generate a bias voltage for the integrated circuit when the power supply is below the predetermined value.
- 2. A method as in claim 1 wherein the generation of the bias voltage comprises:
coupling the pad voltage into a drain of a PMOS (P-channel Metal Oxide Semiconductor) device; and coupling the power supply voltage into a gate of the PMOS device.
- 3. A method as in claim 2 wherein using the pad voltage to generate a bias voltage for the integrated circuit further comprises:
coupling the drain of the PMOS device to the pad voltage; and using the source voltage of the PMOS device to couple the pad voltage to the bias voltage.
- 4. A method as in claim 2 wherein coupling the pad voltage into the drain of a MOS (Metal Oxide Semiconductor) device comprises:
providing the pad voltage to an input of a plurality of diode connected MOS devices; and coupling an output of the plurality of diode connected MOS devices to the drain of the MOS device.
- 5. A method for generating a bias voltage (bias_mid) from a pad voltage (Vpad), when a power supply (VDDO) is not present the method comprising:
providing VDDO to a first semiconductor device; providing bias-mid to the first semiconductor device such that the first semiconductor device will turn off when bias_mid−VDDO exceeds the threshold of the first semiconductor device; and using the turn off of the first semiconductor device to couple Vpad to bias_mid.
- 6. The method of claim 5 wherein using the turn off of the first semiconductor device to couple Vpad to bias_mid further comprises:
turning on a second semiconductor device and turning off a third semiconductor device which are coupled together thereby providing a turn on voltage for a fourth semiconductor device; and using the turn on of the fourth semiconductor device to couple Vpad to bias_mid.
- 7. A method for generating a voltage for biasing a device well, the method comprising:
providing a semiconductor device disposed between the device well and an input/output pad; and turning on the semiconductor device when VDDO is lower than the pad voltage (Vpad), thereby coupling Vpad to the device well.
- 8. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting an output enable signal; accepting a first input voltage VDDO; accepting a second input voltage VDDP; providing VDDP voltage to Bias_Mid if the output enable signal is at an enable value; and providing a voltage to bias_mid that is proportional to the pad voltage if the output enable signal is at a disable value.
- 9. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting a power supply voltage (VDDO); accepting a voltage VDDP; providing a bias voltage to Bias_Mid, the bias voltage in a range having a maximum value of VDDP+an offset voltage VT and a minimum value of VDDO−an offset voltage VTP, if VDDO is greater than a predetermined value; and providing a bias voltage to Bias_Mid that is proportional to Vpad if VDDO is not greater than a predetermined value.
- 10. A method as in claim 9 wherein VDDP is equal to VDDO.
- 11. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting a power supply voltage VDDO; accepting a voltage VSSC; providing a bias voltage to Bias_Mid, the bias voltage being in a range between VSSC+nVT and VDDO−Vat if VDDO is greater than a predetermined value; and providing a bias voltage to Bias_Mid, that is proportional to VPAD if VDDO is not greater than a predetermined value.
- 12. A method as in claim 11 wherein VSSC is equal to zero volts.
- 13. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting a power supply voltage VDDO; providing a voltage derived from VDDO to Bias_Mid if VDDC is greater than a predetermined value and providing a voltage derived from VPAD to Bias_Mid if VDDO is not greater than the predetermined value.
- 14. The method of claim 13 where the predetermined value is approximately 3.3 Volts.
- 15. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting a power supply voltage VDDO; accepting a second voltage VDDP; providing a voltage derived from VDDO and VDDP to Bias_Mid if VDDO and VDDP are greater than predetermined values; and providing voltage derived from VPAD to Bias_Mid if VDDO and VDDP are not greater than predetermined values.
- 16. A method for generating a bias voltage (bias_mid) using a bias circuit tie method comprising:
accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad; accepting a power supply voltage VDDO; accepting a second voltage VDDP; providing a voltage derived from VDDO or VDDP to Bias_Mid if VDDO or VDDP are greater than predetermined values; and providing voltage derived from VPAD to Bias_Mid if VDDO and VDDP are not greater than predetermined values.
- 17. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, said fourth bias voltage in a range having a maximum value of VSSC+nVT, and a minimum value of VDDO−VTp, when VDDO is greater than a predetermined value, and wherein nVT and VTp are offset voltages, and when VDDO is not greater than a predetermined value the fourth bias voltage is derived from the pad voltage;
- 18. An apparatus as in claim 17 wherein VSSC is equal to ground potential.
- 19. An apparatus as in claim 17 wherein nVT and VTp are the same.
- 20. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD), and wherein the fourth bias voltage is in a range having a maximum value of VDDO+VTp and a minimum value of VDDO−VTP when VDDO is greater than a predetermined value, where VT and VTp are offset voltages.
- 21. An apparatus as in claim 20 wherein VSSC is at ground potential.
- 22. An apparatus as in claim 20 wherein VT and VTp are the same offset voltages.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims priority from provisional application No. 60/260,582 entitled “Sub-Micron, high input voltage tolerant I/O circuit” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full.
[0002] This application also claims priority from provisional application No. 60/260,580 entitled “Sub-Micron, high input voltage tolerant I/O circuit with power management support” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full.
Provisional Applications (2)
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Number |
Date |
Country |
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60260580 |
Jan 2001 |
US |
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60260582 |
Jan 2001 |
US |