Claims
- 1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage, coupled to the gate of the second upper MOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, the fourth bias voltage being in a range, the range having a maximum value of VDDP+VT and a minimum value of (VDDO −VTp), where VDDP and VDDO are power supply voltages and VT and VTp are offset voltages.
- 2. The apparatus of claim 1 wherein VDDO and VDDP are the same power supply.
- 3. The apparatus of claim 1 wherein VT and VTp are the same offset voltages.
- 4. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPAD) when the pad is in an output disable mode, and said bias circuit providing a fixed fourth bias voltage to the gate of the first lower MOS device when the pad is in an output enable mode.
- 5. The apparatus of claim 4 wherein the fixed fourth bias voltage is VDDP.
- 6. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device equal to the voltage on the I/O pad (VPAD)when the pad is in an output disable mode, and where the third bias voltage to the gate of the second upper MOS device equal to a fixed voltage when the pad is in an output enabled mode; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device.
- 7. The apparatus of claim 6 wherein the fixed voltage is VDDC.
- 8. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (VPA), said fourth bias circuit comprising a capacitive voltage divider.
- 9. The apparatus of claim 8 wherein the capacitive voltage divider proportions the difference between a pad and power supply voltage to derive the fourth bias voltage, when a voltage provided to the pad is changing.
- 10. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an input/output (I/O) pad; an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (VDDO)and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad; a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential; a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device depending on the voltage on the I/O pad (VPAD) said third bias circuit comprising a capacitive voltage divider; and a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device.
- 11. The apparatus of claim 10 wherein the capacitive voltage divider proportions a difference in voltage at the pad and a power supply voltage to derive the third bias voltage when the pad is switching.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a divisional of allowed Application Ser. No. 10/043,788 filed Jan. 9, 2002, which claimed the benefit of the filing date of U.S. Provisional Application No. 60/260,582 entitled “Sub-Micron, high input voltage tolerant I/O circuit” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full, and is related to U.S. patent application Ser. No. 10/043,763, filed on Jan. 9, 2002.
[0002] This application also claims priority from provisional application No. 60/260,580 entitled “Sub-Micron, high input voltage tolerant I/O circuit with power management support” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full.
Provisional Applications (2)
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Number |
Date |
Country |
|
60260582 |
Jan 2001 |
US |
|
60260580 |
Jan 2001 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
10043788 |
Jan 2002 |
US |
Child |
10621005 |
Jul 2003 |
US |