Claims
- 1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:
an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices coupled between a power supply (VDDO) and an I/O pad; a lower pair of N-channel MOS devices (NMOS), coupled between the I/O pad and a ground potential; a first bias circuit providing a first bias voltage to the first upper PMOS device when the I/O pad is in an output mode and VDDO voltage otherwise; a second bias circuit providing a second bias voltage to the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise; a third bias circuit providing a first fixed voltage to the second upper PMOS device when VPAD is less than the VDDO voltage and a voltage equal to VPAD otherwise; and a fourth bias circuit providing a second fixed voltage when VPAD is less than a pre-determined value and a voltage higher than the second fixed voltage otherwise.
- 2. The apparatus of claim 1 further comprising a well biasing circuit which provides a well bias to the upper pair of PMOS devices.
- 3. The apparatus of claim 2 wherein the well biasing circuit provides a bias voltage of VDDO if a voltage on the I/O pad is less than VDDO and provides the voltage on the I/O pad as the bias voltage otherwise.
- 4. The apparatus of claim 1 further comprising:
a NMOS device having a drain coupled to VPAD; the NMOS device having a source coupled to core circuitry; and having the gate coupled to the fourth bias voltage.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a continuation of allowed application Ser. No. 10/043,788 filed Jan. 9, 2002, which claimed the benefit of the filing date of U.S. Provisional Application No. 60/260,582 entitled “Sub-Micron, high input voltage tolerant I/O circuit” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full, and is related to U.S. patent application Ser. No. 10/043,763, filed on Jan. 9, 2002.
[0002] This application also claims priority from provisional application No. 60/260,580 entitled “Sub-Micron, high input voltage tolerant I/O circuit with power management support” filed Jan. 9, 2001, which is hereby incorporated by reference as though set forth in full.
Provisional Applications (2)
|
Number |
Date |
Country |
|
60260582 |
Jan 2001 |
US |
|
60260580 |
Jan 2001 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
10043788 |
Jan 2002 |
US |
Child |
10621008 |
Jul 2003 |
US |