Claims
- 1. A power supply circuit coupled to a first voltage, a second voltage, and a control voltage, said power supply circuit comprising:a plurality of MOS transistors serially coupled between the first voltage and the second voltage, wherein said plurality of MOS transistors comprises both PMOS and NMOS transistors, wherein one of said plurality of MOS transistors is switchable in response to the control voltage, has a first current flowing terminal coupled to another of the plurality of MOS transistors, a second current flowing terminal coupled to the second voltage, and a control terminal coupled to the control voltage, and wherein the power supply circuit is configured to generate a third voltage at an output node when the control voltage is above a selected value and to generate a fourth voltage at the output node when the control voltage is below the selected value.
- 2. The power supply according to claim 1 wherein the first voltage is higher than the second voltage.
- 3. The power supply circuit according to claim 1 wherein the first voltage is a high voltage and the second voltage is a ground voltage.
- 4. The power supply circuit according to claim 3 wherein the control voltage is a substrate voltage of a substrate.
- 5. The power supply circuit according to claim 1 wherein the plurality of MOS transistors comprises:a first PMOS transistor having a source terminal coupled to the first voltage, a drain terminal coupled to the output node, and a gate terminal coupled to the second voltage; two diode-connected NMOS transistors serially coupled between the output node and a second node; a diode-connected PMOS transistor coupled between the second node and a third node; a second PMOS transistor having a source terminal coupled to the N well of said second PMOS transistor and to the third node, a gate terminal coupled to the control voltage, and a drain terminal coupled to the second voltage, said second PMOS transistor comprising the switchable MOS transistor.
- 6. The power supply circuit according to claim 1 wherein the output node is coupled to a first PMOS transistor and to a first NMOS transistor, wherein the first PMOS transistor and the first NMOS transistor are two of the plurality of serially-coupled MOS transistors.
- 7. The power supply circuit according to claim 1 wherein the plurality of MOS transistors comprises at least two NMOS transistors, and wherein each NMOS transistor is diode-connected.
- 8. The power supply circuit according to claim 1 wherein the switchable MOS transistor is a PMOS transistor.
Parent Case Info
This application is a divisional of and claims the benefit of U.S. application Ser. No. 08/882,564, filed Jul. 3, 1997, now U.S. Pat. No. 6,064,250, which claims the benefit of U.S. Provisional Application No. 60/022,724, filed Jul. 29. 1996. The disclosures of each application are incorportated herein by reference.
US Referenced Citations (47)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 463 545 |
Feb 1992 |
EP |
0 576 008 |
Dec 1993 |
EP |
0 669 619 A2 |
Feb 1995 |
EP |
Provisional Applications (2)
|
Number |
Date |
Country |
|
60/022724 |
Jul 1996 |
US |
|
60/022714 |
Jul 1996 |
US |