Superconductor logic and switching circuits

Abstract

Current controlled superconductor switches formed by reactive patterning or other fabrication techniques may be used to form logic circuits including OR, AND, NOR, NAND, and NOT gates, a circuit breaker or an analog-to-digital converter. Each switch contains a superconductor resistor electrically connected in parallel with a non-superconductor resistor. The superconductor resistor has a critical current I.sub.c, such that it exhibits no electrical resistance to current flow less than I.sub.c, and exhibits positive electrical resistance to current flow greater than or equal to I.sub.c. The switch can accordingly be toggled between two states (i.e. superconducting and non-superconducting) by suitably controlling the current flowing through the switch. This switching behaviour provides the basis for constructing logic gates and other digital circuit devices.

Description

FIELD OF THE INVENTION

This application pertains to electronic logic circuits and to a circuit breaker made with current controlled superconducting switches formed of high critical temperature superconductor materials. The logic circuits include OR, AND, NOR, NAND, and NOT gates, as well as an analog-to-digital converter, with encoder.

BACKGROUND OF THE INVENTION

Unlike most conventional metallic superconductors, oxide high critical temperature superconductor ("HT.sub.c S") materials (i.e. materials which exhibit superconducting characteristics at temperatures above liquid nitrogen temperature of 77 degrees Kelvin) have a large normal state resistivity. Typical resistivities of YBaCuO material at 100 degrees Kelvin (".degree. K") are of the order of 100 .mu..OMEGA.-cm, which is at least one order of magnitude higher than that of metallic superconductors. The large difference in resistance between the normal state and the superconducting state is suitable for making high critical temperature ("T.sub.c ") superconducting switches that are compatible with many kinds of electronic circuits.

If the temperature of a HT.sub.c S material exceeds that material's T.sub.c, then the material remains in a "normal" state in which it exhibits a large resistivity to an applied current. Similarly, if the current applied to a HT.sub.c S material exceeds the material's critical current ("I.sub.c "), then the material will also remain in the "normal" state aforesaid. In the normal state, an electrical current passing through the HT.sub.c S material establishes an electrical voltage across the material, due to the normal resistance exhibited by the material. But, if the temperature of a HT.sub.c S material does not exceed that material's T.sub.c ; and, if the current applied to the HT.sub.c S material does not exceed that material's I.sub.c, then the material switches to the superconducting state in which it exhibits essentially zero resistance to an applied current. In this application, the term "superconductor resistor" is used to refer to HT.sub.c S materials which are capable of exhibiting dual resistance states as aforesaid.

A HT.sub.c S material can be switched between the normal and superconducting states by modulating the current applied to the material. This is the basic principle of operation of a current controlled superconducting switch ("CCSS"). If the current applied to a CCSS device is less than I.sub.c, then the device is superconductive with zero resistance, and no voltage is developed across the device (i.e. the switch is "off"). But, if the current applied to the device exceeds I.sub.c, then the device switches to the normal resistive state and a voltage is developed across the device (i.e. the switch is turned "on"). A CCSS device can accordingly be constructed by electrically connecting a HT.sub.c S element in parallel with a fixed (i.e. non-superconducting) resistor element. An input current signal can be used to control the device's switching behaviour , with the voltage developed across the fixed resistor representing the output. When the input current signal is below I.sub.c of the HT.sub.c S element, all of the current flows through the HT.sub.c S element and no current flows through the fixed resistor so the voltage output across the fixed resistor is zero (i.e. the switch is "off"). If the input current signal exceeds the HT.sub.c S element's Ic, then the current is divided between the two circuit elements and a voltage develops across the fixed resistor (i.e. the switch is turned "on").

The present invention discloses how such CCSS devices can be adapted to the fabrication of logic gates, circuit breakers, or analog to digital converters, all of which are useful in the construction of low temperature digital electronic devices.

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment, the invention provides a logic inverter gate having an input current source I. A superconductor resistor is electrically connected to the current source. The superconductor resistor has a critical current I.sub.c, such that it exhibits a resistance of 0 ohms when I<I.sub.c and a resistance of R.sub.s ohms when I.gtoreq.I.sub.c. A first non-superconductor resistor is electrically connected in series with the superconductor resistor. The first non-superconductor resistor has a resistance of r ohms and develops an output voltage V.sub.out in response to current flow. A second non-superconductor resistor is electrically connected in parallel across the two series-connected resistors. The second non-superconductor resistor has a resistance of R ohms. The resistance values are selected such that r<<R<<R.sub.s. In operation, I<I.sub.c represents a first binary logical input signal to the inverter I.gtoreq.I.sub.c represents a second binary logical input signal, V.sub.out .apprxeq.I*r represents a first binary logical output signal, and V.sub.out .apprxeq.I*R*r/R.sub.s represents a second binary logical output signal.

The invention further provides a logic "NOR" gate having two input current sources I.sub.a and I.sub.b. A superconductor resistor is electrically connected to the current sources. The superconductor resistor has a critical current I.sub.c, such that it exhibits a resistance of 0 ohms when I.sub.a <I.sub.c and I.sub.b <I.sub.c, and a resistance of R.sub.S ohms when I.sub.a .gtoreq.I.sub.c or I.sub.b .gtoreq.I.sub.c. A first non-superconductor resistor is electrically connected in series with the superconductor resistor. The first non-superconductor resistor has a resistance of r ohms and develops an output voltage V.sub.out in response to current flow. A second non-superconductor resistor is electrically connected in parallel across the two series-connected resistors. The second non-superconductor resistor has a resistance of R ohms. The resistance values are selected such that r<<R<<R.sub.s. In operation, I.sub.a <I.sub.c or I.sub.b <I.sub.c represents a first binary logical input signal to the gate, I.sub.a .gtoreq.I.sub.c or I.sub.b .gtoreq.I.sub. c (or both I.sub.a .gtoreq.I.sub.c and I.sub.b .gtoreq.I.sub.c) represents a second binary logical input signal, V.sub.out .apprxeq.I*r represents a first binary logical output signal of the gate, and V.sub.out .apprxeq.I*R*r/R.sub.s represents a second binary logical output signal.

The invention further provides an logic "NAND" gate which may be driven by a plurality of current sources I.sub.k, where k=1, 2, . . . , n and n.gtoreq.2. A corresponding plurality of superconductor resistors are electrically connected in parallel with one another and to the current sources. Each superconductor resistor has a critical current I.sub.c, 0 ohms resistance when conducting current<I.sub.c, and a resistance of R.sub.s ohms when .SIGMA.I.sub.k >n*I.sub.c. A first non-superconductor resistor is electrically connected in series with the superconductor resistors. The first non-superconductor resistor has r ohms resistance and develops an output voltage V.sub.out in response to current flow therethrough. A second non-superconductor resistor is electrically connected in parallel across the previously mentioned resistors. The second non-superconductor resistor has a resistance of R ohms. The resistance values are selected such that r<<R<<R.sub.s. In operation, 0<I.sub.k <I.sub.c /n represents, for at least one value of k, a first binary logical input signal to the gate; I.sub.c <I.sub. k <(n+1)I.sub.c /n represents, for all values of k, a second binary logical input signal to the gate; V.sub.out .apprxeq.I*r represents a first binary logical output signal of the gate; and, V.sub.out .apprxeq.I*R*r/R.sub.s represents a second binary logical output signal of the gate.

The superconductor resistors may be superconducting films deposited on a substrate and patterned into small structures by reactive patterning, chemical etching, ion milling, lithography, or similar fabrication techniques.

The invention further provides a circuit breaker for preventing a current I flowing through a superconductor circuit having a normal (i.e. non-superconductive) resistive load r.sub.L from exceeding a critical current I.sub.c. A superconductor resistor is electrically connected to the current source and in series with the superconductor circuit. The superconductor resistor has a critical current I.sub.c, such that it exhibits a resistance of 0 ohms when I<I.sub.c and a resistance of R.sub.s ohms when I.gtoreq.I.sub.c. A non-superconductor resistor is electrically connected in parallel across the series-connected superconductor resistor and the electrical circuit. The non-superconductor resistor has a resistance of R.sub.L ohms. The resistance values are selected such that r.sub.L <<R.sub.L <<R.sub.s. The non-superconductor resistor may be a light emitting diode or an alarm device.

The invention further provides an analog to digital converter for converting an input analog current signal I to a digital voltage signal within a range of digital voltage signals V.sub.1, V.sub.2, . . . V.sub.n, with each of the digital voltage signals corresponding to a selected magnitude portion of the analog signal. A plurality of identical current controlled superconductor switches are used to form the analog to digital converter. Each switch comprises a superconductor resistor electrically connected in parallel with a non-superconductor resistor. The superconductor resistor has a critical current I.sub.c, such that it exhibits no electrical resistance to current flow less than I.sub.c, and exhibits positive electrical resistance to current flow greater than or equal to I.sub.c. The switches are arranged in a plurality of tiers R.sub.1, R.sub.2, . . . R.sub.n. The first tier R.sub.1 has a single switch; the second tier R.sub.2 has two switches electrically connected in parallel; the third tier R.sub.3 has three switches electrically connected in parallel, and so on with each successive tier R.sub.i having an integer number "i" of switches electrically connected in parallel. The tiers are electrically connected in series with one another, such that the digital voltage signal V.sub.1 is developed across the tier R.sub.1 when I.gtoreq.I.sub.c ; the digital voltage signal V.sub.2 is developed across the tier R.sub.2 when I.gtoreq.2*I.sub.c ; the digital voltage signal V.sub.3 is developed across the corresponding tier R.sub.3 when I.gtoreq.3*I.sub.c ; and each successive tier R.sub.i develops a corresponding digital voltage signal V.sub.i when I.gtoreq.i*I.sub.c.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electronic circuit schematic diagram of a current controlled superconducting switch ("CCSS") .

FIG. 2 is a graph showing input current (upper waveform) and output voltage (lower waveform) values for the CCSS of FIG. 1.

FIG. 3(a) is an electronic circuit schematic diagram of a logic "OR" gate constructed with a CCSS.

FIG. 3(b) is an electronic circuit schematic diagram of an alternative logic "OR" gate constructed with a CCSS.

FIG. 3(c) is an electronic circuit schematic diagram of a logic "AND" gate constructed with a CCSS.

FIG. 3(d) is an electronic circuit schematic diagram of an alternative logic "AND" gate constructed with a CCSS.

FIG. 3(e) is an electronic circuit schematic diagram of a logic "NOT" (i.e. inverter) gate constructed with a CCSS.

FIG. 3(f) is an electronic circuit schematic diagram of a logic "NOR" gate constructed with a CCSS.

FIG. 3(g) shows how a bias current may be applied to the "NOT" gate of FIG. 3(e).

FIG. 3(h) is an electronic circuit schematic diagram of a logic "NAND" gate constructed with a CCSS.

FIG. 3(i) is an electronic circuit schematic diagram of an "n" input logic "NAND" gate.

FIG. 4 is an electronic circuit schematic diagram of a current overdrive protection circuit breaker constructed with a CCSS.

FIG. 5(a) is an electronic circuit schematic diagram of an analog to digital converter constructed with CCSS elements.

FIG. 5(b) is an electronic circuit schematic diagram of an alternative analog to digital converter.

FIG. 6 is an electronic circuit schematic diagram of an analog to digital converter with a two-bit encoder.

FIG. 7 is a graph of output voltage for the "OR" circuits of FIGS. 3(a) and 3(b) for various values of input currents I.sub.a and I.sub.b.

FIG. 8 is a graph of output voltage for the "AND" circuits of FIGS. 3(c) and 3(d) for various values of input currents I.sub.a and I.sub.b.

FIG. 9 is a plot of the output voltage for the "NOR" gate of FIG. 3(f) for various values of input currents I.sub.a and I.sub.b.

FIG. 11 is a graph of output voltage as a function of a varying input current for the biased "NOT" circuit of FIG. 3(g).

FIG. 12 is a graph of output voltage at various input currents I.sub.a and I.sub.b for the "NAND" circuit of FIG. 3(h).

FIG. 13 is a graph of output voltage at various input currents I.sub.l . . . I.sub.n for the n-input "NAND" circuit of FIG. 3(i).

FIG. 14 is a graph of output voltages versus input current for the analog to digital convertor circuit of FIG. 5(a).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 depicts a current controlled superconducting switch ("CCSS") in which a reactively patterned HT.sub.c S "superconductor resistor" R.sub.s having a critical current I.sub.c is electrically connected in parallel with a fixed external load resistor R. The input signal I is an alternating current. The output is the voltage V.sub.out developed across R. If I<I.sub.c and if the temperature of HT.sub.c S superconductor resistor R.sub.s is kept at or below 77.degree. K., then all of the current will flow through resistor R.sub.s since it will be in the superconducting state at which it exhibits essentially zero resistance to electrical current flow. V.sub.out is zero in this case, corresponding to an "OFF" state. If I>I.sub.c, then R.sub.s switches to the normal (i.e. non-superconducting) state in which it exhibits normal resistance to electrical current flow. In this case, the input current flows through both of resistors R.sub.s and R. V.sub.out is non-zero in this case, corresponding to an "ON" state.

When HT.sub.c S resistor R.sub.s operates in the normal state the value of V.sub.out will depend upon the ratio of the resistance values of R.sub.s and R, i.e. V.sub.out .apprxeq.I*(R*R.sub.s)/(R.sub.s +R). In general, R.sub.s must be very large to exhibit a measurable switching behaviour. Ideally, one expects that R.sub.s =0.OMEGA. at temperatures of about 77.degree. K. However, the contact resistance of the metal leads used to establish electrical connection with the HT.sub.c S line structure has been found to be about 0.1.OMEGA. to 1.OMEGA. for a Au-YBaCuO contact (see "Characterization of bilayer-metal contacts to high T.sub.c superconducting films", Q.Y. Ma et al, J. Vac. Sci. Technol. A9(3) p. 390, 1991) . The normal state resistance of R.sub.s must be much larger than this value. Usually, one chooses R.sub.s to be in the range of 1.OMEGA. to 100 k.OMEGA. and R to be in the range of 0.1.OMEGA. to 1 times the normal resistance value of HT.sub.c S resistor R.sub.s. FIG. 2 shows input current and output voltage waveforms for a CCSS having R.sub.s =2.3 k.OMEGA., R=1.5 k.OMEGA. and I.sub.c =30 .mu.A. The input 1 kHz square wave (upper waveform in FIG. 2) generates a low current of 10 .mu.A and a high current of 150 .mu.A. As can be seen, the output voltage of the device (lower waveform) switches between zero and 0.14 volts at 77.degree. K. For a film with a large critical current density (over one million amperes per centimeter square) a smaller value of R.sub.s can be chosen for the switching measurement.

A CCSS can be adapted to form various logic circuits, as will now be described with reference to FIGS. 3(a) through 3(h). As depicted in FIG. 3(a), an "OR" gate may be formed by applying two separate input current signals I.sub.a and I.sub.b to a CCSS device of the type described above with reference to FIG. 1. (In FIGS. 3(a) through 3(h), R.sub.s denotes a resistor formed of HT.sub.c S material having a critical current I.sub.c, and R denotes a fixed, non-superconducting resistor.) As shown in FIG. 7, if either one or both of input signals I.sub.a or I.sub.b exceed I.sub.c, then the gate is "ON" (i.e. V.sub.out is non-zero). If both input signals I.sub.a and I.sub.b remain less than I.sub.c, then the gate is "OFF" (i.e. V.sub.out is zero).

FIG. 3(b) depicts an alternative "OR" gate formed by connecting fixed resistor R in series with HT.sub.c S resistor R.sub.s, and by applying two separate input current signals I.sub.a and I.sub.b to the gate. The input condition required to turn the gate "ON" is again I.sub.a or I.sub.b >I.sub.c, with the gate remaining "OFF" if both I.sub.a and I.sub.b <I.sub.c. Note that the output signal V.sub.out is the voltage developed across HT.sub.c S resistor R.sub.s in both the FIG. 3(a) and 3(b) embodiments. The following "truth table" summarizes the input and output conditions for the "OR" gates of FIGS. 3(a) and 3(b):

______________________________________Input OutputI.sub.a I.sub.b V.sub.out______________________________________0 0 01 0 10 1 11 1 1______________________________________ where a logical "0" input signal is represented by the condition that the input signal (i.e. I.sub.a or I.sub.b) is less than I.sub.c ; a logical "1" input signal is represented by the condition that the input signal exceeds I.sub.c ; a logical "0" output signal is represented by the condition that V.sub.out =zero, and a logical "1" output signal is represented by the condition that V.sub.out is non-zero.

The following equations provide a comparison of the input power ("P.sub.i ") and output power ("P.sub.o ") conditions for the "OR" gates of FIGS. 3 (a) and 3(b):

______________________________________For FIG. 3(a): V.sub.out .apprxeq. I*(R*R.sub.S)/(R+R.sub.S) .apprxeq. I*R P.sub.i = I.sup.2 *R P.sub.o = I.sup.2 *R*[R/(R+R.sub.S)].sup.2For FIG. 3(b): V.sub.out .apprxeq. I*R.sub.S P.sub.i = I.sup.2 *(R+R.sub.S) P.sub.o = I.sup.2 *R.sub.S______________________________________

Thus, for FIG. 3(a) the output to input power ratio is P.sub.o /P.sub.i =[R/(R+R.sub.s)].sup.2 ; for FIG. 3(b) the output to input power ratio is P.sub.o /P.sub.i =R/(R+R.sub.s); and, the matching power conditions (R=R.sub.s) are P.sub.o =1/4P.sub.i, and P.sub.o =1/2P.sub.i for FIGS. 3(a) and 3(b) respectively.

As depicted in FIG. 3(c), an "AND" gate may be formed by connecting a second HT.sub.c S resistor in parallel across a CCSS device. The second HT.sub.c S resistor has the same critical current I.sub.c as the HT.sub.c s resistor in the CCSS device. Two input current signals I.sub.a or I.sub.b are applied to the gate. The input condition required to turn the gate "ON" is I.sub.a +I.sub.b <2*I.sub.c. As shown in FIG. 8, if I.sub.a or I.sub.b <I.sub.c, but<2*I.sub.c, then the gate remains "OFF".

FIG. 3(d) depicts an alternative "AND" gate formed by connecting fixed resistor R in series with two parallel-connected HT.sub.c s resistors R.sub.s, and by applying two input current signals I.sub.a or I.sub.b. The input condition required to turn the gate "ON" is again I.sub.a +I.sub.b >2*I.sub.c, with the gate remaining "OFF" if I.sub.a or I.sub.b <I.sub.c and >2*I.sub.c. Note that the output signal V.sub.out is the voltage developed across the parallel-connected HT.sub.c S resistors in both the FIG. 3(c) and 3(d) embodiments. The following "truth table" summarizes the input and output conditions for the "AND" gates of FIGS. 3(c) and 3(d):

______________________________________Input OutputI.sub.a I.sub.b V.sub.out______________________________________0 0 01 0 00 1 01 1 1______________________________________ where a logical "0" input signal is represented by the condition that the input signal (i.e. I.sub.a or I.sub.b) is less than I.sub.c ; a logical "1" input signal is represented by the condition that the input signal exceeds I.sub.c, but does not exceed twice the value of I.sub.c ; a logical "0" output signal is represented by the condition that V.sub.out is zero, and a logical "1" output signal is represented by the condition that V.sub.out is non-zero.

As depicted in FIG. 3(e), a "NOT" (i.e. inverter) gate is formed by connecting a HT.sub.c S resistor R.sub.s in series with a small fixed resistor r, and by connecting a larger fixed resistor R in parallel across the two series-connected resistors. FIG. 9 is a graph of output voltage V.sub.out as a function of input current I for the circuit of FIG. 3(e). If r<<R<<R.sub.s, and if the input current signal I<<I.sub.c, then most of the input current flows through the circuit loop containing R.sub.s and an output voltage V.sub.out .apprxeq.I*r is developed across r (i.e. the device is "ON"). If I>>I.sub.c then most of the input current flows through the circuit loop containing R and a smaller output voltage V.sub.out .apprxeq.I*R*r/(R+R.sub.s +r).apprxeq.I*R*r/R.sub.s is developed across r (i.e. the device turns "OFF"). The following "truth table" summarizes the input and output conditions for the "NOT" gate of FIG. 3(e):

______________________________________ Input Output I V.sub.out______________________________________ 0 1 1 0______________________________________ where a logical "0" input signal is represented by the condition that the input signal I is less than I.sub.c ; a logical "1" input signal is represented by the condition that the input signal exceeds I.sub.c ; a logical "1" output signal is represented by the condition that V.sub.out has a first value I*r; a logical "0" output signal is represented by the condition that V.sub.out has a second value I*R*r/R.sub.s ; and r<<R<<R.sub.s.

As depicted in FIG. 3(f) a "NOR" gate is formed by applying two input current signals I.sub.a and I.sub.b to the "NOT" gate of FIG. 3(e). As shown in FIG. 10, if both input signals I.sub.a and I.sub.b remain less than I.sub.c, then the device turns "ON" (i.e. V.sub.out .apprxeq.Ir). If either one or both of input signals I.sub.a or I.sub.b exceeds I.sub.c, and if I.sub.a +I.sub.b <2*I.sub.c then the device turns "OFF" (i.e. V.sub.out .apprxeq.I*R*r/(R+R.sub.s +r).apprxeq.I*R*r/R.sub.s). The following "truth table" summarizes the input and output conditions for the "NOR" gate of FIG. 3(f):

______________________________________Input OutputI.sub.a I.sub.b V.sub.out______________________________________0 0 11 0 00 1 01 1 0______________________________________ where a logical "0" input signal is represented by the condition that the input signal (i.e. I.sub.a or I.sub.b) is less than I.sub.c ; a logical "1" input signal is represented by the condition that the input signal exceeds I.sub.c, but does not exceed twice the value of I.sub.c ; a logical "1" output signal is represented by the condition that V.sub.out has a first value I*r; a logical "0" output signal is represented by the condition that V.sub.out has a second value I*R*r/R.sub.s ; and r<<R<<R.sub.s.

In many potential applications a current or voltage bias is required to reduce power consumption and/or to obtain current gain. This is particularly so in the case of integrated logic circuits. FIG. 3(g) shows how a direct current ("DC") bias signal may be applied to the "NOT" gate of FIG. 3(e). Those skilled in the art will understand that the same technique can be employed with other logic gates constructed in accordance with the present invention. Referring to FIG. 3 (g) and 11, DC bias current I.sub.B is applied to the input of the "NOT" gate. I.sub.B is slightly less than the critical current I.sub.c of superconductor resistor R.sub.s. A small alternating current ("AC") signal i is applied to the "NOT" gate as an input signal. If the total applied current I=I.sub.B +i is less than I.sub.c, then the device remains "ON" (i e. V.sub.out .apprxeq.I*r) If I>I.sub.c, the device is "OFF" (i.e. V.sub.out .apprxeq.I*r*R/R.sub.s). By biasing the device as aforesaid one need only apply a very small current i as a trigger to switch the device "ON" and "OFF".

As depicted in FIG. 3(h), the FIG. 3(e) "NOT" gate is converted into a "NAND" gate by connecting a second HT.sub.c S resistor R.sub.s in parallel across the first HT.sub.c S resistor, and by applying two input current signals I.sub.a and I.sub.b to the resultant circuit. As shown in FIG. 12, if either one or both of input signals I.sub.a and I.sub.b remain less than I.sub.c, then the device remains "ON" (i.e. V.sub.out .apprxeq.I*r). If both input signals I.sub.a and I.sub.b exceed I.sub.c, and if I.sub.a +I.sub.b >2I.sub.c then the device turns "OFF" (i.e. V.sub.out .apprxeq.I*R*r/(R+R.sub.s +r).apprxeq.I*R*r/R.sub.s). The following "truth table" summarizes the input and output conditions for the "NAND" gate of FIG. 3(h):

______________________________________Input OutputI.sub.a I.sub.b V.sub.out______________________________________0 0 11 0 10 1 11 1 0______________________________________ where the logical input and output signal conditions are the same as those described above for the NOR gate of FIG. 3(f). Those skilled in the art will understand that the FIG. 3(e) "NOT" gate may alternatively be converted into a "NAND" gate by substituting for the first HT.sub.c S resistor a different HT.sub.c S resistor (not shown) having a critical current value of 2*I.sub.c, and by applying two input current signals I.sub.a and I.sub.b to the resultant circuit, as aforesaid.

More generally, as shown in FIG. 3(i), the FIG. 3(e) "NOT" gate may be converted into an "n" input "NAND" gate by substituting for the first HT.sub.c S resistor a plurality of "n" HT.sub.c S resistors each having a critical current value of I.sub.c and by applying a corresponding plurality of "n" input current signals I.sub.a, I.sub.b, I.sub.c. . . to the resultant device. A logic "0" or "OFF" input condition is defined as 0<I.sub.k <I.sub.c /n where k=1, 2, 3 . . . n. A logic "1" or "ON" input condition is defined as I.sub.c <I.sub.k <(n+1) I.sub.c /n. To perform the NAND function, the device's output must remain "ON" if any one or more of the input current signals I.sub.k is "OFF", and switch to the "OFF" state if all of the input current signals I.sub.k are "ON". Thus, the minimum total input current .SIGMA.I.sub.k required to switch the device "OFF" is n*I.sub.c. The FIG. 3(i) device satisfies these requirements. Assume for example that all but one of the input current signals I.sub.k are "ON" with the one remaining input current signal being "OFF". The total current .SIGMA.I.sub.k applied to the device is therefore .SIGMA.I.sub.k <(n-1)(n+1)I.sub.c /n+I.sub.c /n=(n.sup.2 -1)I.sub.c /n+I.sub.c /n=nI.sub.c. Accordingly .SIGMA.I.sub.k <nI.sub.c, so the HT.sub.c S resistors are not all switched to the normal state and the device's output remains "ON". But, as shown in FIG. 13, if all of the input current signals I.sub.k are "ON", then .SIGMA.I.sub.k >nI.sub.c so the HT.sub.c S resistors are all switched to the normal state and the device's output turns "OFF".

As depicted in FIG. 4, a circuit breaker may be formed by connecting a superconductor resistor R.sub.s in series with a effective resistance r.sub.L and by connecting a non-superconducting resistor R in parallel across the two series-connected resistors. The circuit breaker can be used to prevent excess current from flowing in r.sub.L which, in practice, represents the normal resistance of a superconducting device or the effective resistance of some other circuit which is to be protected. R can be a light emitting diode ("LED") or an alarm device. If r.sub.L <<R<<R.sub.s, then if the input current I exceeds I.sub.c (which could be the maximum current sustainable by the r.sub.L loop), R.sub.s switches to the normal resistive (i.e. non-superconducting) state. A portion of the input current then flows in the R loop, thus triggering the LED or alarm device. If I remains less than I.sub.c, then it flows through the R.sub.s -r.sub.L loop to drive the working device. It will be noted that the circuit breaker is self-resetting, in that the device switches repetitively between the normal and superconducting states, depending upon the variation of I relative to I.sub.c.

FIG. 5(a) depicts an analog to digital converter constructed with a plurality of identical CCSS devices of the type described above with reference to FIG. 1, each having a critical current I.sub.c and having a normal (i.e. non-superconducting) resistance R.sub.s. As may be seen, the circuit comprises a series-connected cascade of successively increasing numbers of parallel-connected CCSS devices. The circuit is constructed such that the first tier comprises a single CCSS device having a resistance value R.sub.1 =R.sub.s *R/(R.sub.s +R). The second tier comprises two parallel-connected CCSS devices identical to the device used to form the first tier, such that the resistance value of the second tier R.sub.2 =R.sub.1 /2. The third tier comprises three parallel-connected CCSS devices identical to the other CCSS devices, such that the resistance value of the third tier R.sub.3 =R.sub.1 /3. Further tiers could be added to extend the conversion range of the device, if desired, with the resistance value of the n.sup.th tier R.sub.n =R.sub.1 /n.

The input analog signal which is to be digitized is applied across the device, as shown. This causes a current I to flow through a normal (i.e. non-superconducting) fixed resistor R which is connected in series with the device. The digitized output signals V.sub.1, V.sub.2, V.sub.3, . . . V.sub.n are the voltages developed across each of the corresponding tiers R.sub.1, R.sub.2, R.sub.3, . . . R.sub.n respectively. In operation, as shown in FIG. 14, when the input current I reaches the critical current I.sub.c of CCSS tier R.sub.1, that tier switches from the superconducting state (in which V.sub.1 =0) to the normal resistivity state (in which V.sub.1 .apprxeq.I.sub.c *R if R.sub.s >>R). For convenience, the term V.sub.o is defined such that V.sub.o =I.sub.c *R. Provided I<2*I.sub.c, tiers R.sub.2, R.sub.3, . . . R.sub.n remain in the superconducting state (i.e. V.sub.2 =V.sub.3 . . . =V.sub.n =0 ). Accordingly, the voltage V.sub.a at point A=V.sub.1 =V.sub.o ; and, V.sub.b =V.sub.c =. . . =V.sub.n =0.

If the input current I reaches 2*I.sub.c, then CCSS tier R.sub.1 remains in the normal state and CCSS tier R.sub.2 switches from the superconducting state (in which V.sub.2 =0) to the normal resistivity state (in which V.sub.2 .apprxeq.2*I.sub.c *R/2=V.sub.o). In this case, V.sub.a =V.sub.1 +V.sub.2 =2*I.sub.c *R+V.sub.o =3*V.sub.o ; V.sub.b =V.sub.o ; and, V.sub.c . . . V.sub.n 0. Provided I<3*I.sub.c, tiers R.sub.3 . . . R.sub.n remain in the superconducting state (i.e. V.sub.3 . . . V.sub.n =0).

If the input current I reaches 3*I then CCSS tiers R.sub.1 and R.sub.2 remain in the normal state and CCSS tier R.sub.3 switches from the superconducting state (in which V.sub.3 =0) to the normal resistivity state (in which V.sub.3 .apprxeq.3*I.sub.c *R/3=V.sub.o). In this case, V.sub.c =V.sub.o ; V.sub.b =V.sub.2 +V.sub.3 =3*I.sub.c *R/2+V.sub.o =5*V.sub.o /2; V.sub.a =V.sub.1 +V.sub.b =3*V.sub.o +5*V.sub.o /2=11*V.sub.o /2; and, V.sub.d . . . V.sub.n =0. Provided I<4*I.sub.c any further tiers R.sub.4 . . . R.sub.n (not shown) remain in the superconducting state (i.e. V.sub.4 . . . V.sub.n =0).

In general, if the input current I reaches n*I.sub.c then CCSS tiers R.sub.1, R.sub.2 . . . R.sub.n-1 remain in the normal state and CCSS tier R.sub.n switches from the superconducting state (in which V.sub.n =0) to the normal resistivity state (in which V.sub.n =n*Ic*R/n=V.sub.o). If the input current I subsequently falls below n*I.sub.c, then CCSS tier R.sub.n switches from the normal resistivity state back to the superconducting state in which V.sub.n =0. Provided I>(n-1)*I.sub.c tiers R.sub.1, R.sub.2 . . . R.sub.n-1 remain in the normal resistivity state (i.e. V.sub.1 =V.sub.2 . . . =V.sub.n-1 =V.sub.o). Consequently, if I falls below 3*I.sub.c then CCSS tier R.sub.3 switches back to the superconducting state, such that V.sub.3 . . . V.sub.n =0, with V.sub.b =V.sub.2 =V.sub.o and V.sub.a =V.sub.1 +V.sub.2 =3*V.sub.o, provided I>2*I.sub.c. If I falls below 2*I.sub.c then CCSS tier R.sub.2 switches back to the superconducting state, such that V.sub.2 =V.sub.3 . . . V.sub.n =0 or V.sub.b =V.sub.c . . . V.sub.n =0, with V.sub.a =V.sub.1 =V.sub.o, provided I>I.sub.c. If I falls below Ic then CCSS tier R.sub.1 switches back to the superconducting state, such that V.sub.a =V.sub.b =V.sub.c . . . =V.sub.1 =V.sub.2 =V.sub.3 . . . V.sub.n =0. The following table summarizes the input and output conditions for the analog to digital converter of FIG. 5(a):

______________________________________I V.sub.a V.sub.b V.sub.c . . . V.sub.n______________________________________I.sub.c 1 0 0 . . . 02*I.sub.c 1 1 0 . . . 03*I.sub.c 1 1 1 . . . 0n*I.sub.c 1 1 1 . . . 1______________________________________ where a logical "0" output signal is represented by an output voltage of zero (or a small voltage value), and a logical "1" output signal is represented by a non-zero output voltage (or a large voltage value).

FIG. 5(b) illustrates an alternative technique for constructing an analog to digital converter using circuit components identical to those shown in FIG. 5(a), except that the CCSS devices are replaced by superconductor resistors which are connected in such a way that R.sub.1 =R.sub.s when I>I.sub.c, R.sub.2 =R.sub.s /2 when I>2*I.sub.c, . . . R.sub.n =R.sub.s /n when I>n*I.sub.c. The analog to digital conversion performance of the FIG. 5(b) circuit is very similar to that of the FIG. 5(a) circuit, except that the output voltage V.sub.o is defined as I.sub.c *R in the case of the FIG. 5(b) circuit.

The output of an analog to digital converter of the type shown in FIGS. 5(a) or 5(b) is a set of quantized voltage values (i.e. V.sub.a, V.sub.b, . . . V.sub.n). A code word [B.sub.0, B.sub.1, . . . B.sub.k ] can be assigned to further convert each input signal into a compact code associated uniquely with that signal. Devices capable of performing such conversion are called encoders and are typically characterized as having an n-bit-wide input and a k-bit-wide output, with n usually being greater than k.

FIG. 6 depicts an analog to digital converter with a two-bit encoder. The analog to digital converter portion of the FIG. 6 circuit is identical to the analog to digital converter described above with reference to FIG. 5(a). The analog input current is accordingly first converted into three digitized values V.sub.a, V.sub.b, and V.sub.c as previously explained. These three values are then each translated into a more compact, 2-bit code [B.sub.0, B.sub.1 ] by the encoder portion of the circuit, which consists of an AND gate like the one described above with reference to FIG. 3(c), and a NOT gate as described above with reference to FIG. 3(e).

The input of the AND gate is connected to both the V.sub.a and the V.sub.b terminals of the analog to digital converter. The output of the AND gate is the voltage B.sub.0 developed across the AND gate's non-superconductor resistor R. The input of the NOT gate is connected to the V.sub.c terminal of the analog to digital converter. The output of the NOT gate is the voltage B.sub.1 developed across the NOT gate's non-superconductor resistor r. Buffer resistors R.sub.o are inserted between the V.sub.a and V.sub.b terminals and the two inputs of the AND gate to prevent the majority of the current flow from bypassing the analog to digital converter through the encoder. The superconductor resistors R.sub.s in the AND gate are selected so that their critical current i.sub.c <<I.sub.c, where I.sub.c is the critical current of the superconductor resistors in the analog to digital converter.

In operation, R.sub.o >R>r and I.sub.c >>i.sub.c. For example, one may select R.sub.o =10*R and i.sub.c =I.sub.c /10. If I=0, then V.sub.a =V.sub.b =V.sub.c =B.sub.0 =B.sub.1 =0. If I rises slightly above I.sub.c (say I.apprxeq.1.1*I.sub.c), then V.sub.a =1 and V.sub.b =V.sub.c =0 (it being understood that "0" and "1" are logical variables corresponding to small and a large voltage values, respectively). One tenth of the input current flows through the AND gate, so I.sub.1 =0.1*I.sub.c =i.sub.c <2*i.sub.c. Therefore, B.sub.0 is low or "0". A small portion I.sub.2 of the input current I flows through the NOT gate, which is "ON", outputting a high voltage B.sub.1 =I.sub.2 *r (i.e. B.sub.1 ="1"). If the input current rises above 2*I.sub. c, then V.sub.b =V.sub.a =1, and V.sub.c =0. In this case I.sub.1 is well above 2*i.sub.c, so the AND gate turns "ON" and B.sub.0 =1. The NOT gate remains "ON" (i.e. B.sub.1 ="1"). If the input current rises above 3*I.sub.c, then V.sub.a =V.sub.b =V.sub.c =1. The current I.sub.2 becomes large, turning the NOT gate "OFF" (i.e. B.sub.1 ="0"). The AND gate remains "ON" (i.e. B.sub.0 ="1"). The following table summarizes the input and output conditions for the analog to digital converter/encoder of FIG. 6:

______________________________________Input A/D Converter Output Encoder OutputI V.sub.a V.sub.b V.sub.c B.sub.0 B.sub.1______________________________________0 0 0 0 0 0I.sub.c 1 0 0 0 12*I.sub.c 1 1 0 1 13*I.sub.c 1 1 1 1 0______________________________________

The encoder can be built by selecting different combinations of logic gates. In the example of the two-bit encoder of FIG. 6, an AND gate and a NOT gate are used to perform the digital encoding function. The same function may be performed by constructing the encoder with other logic gate combinations. For example, a two-input NAND gate could receive the V.sub.a and V.sub.c signals with the B.sub.1 output being tied directly to V.sub.b. The conversion range of the analog to digital converter can be extended as described above, if desired. The conversion range of the encoder can be similarly extended, using multiple input logic gates for the encoder (see for example the foregoing description of the manner in which the NOT gate of FIG. 3(e) may be converted into an "n" input "NAND" gate).

Conventional logic circuits are now commercially made of transistors which are typically semiconductor field effect transistors ("FET"). Each logic gate normally comprises several FETs. Formation of such a gate requires complicated circuit design, multilevel device structures, and very sophisticated fabrication technologies. Logic circuits constructed in accordance with the present invention may be formed with CCSS structures having only two components, namely a HT.sub.c S line and a fixed (non-superconducting) resistor (which can be a metal line). Such structures are single level planar devices which are relatively easy to fabricate. In view of the simplicity of the basic CCSS structure, it is expected that logic circuits could be integrated much more densely than can be achieved with conventional semiconductor integrated circuits or with conventional Josephson Junction type logic circuits.

The resistive loss of a HT.sub.c S material is much less than that of good metal for operating frequencies lower than 100 GHz (10.sup.11 Hertz). For most microwave applications (10-100 GHz), logic circuits constructed in accordance with the present invention should perform well. For higher frequency applications additional capacitor and inductor components would have to be included in the circuit, but this would necessitate analysis of and compensation for the impedances introduced by the additional components.

The normal state resistance of a HT.sub.c S element depends on the geometry of the material. For electronic applications, thin film HT.sub.c S materials are required. In-situ laser ablated YBCO films on MgO substrates have been successfully employed. Film deposition was carried out in a vacuum chamber with oxygen partial pressure of 100-200 mTorr. The substrate was kept at 750.degree.-800.degree. C. using a high temperature heater made by US Inc. An excimer pulse laser (248 nm) beam was focused onto a YBCO target with fluence of 1-3 J/cm.sup.2. The films showed critical temperature above 88.degree. K. and critical current density of greater than 1.times.10.sup.6 A/cm.sup.2 at 77.degree. K. Typical normal state resistivity of a film is about 0.1 m.OMEGA.-cm at 100.degree. K., corresponding to a sheet resistance of a few ohms per square measured by a four-point probe technique.

To operate as a switch, the normal state resistance of the HT.sub.c S material must match standard circuit resistance values, for example, a 50 .OMEGA. transmission line. This can be achieved by patterning the film into micron-sized striplines. Using a reactive patterning technique, such as that disclosed in "Novel method of patterning YBaCuO superconducting thin films", Q.Y. Ma et al Appl. Phys. Lett., 55, p. 896, (1989) various superconducting line structures with different lengths and widths have been fabricated. This method locally introduces Si into a YBCO film by a high temperature Si-YBCO reaction; this destroys the conductivity of the Si containing region. The technique is most effective for single level planar patterning. Prior to the YBCO film deposition, a thin layer of Si is evaporated onto an MgO substrate by electron-beam deposition. The Si film is patterned using conventional photolithography techniques. During the high temperature deposition of the YBCO film, the film above the Si patterned area becomes insulating due to the Si-YBCO interaction. The remaining areas define the superconducting structures. The resistances of the patterned structures were in the range of 10 .OMEGA.-100 k.OMEGA.. Those skilled in the art will understand that other fabrication techniques such as chemical etching, ion milling, lithography, etc. may be used to fabricate switch structures in accordance with the invention.

Logic circuits constructed in accordance with the present invention may be used to form superconducting digital electronic and/or superconductor-semiconductor hybrid circuits. Circuit breakers constructed in accordance with the present invention may be used to protect any low temperature electronic system including Josephson junction circuits, silicon integrated circuits operated at liquid nitrogen temperatures (77.degree. K.), liquid nitrogen cooled supercomputers, and so on.

As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.

Claims

1. A logic inverter gate comprising:

(a) an input current source I;

(b) a superconductor resistor electrically connected to said current source, said superconductor resistor having a critical current I.sub.c, having a resistance of 0 ohms when I<I.sub.c and having a resistance of R.sub.s ohms when I.gtoreq.I.sub.c ;

(c) a first non-superconductor resistor electrically connected in series with said superconductor resistor, said first non-superconductor resistor having a resistance of r ohms and developing an output voltage V.sub.out in response to current flow through said first non-superconductor resistor;

(d) a second non-superconductor resistor electrically connected in parallel across said series-connected resistors, said second non-superconductor resistor having a resistance of R ohms;

wherein:

(e) r<<R<<R.sub.s ; and,

(f) I<I.sub.c represents a first binary logical input signal to said gate, I.gtoreq.I.sub.c represents a second binary logical input signal to said gate, V.sub.out .apprxeq.I*r represents a first binary logical output signal of said gate, and V.sub.out .apprxeq.I*R*r/R.sub.s represents a second binary logical output signal of said gate.

2. A logic inverter gate as defined in claim 1, wherein:

(a) said input current source I comprises an input AC current signal i and a DC bias current I.sub.B ;

(b) I.sub.B is slightly less than I.sub.c ; and,

(c) i is selected such that I=I.sub.B +i>I.sub.c, or such that I=I.sub.B +i<I.sub.c.

3. A logic inverter gate as defined in claim 1, wherein said superconductor resistor is a superconducting film deposited on a substrate and patterned by reactive patterning.

4. A logic "NOR" gate comprising:

(a) first and second input current sources I.sub.a and I.sub.b ;

(b) a superconductor resistor electrically connected to said current sources, said superconductor resistor having a critical current I.sub.c, having a resistance of 0 ohms when I.sub.a <I.sub.c and I.sub.b <I.sub.c, and having a resistance of R.sub.s ohms when I.sub.a .gtoreq.I.sub.c or I.sub.b .gtoreq.I.sub.c ;

(c) a first non-superconductor resistor electrically connected in series with said superconductor resistor, said first non-superconductor resistor having a resistance of r ohms and developing an output voltage V.sub.out in response to current flow through said first non-superconductor resistor;

(d) a second non-superconductor resistor electrically connected in parallel across said series-connected resistors, said second non-superconductor resistor having a resistance of R ohms;

wherein:

(e) r<<R<<R.sub.s ; and,

(f) I.sub.a <I.sub.c and I.sub.b <I.sub.c represents a first binary logical input signal to said gate, I.sub.a .gtoreq.I.sub.c and/or I.sub.b .gtoreq.I.sub.c represents a second binary logical input signal to said gate, V.sub.out .apprxeq.I*r represents a first binary logical output signal of said gate, and V.sub.out .apprxeq.I*R*r/R.sub.s represents a second binary logical output signal of said gate, where I=I.sub.a +I.sub.b.

5. A logic "NOR" gate as defined in claim 4, further comprising a DC bias current I.sub.B electrically connected to said superconductor resistor, and wherein:

(a) I.sub.B <I.sub.c ;

(b) said first binary logical input signal is represented by I.sub.B +I.sub.a <I.sub.c and I.sub.B +I.sub.b <I.sub.c ; and,

(c) said second binary logical input signal is represented by I.sub.B +I.sub.a .gtoreq.I.sub.c and/or I.sub.B +I.sub.b .gtoreq.I.sub.c.

6. A logic "NOR" gate as defined in claim 4, wherein said superconductor resistors are superconducting films deposited on a substrate and patterned by reactive patterning.

7. A logic "NAND" gate comprising:

(a) a plurality of current sources I.sub.k, where k=1, 2, . . . , n and n.gtoreq.2;

(b) a corresponding plurality of superconductor resistors electrically connected in parallel with one another and to said current sources, said superconductor resistors each having a critical current I.sub.c, each having a resistance of 0 ohms when conducting a current less than I.sub.c, and each having a resistance of R.sub.S ohms when .SIGMA.I.sub.k .gtoreq.n*I.sub.c ;

(c) a first non-superconductor resistor electrically connected in series with said superconductor resistors, said first non-superconductor resistor having a resistance of r ohms and developing an output voltage V.sub.out in response to current flow through said first non-superconductor resistor;

(d) a second non-superconductor resistor electrically connected in parallel across said previously mentioned resistors, said second non-superconductor resistor having a resistance of R ohms;

wherein:

(e) r<<R<<R.sub.s /n; and,

(f) 0<I.sub.k <I.sub.c /n represents, for at least one value of k, a first binary logical input signal to said gate; I.sub.c <I.sub.k <(n+1)I.sub.c /n represents, for all values of k, a second binary logical input signal to said gate; V.sub.out .apprxeq.I*r represents a first binary logical output signal of said gate; and, V.sub.out .apprxeq.I*R*r*n/R.sub.s represents a second binary logical output signal of said gate where I=.SIGMA.I.sub.k.

8. A logic "NAND" gate as defined in claim 7, further comprising a DC bias current I.sub.B electrically connected to said superconductor resistors, and wherein:

(a) I.sub.B <n*I.sub.c ; and,

(b) said input current sources I.sub.k are selected such that I.sub.B +I.sub.k <I.sub.c for every value of k.

9. A logic "NAND" gate as defined in claim 7, wherein said superconductor resistors are superconducting films deposited on a substrate and patterned by reactive patterning.

10. A circuit breaker for preventing a current I flowing through a circuit having an effective resistance r.sub.L from exceeding a critical current I.sub.c, said circuit breaker comprising:

(a) a source of said current I;

(b) a superconductor resistor electrically connected in series with said circuit and connected to said current source, said superconductor resistor having a critical current I.sub.c, having a resistance of 0 ohms when I<I.sub.c and having a resistance of R.sub.s ohms when I.gtoreq.I.sub.c ; and,

(c) a non-superconductor resistor electrically connected in parallel across said series-connected superconductor resistor and superconductor circuit, said non-superconductor resistor having a resistance of R.sub.L ohms;

wherein r.sub.L <<R.sub.L <<R.sub.s.

11. A circuit breaker as defined in claim 10, wherein said superconductor resistor is a superconducting film deposited on a substrate and patterned by reactive patterning.

12. A circuit breaker as defined in claim 10, wherein said non-superconductor resistor is a light emitting diode.

13. A circuit breaker as defined in claim 10, wherein said non-superconductor resistor is an alarm device.

14. An analog to digital converter for representing the magnitude of an input analog current signal I as a plurality of binary voltage signals V.sub.1, V.sub.2, . . . V.sub.n, each of said voltage signals corresponding to a selected magnitude portion of said analog signal, said analog to digital converter comprising a plurality of current controlled superconductor switches, each of said switches comprising a superconductor resistor electrically connected in parallel with a non-superconductor resistor, said superconductor resistor having a critical current I.sub.c, having no electrical resistance to current flow less than I.sub.c and having positive electrical resistance to current flow greater than or equal to I.sub.c, said switches being arranged in a plurality of tiers R.sub.1, R.sub.2, . . . R.sub.n with said first tier R.sub.1 comprising one of said switches, said second tier R.sub.2 comprising two of said switches electrically connected in parallel, said third tier R.sub.3 comprising three of said switches electrically connected in parallel, and each successive tier R.sub.i comprising an integer number i of said switches electrically connected in parallel, said tiers being electrically connected in series, whereby said voltage signal V.sub.1 is developed across said tier R.sub.1, V.sub.1 is larger than a first threshold value when I.gtoreq.I.sub.c, and V.sub.1 .apprxeq.0 when I<I.sub.c, said voltage signal V.sub.2 is developed across said tier R.sub.2, V.sub.2 is larger than said threshold value when I.gtoreq.2*I.sub.c, and V.sub.2 .apprxeq.0 when I<2*I.sub.c said voltage signal V.sub.3 is developed across said corresponding tier R.sub.3, V.sub.3 is larger than said threshold value when I.gtoreq.3*I.sub.c, and V.sub.3 .apprxeq.0 when I<3*I.sub.c and each successive tier R.sub.i develops a corresponding voltage signal V.sub.i which is larger than said threshold value when I.gtoreq.i*I.sub.c.

15. An analog to digital converter as defined in claim 14, further comprising an encoder for encoding said voltage signals V.sub.1, V.sub.2, . . . V.sub.n, as coded signals B.sub.0, B.sub.1, . . . B.sub.k, where k<n.

16. An analog to digital converter for representing the magnitude of an input analog current signal I as a plurality of binary voltage signals V.sub.1, V.sub.2, . . . V.sub.n, each of said voltage signals corresponding to a selected magnitude portion of said analog signal, said analog to digital converter comprising a plurality of superconductor resistors each having a critical current I.sub.c, having no electrical resistance to current flow less than I.sub.c and having positive electrical resistance to current flow greater than or equal to I.sub.c, said superconductor resistors being arranged in a plurality of tiers R.sub.1, R.sub.2, . . . R.sub.n with said first tier R.sub.1 comprising one of said superconductor resistors, said second tier R.sub.2 comprising two of said superconductor resistors electrically connected in parallel, said third tier R.sub.3 comprising three of said superconductor resistors electrically connected in parallel, and each successive tier R.sub.i comprising an integer number i of said superconductor resistors electrically connected in parallel, said tiers being electrically connected in series, whereby said voltage signal V.sub.1 is developed across said tier R.sub.1, V.sub.1 is greater than a first threshold value when I.gtoreq.I.sub.c, and V.sub.1 .apprxeq.0 when I<I.sub.c said digital voltage signal V.sub.2 is developed across said tier R.sub.2, V.sub.2 is greater than said first threshold value when I.gtoreq.2*I.sub.c, and V.sub.1 .apprxeq.0 when I<2*I.sub.c, said digital voltage signal V.sub.3 is developed across said corresponding tier R.sub.3, V.sub.3 is greater than said first threshold value when I.gtoreq.3*I.sub.c, and V.sub.3 .apprxeq.0 when I<3*I.sub.c, and each successive tier R.sub.i develops a corresponding digital voltage signal V.sub.i which is greater than said first threshold value when I.gtoreq.i*I.sub.c.

17. An analog to digital converter as defined in claim 16, further comprising an encoder for encoding said voltage signals V.sub.1, V.sub.2, . . . V.sub.n, as coded signals B.sub.0, B.sub.1, . . . B.sub.k, where k<n.