Patent Application
20200412089
The disclosures herein relate to a surface emitting laser.
A vertical cavity surface emitting laser (VCSEL), which is also referred to as a surface emitting laser, has two reflector layers and an active layer interposed between the reflector layers disposed over a semiconductor substrate, and emits light in the direction perpendicular to the surface of the semiconductor substrate. A surface emitting laser has a current confinement structure that is made by forming a mesa with the active layer and the reflector layers and by selectively oxidizing a portion of the reflector layers of the mesa to form an oxide layer (see Patent Document 1, for example).
The surface emitting laser as described above is made by processing the surface of a semiconductor substrate. Such a surface has a mesa and electrode pads formed thereon, so that the top surface of a surface emitting laser chip has surface irregularities. In the case in which the elevation of the top surface varies from position to position on a surface emitting laser chip, the surface emitting laser chip may be inclined when held by a collet for transfer. As a result, the portion for transmitting laser light may be damaged, or transfer may not be completed as desired.
Accordingly, there may be a need for a surface emitting laser that is not inclined when held by a collet at the time of transferring the surface emitting laser.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2019-33210
According to an embodiment, a surface emitting laser includes a substrate, semiconductor layers including a lower contact layer, a lower reflector layer, an active layer, an upper reflector layer, and an upper contact layer which are laminated, in the order named, on the substrate, a light transmitting window configured to transmit laser light from the semiconductor layers, a first electrode pad connected to the upper contact layer, a second electrode pad connected to the lower contact layer, a first dummy pad, and a second dummy pad, wherein the first electrode pad, the second electrode pad, the first dummy pad, and the second dummy pad are disposed on the semiconductor layers at a place different from the light transmitting window, and wherein the substrate is classified into a first region, a second region, a third region, and a fourth region by both a straight line extending in a first direction passing through a center of the substrate in a plan view and a straight line extending in a second direction perpendicular to the first direction and passing through the center of the substrate, the first electrode pad being situated in the first region, the second electrode pad being situated in the second region, the first dummy pad being situated in the third region, and the second dummy pad being situated in the fourth region.
According to the present disclosures, a surface emitting laser is prevented from being inclined when held by a collet at the time of transferring the surface emitting laser.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
Embodiments will be described in the following.
Embodiments of the present disclosures will be listed and described first. In the following description, the same or corresponding elements are referred to by the same reference numerals, and a duplicate description thereof will be omitted.
[1] According to an embodiment of the present disclosures, a surface emitting laser includes a substrate, semiconductor layers including a lower contact layer, a lower reflector layer, an active layer, an upper reflector layer, and an upper contact layer which are laminated, in the order named, on the substrate, a light transmitting window configured to transmit laser light from the semiconductor layers, a first electrode pad connected to the upper contact layer, a second electrode pad connected to the lower contact layer, a first dummy pad, and a second dummy pad, wherein the first electrode pad, the second electrode pad, the first dummy pad, and the second dummy pad are disposed on the semiconductor layers at a place different from the light transmitting window, wherein the substrate is classified into a first region, a second region, a third region, and a fourth region by both a straight line extending in a first direction passing through a center of the substrate in a plan view and a straight line extending in a second direction perpendicular to the first direction and passing through the center of the substrate, the first electrode pad being situated in the first region, the second electrode pad being situated in the second region, the first dummy pad being situated in the third region, and the second dummy pad being situated in the fourth region.
This arrangement prevents a surface emitting laser from being inclined when held by a collet at the time of transferring the surface emitting laser.
[2] A surface emitting laser includes a substrate, semiconductor layers including a lower contact layer, a lower reflector layer, an active layer, an upper reflector layer, and an upper contact layer which are laminated, in the order named, on the substrate, a light transmitting window configured to transmit laser light from the semiconductor layers, a first electrode pad connected to the upper contact layer, a second electrode pad connected to the lower contact layer, a first dummy pad, and a second dummy pad, wherein the first electrode pad, the second electrode pad, the first dummy pad, and the second dummy pad are disposed on the semiconductor layers at a place different from the light transmitting window, and wherein the light transmitting window is situated between the first dummy pad and the second dummy pad.
This arrangement prevents a surface emitting laser from being inclined when held by a collet at the time of transferring the surface emitting laser.
[3] The first dummy pad and the second dummy pad are an oblong rectangular shape, wherein a length of a short side of the oblong rectangular shape is greater than or equal to 5 micrometers and smaller than or equal to 40 micrometers, and wherein a length of a long side of the oblong rectangular shape is greater than or equal to 80 micrometers and smaller than or equal to 100 micrometers.
This arrangement allows the first dummy pad and the second dummy pad to come in contact with the hold face of a collet, thereby preventing a surface emitting laser from being inclined when held by the collet.
[4] A plurality of the noted first dummy pads are provided, wherein a length of the first dummy pad in the first direction ranges from 20 micrometers to 40 micrometers, and wherein the plurality of first dummy pads are aligned in the second direction perpendicular to the first direction.
This arrangement prevents a surface emitting laser from being inclined when held by a collet.
[5] A distance from an edge of the substrate to the edge of the first dummy pad that is closest to the edge of the substrate is greater than or equal to 20 micrometers and less than or equal to 50 micrometers.
This arrangement prevents a surface emitting laser from being inclined when held by a collet.
In the following, an embodiment of the present disclosures will be described in detail, but the present embodiments are not limited to those disclosed herein. In the present application, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are orthogonal to each other. The plane that includes the X1-X2 direction and the Y1-Y2 direction is referred to as an XY plane. The plane that includes the Y1-Y2 direction and the Z1-Z2 direction is referred to as a YZ plane. The plane that includes the Z1-Z2 direction and the X1-X2 direction is referred to as a ZX plane.
A surface emitting laser that is inclined when held by a collet at the time of transferring the surface emitting laser will first be described by referring to a surface emitting laser chip 10 illustrated in
The surface emitting laser chip 10 has semiconductor layers 21 formed on a substrate 20 made of GaAs. A mesa 30 comprised of the semiconductor layers 21 is formed by processing the semiconductor layers 21. An insulating film 22 is formed on the semiconductor layers 21, on the lateral surface of the mesa 30, and the like. A lower DBR layer, an active layer, and an upper DBR layer (now shown) are formed in the mesa 30. A p electrode 41 having a ring shape is formed around the light transmitting window 31 on the upper surface of the mesa 30. An n electrode 51 having an arc shape is formed around the mesa 30. The surface emitting laser receives current that flows between the p electrode 41 and the n electrode 51, thereby emitting laser light from the light transmitting window 31 situated on the top surface of the mesa 30 in the direction perpendicular to the surface of the substrate 20, as illustrated by a dashed-line arrow.
The p electrode 41 is connected to a p electrode pad 43 via an interconnect 42, and the n electrode 51 is connected to an n electrode pad 53 via an interconnect 52. The p electrode pad 43 and the n electrode pad 53 are used for wire bonding connections or the like, and, thus, are required to have a suitable size. Their thickness is set to 1.7 micrometers.
In the example illustrated in
Accordingly, there is a need for a surface emitting laser that is not inclined when held by a collet at the time of transferring the surface emitting laser chip.
In the following, a surface emitting laser according to the present embodiment will be described with reference to
The surface emitting laser chip 110 of the present embodiment has semiconductor layers 21 formed on a substrate 20 made of GaAs. A mesa 30 comprised of the semiconductor layers 21 is formed by processing the semiconductor layers 21. The semiconductor layers 21 are comprised of a first lower DBR layer, a lower contact layer, a second lower DBR layer, an active layer, an upper DBR layer, and an upper contact layer formed on the substrate 20, as will be described later. In the present application, the second lower DBR layer or a set of the first lower DBR layer and the second lower DBR layer is referred to as a lower reflector layer, and the upper DBR layer is referred to as an upper reflector layer.
An insulating film 22 is formed on the semiconductor layers 21, on the lateral surface of the mesa 30, and the like. The lower DBR layer, the active layer, and the upper DBR layer (not shown in
The p electrode 41 is connected to a p electrode pad 43 via an interconnect 42, and the n electrode 51 is connected to an n electrode pad 53 via an interconnect 52. A groove is formed around the mesa 30. The semiconductor layers 21 situated outside the groove are referred to as a terrace of the semiconductor layers 21. The p electrode pad 43 and the n electrode pad 53 are formed on the terrace. The p electrode pad 43 and the n electrode pad 53 are used for wire bonding connections or the like, and, thus, are required to have a suitable size. For example, they are a circular shape with a diameter of 100 micrometers, and has a height of 1 to 4 micrometers above the upper surface of the terrace of the semiconductor layers 21, which is more preferably in the range of 1.4 micrometers to 1.7 micrometers. In the present application, the p electrode pad 43 may sometimes be referred to as a first electrode pad, and the n electrode pad 53 may sometimes be referred to as a second electrode pad.
The surface emitting laser of the present embodiment has a first dummy pad 161 and a second dummy pad 162. The first dummy pad 161 and the second dummy pad 162 have a height, above the upper surface of the terrace of the semiconductor layers 21, which is in the range of 1 to 4 micrometers and preferably in the range of 1.4 to 1.7 micrometers, and are substantially the same thickness as the p electrode pad 43, the n electrode pad 53, and the like.
The p electrode pad 43, the n electrode pad 53, the first dummy pad 161, and the second dummy pad 162 are formed on the insulating film on the semiconductor layers 21 at a different place from the light transmitting window 31.
The height of the upper surface of the p electrode pad 43 above the upper surface of the terrace semiconductor layers 21 is at least 0.5 micrometers higher than the height of the upper surface of the p electrode 41. Similarly, the height of the upper surface of the n electrode pad 53, the first dummy pad 161, and the second dummy pad 162 with reference to the upper surface of the terrace semiconductor layers 21 is at least 0.5 micrometers higher than the height of the upper surface of the p electrode 41. Making the upper surfaces of the electrode pads and the dummy pads higher than the p electrode 41 may prevent the light transmitting window 31 and the p electrode 41 from coming in contact with a collet when the surface emitting laser is held by the collet. Preventing such a contact serves to prevent damage to the light transmitting window 31 and to the p electrode 41.
Differences in height between the upper surfaces of the p electrode pad 43, the n electrode pad 53, the first dummy pad 161, and the second dummy pad 162 are preferably less than or equal to 3 micrometers. This arrangement allows the first dummy pad 161 and the second dummy pad 162 to come in contact with the hold face of a collet, thereby preventing a surface emitting laser from being inclined when held by the collet. The first dummy pad 161 and the second dummy pad 162 are preferably a metal layer having a thickness of 1 micrometer or more formed on the insulating film 22. This arrangement prevents an impact caused by the collet coming in contact with the dummy pads from causing damage to the insulating film 22.
The substrate 20 serving as a basis for the surface emitting laser chip 110 of the present embodiment is a square or oblong rectangular shape.
The substrate 20 serving as a basis for the surface emitting laser chip 110 may be a square with a side of 200 micrometers to 300 micrometers, for example. As illustrated in
The top right region among the four classified regions is referred to as a first region 111a. The remaining regions are referred to as a second region 111b, a third region 111c, and a fourth region 111d in this order in a counterclockwise direction. In the present embodiment, the p electrode pad 43 is disposed in the first region 111a on the surface of the surface emitting laser chip 110, and the n electrode pad 53 is disposed in the second region 111b. The first dummy pad 161 is disposed in the third region 111c, and the second dummy pad 162 is disposed in the fourth region 111d. The term “plan view” refers to a view that is taken from above the substrate 20 or the surface emitting laser chip 110.
The mesa 30 and the light transmitting window 31 are positioned between the third region 111c and the fourth region 111d, so that the mesa 30 and the light transmitting window 31 are situated between the first dummy pad 161 and the second dummy pad 162. The first dummy pad 161 and the second dummy pad 162 are formed such that the Y1-Y2 direction coincides with the lengthwise direction, and the X1-X2 direction coincides with the widthwise direction.
In the example illustrated in
As illustrated in
As illustrated in
In the present embodiment, the width Wx1 and the width Wx2, which are the short sides of oblong rectangles, are preferably greater than or equal to 5 micrometers and less than or equal to 40 micrometers. Excessively narrow widths Wx1 and Wx2 may cause the first dummy pad 161 and the second dummy pad 162 to be damaged upon coming in contact with the collet 70. Further, the mesa 30 is present on the X2 side of the first dummy pad 161 and on the X1 side of the second dummy pad 162, so that there is a limit to the extent to which the widths are increased.
The width Wy1 and the width Wy2, which are the long sides of oblong rectangles, are preferably greater than or equal to 80 micrometers and less than or equal to 100 micrometers. Excessively narrow widths Wy1 and Wy2 may cause the collect to fail to come in proper contact with the dummy pads when the position of the collet for holding is misaligned. Further, the n electrode pad 53 is present on the Y1 side of the first dummy pad 161, and the p electrode pad 43 is present on the Y1 side of the second dummy pad 162, so that there is a limit to the extent to which the widths are increased.
In the present embodiment, as illustrated in
In the following, the structural details of the surface emitting laser according to the present embodiment will be described.
The upper DBR layer 125 has an oxidized region 126a that is made by oxidizing part of the layers constituting the upper DBR layer 125. Upon the formation of the oxidized region 126a, the unoxidized region serves as an aperture region 126b. Accordingly, the surface emitting laser has a current confinement structure 126 comprised of the oxidized region 126a and the aperture region 126b. The oxidized region 126a is made by oxidizing a mesa 30 from the perimeter thereof. The oxidized region 126a contains aluminum oxide (Al2O3), for example, and has an insulating property, thereby conducting less current than the aperture region 126b. The aperture region 126b, which more readily conducts current than the oxidized region 126a, thus serves as a current path. Use of the current confinement structure 126 as described above allows current to be efficiently injected. In the present embodiment, the diameter of the aperture region 126b is 7.5 μm, for example.
The substrate 20 may be a semiconductor substrate made of gallium arsenide (GaAs) having a semi-insulating property, for example. A buffer layer made of GaAs and AlGaAs may be disposed between the substrate 20 and the first lower DBR layer 121.
The first lower DBR layer 121, the second lower DBR layer 123, and the upper DBR layer 125 are a multilayer semiconductor film in which AlxGa1-xAs (x=0.90) and AlyGa1-yAs (y=0.1) with an optical film thickness of λ/4 are alternately laminated. The first lower DBR layer 121 is an i-type semiconductor layer with no dopant impurities. The second lower DBR layer 123 is an n-type semiconductor layer, which is doped with silicon (Si) serving as an impurity at a concentration of 7×1017 cm−3 or more and 4×1018 cm−3 or less, for example. The upper DBR layer 125 is a p-type semiconductor layer, which is doped with zinc (Zn) serving as an impurity at a concentration of 1×1018 cm−3 or more and 2×1019 cm−3 or less, for example.
The lower contact layer 122 is approximately 500 nm in thickness and made of n-type AlxGa1-xAs (x=0.1) that is doped with Si serving as an impurity at a concentration of 2×1018 cm−3, for example. The upper contact layer 127 is approximately 200 nm in thickness and made of p-type (x=0.16) that is doped with Zn serving as an impurity at a concentration of 1×1019 cm−3, for example.
The active layer 124 has a multiple quantum well (MQW) structure in which InyGa1-yAs (y=0.107) layers and AlxGa1-xAs (x=0.3) layers are alternately laminated, for example, providing an optical gain. It may be noted that the substrate 20, the first lower DBR layer 121, the lower contact layer 122, the second lower DBR layer 123, the active layer 124, the upper DBR layer 125, and the upper contact layer 127 may be made of different compound semiconductors from those noted above.
The mesa 30 is constituted by the second lower DBR layer 123, the active layer 124, the upper DBR layer 125, and the upper contact layer 127. Specifically, the second lower DBR layer 123, the active layer 124, the upper DBR layer 125, and the upper contact layer 127 are removed around the area for erecting the mesa 30 to form a groove 32, thereby forming the mesa 30 constituted by the semiconductor layers. The height of the mesa 30 is greater than or equal to 4.5 μm and less than or equal to 5.0 μm, for example. The width of the top face is 30 μm, for example. The width of the groove 32 is 20 micrometers, for example. The mesa 30 has the active layer 124, the upper DBR layer 125, and the upper contact layer 127 at the center thereof.
An insulating film 130 is formed on the semiconductor layers at the places including the upper surface and lateral surface of the mesa 30. The insulating film 130 is made of silicon nitride (SiN), silicon oxynitride (SiON), or the like.
A p electrode 41 is formed on the upper contact layer 127 at the top of the mesa 30. An n electrode 51 is formed on the lower contact layer 122 constituting the bottom face of the groove 32. An interconnect 42 connected to a p electrode pad 43 is disposed on the p electrode 41 at the top of the mesa 30. An interconnect 52 connected to an n electrode pad 53 is disposed on the n electrode 51 situated on the bottom face of the groove 32.
The p electrode 41 is made of gold-zinc (AuZn) or the like, and has a thickness of approximately 150 nanometers, for example. The n electrode 51 is made of a film in which gold (Au), germanium (Ge), and nickel (Ni) are laminated, for example, and has a thickness of approximately 200 nanometers, for example. The interconnect 42, the interconnect 52, the p electrode pad 43, the n electrode pad 53, the first dummy pad 161, and the second dummy pad 162 are made of a metal such as Au, for example.
In the surface emitting laser of the present embodiment, bonding wires (not shown) or the like are connected to the p electrode pad 43 and the n electrode pad 53 to inject current into the surface emitting laser. Light emitted by the active layer 124 upon the injection of current oscillates in the resonator constituted by the first lower DBR layer 121, the second lower DBR layer 123, and the upper DBR layer 125, and then comes out of the light transmitting window 31 as a laser beam in the Z1 direction indicated by a dashed-line arrow.
In the following, a variation of the surface emitting laser according to the present embodiment will be described. The surface emitting laser of the present embodiment may be such that a plurality of first dummy pads 161 are provided as illustrated in
Further, the surface emitting laser of the present embodiment may be such that a plurality of first dummy pads 164 are aligned in the Y1-Y2 direction as illustrated in
Although one or more embodiments have heretofore been described, any particular embodiments are non-limiting, and various variations and modifications may be made without departing from the scopes defined by the claims.
The present application is based on and claims priority to Japanese patent application No. 2019-122050 filed on Jun. 28, 2019, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-122050 | Jun 2019 | JP | national |
