BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a conventional PCI Express switch network;
FIG. 2 is a block diagram of a conventional PCI Express switch;
FIG. 3A is a block diagram of an upstream PCI-PCI bridge in a conventional PCI Express switch;
FIG. 3B is a block diagram of a downstream PCI-PCI bridge in a conventional PCI Express switch;
FIG. 4 is a block diagram of an ASI network;
FIG. 5 is a block diagram of a route complex side PCI Express-ASI bridge of the ASI network;
FIG. 6 is a block diagram of a downstream PCI-PCI bridge in a route complex side PCI Express-ASI bridge;
FIG. 7 is a block diagram of a peripheral device side PCI Express-ASI bridge of the ASI network;
FIG. 8 is a block diagram of an upstream PCI-PCI bridge in the peripheral device side PCI Express-ASI bridge;
FIG. 9 is a block diagram of a first embodiment of the present invention;
FIG. 10A is a block diagram showing an internal configuration of an upstream PCI Express-Ethernet bridge;
FIG. 10B is a block diagram showing an internal configuration of a downstream PCI Express-Ethernet bridge;
FIG. 11 is a diagram showing a configuration of a TLP encapsulating table;
FIG. 12 is a flow chart showing a schematic operation of a first embodiment of the present invention;
FIG. 13A is a flow chart showing an operation performed when the upstream PCI Express-Ethernet bridge receives a TLP;
FIG. 13B is a flow chart showing an operation performed when the upstream PCI Express-Ethernet bridge receives an Ethernet frame;
FIG. 14A is a flow chart showing an operation performed when the downstream PCI Express-Ethernet bridge receives an Ethernet frame;
FIG. 14B is a flow chart showing an operation performed when the downstream PCI Express-Ethernet bridge receives a TLP;
FIG. 15A is a flow chart showing an operation performed when the upstream PCI Express-Ethernet bridge receives a control Ethernet frame from a system manager;
FIG. 15B is a flow chart showing an operation performed when the downstream PCI Express-Ethernet bridge receives a control Ethernet frame from the system manager;
FIG. 16 is a block diagram of another embodiment of the present invention; and
FIG. 17 is a block diagram of still another embodiment of the present invention.