BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a configuration example of a switch apparatus according to an exemplary embodiment of the present invention;
FIG. 2 is a block diagram illustrating a configuration example of a TDM signal input interface of FIG. 1;
FIG. 3 is a block diagram illustrating a configuration example of a packet signal input interface of FIG. 1;
FIG. 4 is a block diagram illustrating a configuration example of a front stage TDM switch of FIG. 1;
FIG. 5 is a block diagram illustrating a configuration example of a middle stage switch of FIG. 1;
FIG. 6 is a block diagram illustrating a configuration example of a back stage TDM switch of FIG. 1;
FIG. 7 is a block diagram illustrating a configuration example of a TDM signal output interface of FIG. 1;
FIG. 8 is a block diagram illustrating a configuration example of a packet signal output interface of FIG. 1;
FIG. 9 is a diagram illustrating a format example of cellized data according to an exemplary embodiment of the present invention;
FIG. 10 is a block diagram illustrating a configuration example of a switch apparatus according to another exemplary embodiment of the present invention;
FIG. 11 is a block diagram illustrating a configuration example of a middle stage switch of FIG. 10;
FIG. 12 is a block diagram illustrating a configuration example of a front stage TDM switch of FIG. 10;
FIG. 13 is a diagram illustrating SONET/SDH frame format example;
FIG. 14 is an image illustrating port selection setting of a TDM switch;
FIG. 15 is a block diagram illustrating an input buffer type switch configuration;
FIG. 16 is a block diagram illustrating such an input buffer type switch configuration that buffer of each input port is provided for each destination output port (VOQ);
FIG. 17 is a block diagram illustrating an output buffer type switch configuration;
FIG. 18 is a block diagram illustrating a common buffer type switch configuration;
FIG. 19 is a block diagram illustrating a load-balance type switch configuration;
FIG. 20 is a block diagram illustrating a configuration of a related TDM-packet hybrid apparatus;
FIG. 21 is a block diagram illustrating a configuration of another related TDM-packet hybrid apparatus; and
FIGS. 22A and 22B are images illustrating mapping technology (virtual concatenation) of packet data on SONET/SDH frame.
EXEMPLARY EMBODIMENT
Next, exemplary embodiments of the present invention will be described referring to the drawings.
First Exemplary Embodiment
FIG. 1 is a block diagram illustrating a configuration example of a switch apparatus according to an exemplary embodiment of the present invention. In FIG. 1, the switch apparatus according to the exemplary embodiment of the present invention is configured to include input interface units 1-1 to 1-N, a front stage TDM (Time Division Multiplex) switch 2, a middle stage switch 3, a back stage TDM switch 4, and output interface units 5-1 to 5-N.
The input interface units 1-1 to 1-N input-interface TDM signal or packet signal, and the internal configuration is such a compatible configuration that TDM signal input interface units 11-1 to 11-N input-interfacing with TDM signal represented by SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy) frame data, and packet signal input interface units 12-1 to 12-N are exchangeable with each other.
The front stage TDM switch 2 executes TDM switching of TDM signal, and TDM switching to cause packet signal to load-balance to the middle stage switch 3. This front stage TDM switch 2 is a switch of N×2N to connect to the output interface units 5-1 to 5-N when TDM signal input interface units 11-1 to 11-N are fully mounted with N ports, and to connect to the middle stage switch 3 when packet signal input interface unit 12-1 to 12-N are fully mounted with N ports.
The middle stage switch 3 buffers load-balanced packet signal for each destination. The back stage switch 4 switches the packet signal buffered by the middle stage switch 3 for each destination.
The output interface units 5-1 to 5-N output-interface switched TDM signal or packet signal, and the internal configuration is such a compatible configuration that TDM signal output interfaces 51-1 to 51-N and packet signal output interfaces 52-1 to 52-N are exchangeable with each other.
FIG. 2 is a block diagram illustrating a configuration example of the TDM signal input interface units 11-1 to 11-N of FIG. 1. In FIG. 2, the TDM signal input interface units 11-1 to 11-N (described as TDM signal input interface 11) are configured with SONET/SDH frame termination unit 111.
FIG. 3 is a block diagram illustrating a configuration example of the packet signal input interface units 12-1 to 12-N of FIG. 1. In FIG. 3, the packet signal input interface units 12-1 to 12-N (described as packet signal input interface 12) includes a cellizing unit 121 which divides inputted packet signal to fixed-length cells, and a cell destination providing unit 122 which provides destination of each divided cell for a cell header by detecting the destination from a header of a packet in the case of cellizing.
FIG. 4 is a block diagram illustrating a configuration example of the front stage TDM switch 2 of FIG. 1. In FIG. 4, the front stage TDM switch 2 includes N:1 selectors 21-1 to 21-2N which selects one set of input signal from N sets of input signal for each output port as a switching operation for TDM signal or packet signal inputted from input ports 1 to N, a TDM signal control memory 22 which designates a port to be selected from the N:1 selectors 21-1 to 21-2N at each time slot as a TDM switching operation for TDM signal input ports, and a packet signal control memory 23 which designates a port to be selected from the N:1 selectors 21-1 to 21-2N at each time slot as a TDM switching operation for load-balancing to the middle stage switch 3 for packet signal input ports.
Here, in FIG. 4, while the input port side has N sets of inputs to cause TDM signal and packet signal be configured to be compatible, when TDM signal is selected, it is selected by the N:1 selectors 21-1 to 21-2N connected to the output interfaces 5-1 to 5-N, and when packet signal is selected, it is selected by the N:1 selectors 21-1 to 21-2N connected to the middle stage switch 3. Thus, the N:1 selectors 21-1 to 21-2N need 2N sets as total of N sets of TDM signal output ports and N sets of packet signal output ports, and the front stage TDM switch 2 become to be a N×2N switch.
FIG. 5 is a block diagram illustrating a configuration example of the middle stage TDM switch 3 of FIG. 1. In FIG. 5, the middle stage switch 3 includes cell extracting units 31-1 to 31-N which identify a cell header part of input signal from the front stage TDM switch 2, destination decision units 32-1 to 32-N which detect destination information of each cell from the identified cell header and decides to store the information in which queue of a subsequent middle stage buffer (middle stage VOQ (Virtual Output Queue)), middle stage VOQs 33-1 to 33-N which buffer packet signal which is cellized and load-balanced by the front stage TDM switch 2 for each destination, and an output timing control unit 34 which controls timing for outputting cells from the middle stage VOQs 33-1 to 33-N to the back stage TDM switch 4.
Here, it is assumed that the number of mounted ports of packet signal input output interface is K (1≦K≦N), and only K sets of the cell extracting units, the destination decision units, and the middle stage VOQs are mounted to avoid the unnecessary increase of circuit size. In FIG. 5, this un-mounted part is illustrated with dotted line.
FIG. 6 is a block diagram illustrating a configuration example of the back stage TDM switch 4 of FIG. 1. In FIG. 6, the back stage TDM switch 4 includes N:1 selectors 41-1 to 41-N which select one set from N sets of input signal for each output port as a switching operation for packet signal which is cellized and inputted from the input ports 1 to N, and a packet signal control memory 42 which designates a port to be selected of the N:1 selectors 41-1 to 41-N at each slot time as a TDM switching operation.
FIG. 7 is a block diagram illustrating a configuration example of the TDM signal output interfaces 51-1 to 51-N of FIG. 1. In FIG. 7, the TDM signal output interfaces 51-1 to 51-N (described as TDM signal output interface 51) is configured with SONET/SDH frame generation unit 511.
FIG. 8 is a block diagram illustrating a configuration example of the packet signal output interfaces 52-1 to 52-N of FIG. 1. In FIG. 8, the packet signal output interfaces 52-1 to 52-N (described as packet signal output interface 52) includes a cell extracting unit 521 which identifies a cell header part for input signal from the back stage TDM switch 4, a source port number (input port number) decision unit 522 which detects input port information from the identified cell header which indicates what input port each cell has come from, and decides to store the information in what queue of the subsequent VIQ (Virtual Input Queue), VIQ 523, and a packet assembling unit 524 which returns the divided cells to packet for each source port (input port).
FIG. 9 is a diagram illustrating a format example of cellized data according to an exemplary embodiment of the present invention. In FIG. 9, the cellized data includes cell header part including destination port number (output port number), a source port number (input port number), and packet header/middle/tail information, and pay load.
Operations of a switch apparatus according to the exemplary embodiment of the present invention will be described referring to such FIG. 1 to FIG. 9.
As illustrated in FIG. 1, the switch apparatus according to the exemplary embodiment of the present invention uses the front stage TDM switch 2 as shared with the switching of TDM signal in a configuration of a load-balance type switch configured with the front stage TDM switch 2 and the middle stage switch 3 and the back stage TDM switch 4 for realizing the switching of packet signal. That is, a function of a TDM switch is realized at same time within one switch fabric for realizing packet switch.
As described above, because a switch fabric of a TDM switch and a packet switch do not exist separately, the TDM signal input interfaces 11-1 to 11-N and the packet signal input interfaces 12-1 to 12-N can be exchangeable with each other and configured to be compatible. And, as described in FIG. 1, the TDM signal output interfaces 51-1 to 51-N and the packet signal output interfaces 52-1 to 52-N also can be exchangeable with each other and configured to be compatible, by providing both of a connection path from the front stage TDM switch 2 and a connection path after passing through the middle stage switch 3 and the back stage TDM switch 4.
In such configurations, for example, if it is assumed that the whole switch capacity required for one apparatus is L, it become to be possible to flexibly distribute the capacity L to a part for processing TDM signal and a part for processing packet signal. That is, it is possible to flexibly allocate the number of input and output interface units to be mounted for TDM signal and the number of input and output interface units to be mounted for packet signal.
Next, each operation of the case that TDM signal is inputted and the case that packet signal is inputted will be described.
First, as an operation for processing TDM signal, as described in FIG. 2, the TDM signal input interfaces 11-1 to 11-N execute SONET/SDH frame termination, and transfers the extracted payload data to the front stage TDM switch 2. In an operation of the front stage TDM switch 2, a port to be selected from the N:1 selectors 21-1 to 21-2N is set at each time slot in the TDM signal control memory 22, and one set is selected from N sets of input signal for each output port in the N:1 selectors 21-1 to 21-2N according to the setting.
A setting image to the TDM signal control memory 22 is illustrated in FIG. 14. Here, the input port number selected at each time slot in each output port has been previously determined for inputted payload data, and the determination is previously set. In SONET/SDH frame, one time slot corresponds to one byte, and one channel data for the same destination is multiplexed by byte-interleave. That is, byte data of the same destination channel appears at a certain interval of time. In the front stage TDM 2, data multiplexed by byte is switched to the destination output port by selecting at the prescribed time slot with the above setting.
When TDM signal is inputted, the signal is directly connected to the TDM output interface unit 51-1 to 51-N in the output interfaces 5-1 to 5-N without passing through the middle stage switch 3 and the back stage TDM switch 4 illustrated in FIG. 1. As illustrated in FIG. 7, the TDM signal output interfaces 51-1 to 51-N generates SONET/SDH frame, puts data on the SONET/SDH frame, and outputs it as TDM signal.
Next, as illustrated in FIG. 3, an operation for processing packet signal cellizes inputted variable length packet signal to fixed length cells at the cellizing unit 121 to cause the subsequent processing to be easy, and in addition provides the destination information to each cell at the cell destination providing unit 122. An example of a cellized data format of this case is illustrated in FIG. 9.
This operation for cellizing identifies a destination of each packet signal, causes the destination information to be a destination for switching, and provides it as a destination port number (output port number) part in a cell header illustrated in FIG. 9. This destination port number is used for the identification in the middle stage switch 3 when the distribution for destination is executed in the back stage TDM switch 4 after load-balancing.
And, this operation for cellizing provides a source port number (input port number) indicating the port number of its own input interface as a source port number (input port number) part in a cell header illustrated in FIG. 9. This source port number is used to identify an input port in the case of separately queuing as VIQ (Virtual Input Queue) for each input port number which each switched cell has passed through when cells are finally assembled to packet at the packet signal output interfaces 52-1 to 52-N indicated later.
Further, information is provided in the cell header, which identifies the location of the divided cell in a packet such as head, middle, or tail, to assemble a packet in the packet signal output interfaces 52-1 to 52-N. Finally, actual packet signal is mounted on payload illustrated in FIG. 9 and is transferred to the front stage TDM switch 2.
An operation for processing packet signal cellized by the front stage TDM switch 2 is to equally distribute (load-balancing) cells to the middle stage VOQ (Virtual Output Queue) in the next middle stage switch 3. Because it is only to balance the load, an operation hereof is an operation of the TDM switch as illustrated in FIG. 14. That is, the operation is set so as to select the input port number at each time slot in such an order that the number is smaller, and repeat the selection to load-balance cells in each output port.
Here, differing from the case of the above TDM signal, in the case of processing packet signal, one time slot corresponds to one cell, and data transferred to the same destination continues during the number of bytes corresponding to one cell length. Thus, the packet signal control memory 23 sets a port to be selected for each cell in the N:1 selectors 21-(N+1) to 21-2N.
And, when packet signal is inputted, because the signal is connected to the middle stage switch 3, the N:1 selector 21-(N+1) to 21-2N illustrated in FIG. 4 are used as N:1 selector. However, in this case, while it is a setting for each cell, if it is such a configuration that data of the number of bytes corresponding to one cell length is continuously set to the same destination, the packet signal control memory 23 can be configured with same hardware as that of the above TDM signal control memory 22, and a hardware configuration for packet signal until the N:1 selectors 21-1 to 21-2N is not particularly different from that of TDM signal.
Further, if the cell load balancing to the middle stage VOQ is executed for each N cells after N cells of the same destination has been accumulated in the input interfaces 1-1 to 1-N, the cell order inversion is not induced because of the difference of cell accumulation state in the middle stage VOQ. According to the above setting, one set of signal are selected from N sets of input signal and transmitted to the middle stage switch 3 in the N:1 selectors 21-(N+1) to 21-2N.
As illustrated in FIG. 5, the middle stage switch 3 extracts cells to identify a cell header of inputted cell signal. This can be performed by causing the input interfaces 1-1 to 1-N, the front stage TDM switch 2, and the middle stage switch 3 to include common frame information indicating a beginning location of the cell. The cell header illustrated in FIG. 9 is identified by extracting cells, and a destination of each cell is identified with the destination port number information by the destination decision units 32-1 to 32-N.
After identifying the destination, the cells are divided for each destination and queued in the middle stage VOQ 23-1 to 23-N. This queuing for each destination is configured so that HOL blocking (Head Of Line blocking) described in Description of the Related Art is avoided, and each cell is caused to be easily read to the next back stage TDM switch 4 according to the instruction of the output timing control 34 when the switching to the destination is executed in the next back stage TDM switch 4.
Because it is previously set in the next back stage TDM switch 5 that each cell is switched to which output port if it is read from which one of the middle stage VOQ 33-1 to 33-N at which timing, according to the setting, the output timing control 34 controls the cell read timing for each identified destination.
Here, if the number of mounted ports of packet signal input output interface is K (1≦K≦N), only K sets of the cell extracting units, the destination decision units, and the middle stage VOQs are mounted respectively. This is why it is avoided that the circuit size is increased because more unnecessary cell extracting units, destination decision units, and middle stage VOQs are mounted if the number of mounted ports of packet signal input and output interface is K in such a configuration that the number of the input and output interfaces of TDM signal and packet signal is flexibly changed. In FIG. 5, the cell extracting units, destination decision units, and middle stage VOQs from K+1 to N are illustrated with dotted lines.
The back stage TDM switch 4 switches to an actual destination. Operation itself of switch unit is basically same as operation in the front stage TDM switch 2. That is, in the packet signal control memory 42, operation of the TDM switch as illustrated in FIG. 14 is set, and like the front stage TDM switch 2, one time slot corresponds to one cell, and data for the same destination continues during the number of bytes of one cell length, so that a port to be selected of the N:1 selectors 41-1 to 41-N is set for each cell. That is, the packet signal control memory 42 continuously sets the bytes corresponding to one cell length to the same destination.
According to this setting, the above output timing control unit 34 of the middle stage switch 3 reads cells from the middle stage VOQs 33-1 to 33-N in consideration of the destination timing, and then, the switching is completed. According to the above setting, one set is selected from N sets of input signal for each output port in the N:1 selectors 41-1 to 41-N, and is transmitted to the packet signal output interfaces 52-1 to 52-N.
As illustrated in FIG. 8, the packet signal output interfaces 52-1 to 52-N extract cells to identify a cell header of inputted cell signal. This can be performed by causing the input interfaces 1-1 to 1-N, the front stage TDM switch 2, the middle stage switch 3, the back stage TDM switch 4, and the output interfaces 5-1 to 5-N to include common frame information indicating a beginning location of the cell.
The packet signal output interfaces 52-1 to 52-N identifies a cell header illustrated in FIG. 9 by extracting cells, and identifies which port each cell has been transmitted from according to the source port number (input port number) information in the cell header in the source port number (input port number) decision unit 522. After identifying the source port, cells are divided for each source port and queued in VIQ 523. This queuing for each source port is performed to easily assemble cells in next packet assembling unit 524. For each cell read for each identified source port, the packet assembling unit 524 decides the location in a packet such as head, middle, or tail, and assemble packet according to the information, and returns it to the original signal to output.
As described above, in the packet signal processing, the load-balance type switch functions as a complete packet switch, which is configured with the input interfaces 1-1 to 1-N, the front stage TDM switch 2, the middle stage switch 3, the back stage TDM switch 4, and the output interfaces 5-1 to 5-N. That is, in such a configuration that packet data mapped on SONET/SDH frame with the related virtual concatenation is TDM-switched, the switching can be performed only at the mapped fixed band speed from an input port to an output port, on the other hand, in the load-balance type switch, it is possible to transmit cells at free band to any output port according to a destination of packet signal inputted from some port, so that switching paths of free band can be constructed.
As described above, in the first exemplary embodiment, because the TDM switch connection and the packet switch connection share a connection path between an input and output interface unit and an switch unit by causing the front stage TDM switch 2 to be a TDM packet hybrid switch used as shared with the switching of TDM signal in a configuration of the load-balance type switch for realizing switching of packet signal, it is possible to secure the flexibility of the mounting capacity distribution between TDM signal and packet signal in the whole switch capacity required for one apparatus.
And, in the first exemplary embodiment, because the front stage TDM switch 2 is used as shared with the switching of TDM signal in a configuration of the load-balance type switch for realizing the switching of packet signal, it is possible to realize the packet signal switching without limiting a path between input and output interface port to a fixed band speed in a TDM-packet hybrid switch.
Second Exemplary Embodiment
FIG. 10 is a block diagram illustrating a configuration example of a switch apparatus according to another exemplary embodiment of the present invention. In FIG. 10, another exemplary embodiment of the present invention has a same configuration as the switch apparatus according to the exemplary embodiment of the present invention illustrated in FIG. 1, except that the TDM signal input and output interface and the packet signal input and output interface are implemented on same interface cards 6-1 to 6-N, and the middle stage switches 63-1 to 63-N (the middle stage switches 63-1 to 63-2 are not illustrated) are provided as distributed for each card of the packet signal input and output interface units.
FIG. 11 is a block diagram illustrating a configuration example of a middle stage switch 63-1 to 63-N of FIG. 10. In FIG. 11, the middle stage switch 63-1 to 63-N (described as middle stage switch 63) includes a cell extracting unit 631 per one input and output port, a destination decision unit 632, a middle stage VOQ 633, and an output timing control unit 634, and the mounting number of the cell extracting unit, the destination decision unit, and the middle stage VOQ corresponds directly to the number of the packet signal input and output interface port. In the case of this configuration, as illustrated in FIG. 10, the input and output interface cards 6-1 to 6-N include both of a transmitting and receiving path with the front stage TDM switch 7 and a transmitting and receiving path with the back stage TDM switch 8.
When the TDM signal input and output interface is mounted, while it is actually enough to include only the transmitting and receiving path with the front stage TDM switch 7, the input and output interface cards 6-1 to 6-N of packet signal and TDM signal, in order to secure the flexibility of the mounting capacity distribution, include also connection paths (in FIG. 10, illustrated with dotted line) between all input and output interface cards 6-1 to 6-N and the back stage TDM switch 8 including the case that the TDM signal input and output interface is mounted.
The feature of this configuration is that a connection path from the front stage TDM switch 7 to the input and output interface cards 6-1 to 6-N is shared in the case of processing TDM signal and in the case of processing packet signal, and can be connected to the TDM signal output interfaces 62-1 and 62-2 in the case of processing TDM signal, and can be connected to the middle stage switches 62-3 to 62-N in the case of processing packet signal in a card.
Thereby, because it becomes to be unnecessary to physically connect to different port such as the output interfaces 5-1 to 5-N in the case of processing TDM signal, and the middle stage switch 3 in the case of processing packet signal as an exemplary embodiment of the present invention illustrated in FIG. 1, the front stage TDM switch 7 needs not N×2N configuration (mounting 2N sets of N:1 selector) as illustrated in FIG. 4, but N×N configuration (N sets of N:1 selector 71-1 to 71-N) as illustrated in FIG. 12, so that a new effect is provided that the circuit size of the front stage TDM switch 7 can be drastically reduced.
While the invention has been particularly shown and described with reference to exemplary embodiments thereof, the invention is not limited to these embodiments. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the claims.
Patent Application
20080056259
