Embodiments of the present disclosure relate to switch circuits, and particularly to a switch circuit used in a computing device.
A computing device can include a plurality of input/output (I/O) devices, such as a mouse, a keyboard, and a display, connected to universal serial bus (USB) interfaces of the computing device. When the computing device is not being used, the display of the computing device is usually turned off to reduce power consumption. However, the I/O devices, such as the mouse and the keyboard of the computing device, are still powered on to work normally when the display is turned off, which causes unnecessary waste of power. Therefore, there is room for improvement in the art.
The figure illustrates a schematic circuit diagram of one embodiment of a computing device including a switch circuit.
The disclosure, including the accompanying drawings, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
Referring to the figure, a computing device 1 includes a switch circuit 100, a universal serial bus (USB) power source 200, and a display 300. The USB power source 200 includes a voltage output port (Vout) to output a voltage (e.g., 5V) to power input/output (I/O) devices (e.g., mouse and keyboard) connected to USB interfaces (not shown) of the computing device 100. The switch circuit 100 is electrically connected between the display 300 and the Vout of the USB power source 200. The switch circuit 10 controls the USB power source 200 to stop outputting the voltage when the display 300 is turned off. Thus, the I/O devices connected to the USB interfaces of the computing device 1 and powered by the USB power source 200 are turned off accordingly, thereby reducing unnecessary power waste of the I/O devices. The switch circuit 10 further controls the USB power source 200 to output the voltage when the display 300 is turned on. Thus, the I/O devices connected to the USB interfaces of the computing device 1 are turned on accordingly.
In this embodiment, the switch circuit 100 includes a power button 11, a signal generation unit 12, a platform control hub (PCH) 13, and a switch unit 14. The power button 11 is electrically connected to the signal generation unit 12. The signal generation unit 12 is electrically connected to a general purpose input output (GPIO) pin of the HUB 13 and an end of the switch unit 14. The other end of the switch unit 14 is electrically connected to the Vout of the USB power source 200. The PCH 13 is electrically connected to the display 300.
When the power button 11 is pressed, the power button 11 transmits a voltage signal to the signal generation unit 12. In this embodiment, one pin of the power button 11 is grounded. Therefore, the voltage signal is a low-level voltage signal (e.g., 0V) and is transmitted to the signal generation unit 12 when the power button 11 is pressed. In other embodiments, the power button 11 can be electrically connected to a power source (e.g., 3.3V) and the voltage signal can be a high-level voltage signal (e.g., 3.3V) accordingly.
When the signal generation unit 12 receives the voltage signal from the power button 11, the signal generation unit 12 generates and outputs a control signal to the PCH 13 and the switch unit 14. In this embodiment, the control signal includes a first control signal and a second control signal. For example, the first control signal can be a low-level signal such as logic “0,” and the second control signal can be a high-level signal such as logic “1.” The signal generation unit 12 generates the first control signal when the power button 11 is pressed an odd number of times, and generates the second control signal when the power button 11 is pressed an even number of times.
The PCH 13 turns off or turns on the display 300 according to the control signal received from the signal generation unit 12, and the switch unit 14 controls the USB power source 200 to output the voltage or not output the voltage according to the control signal. For example, when the control signal is the first control signal (e.g., the low-level signal), the PCH 13 turns off the display 300 and the switch unit 14 controls the USB power source 200 to stop outputting the voltage, thereby turning off the I/O devices powered by the USB power source 200. When the control signal is the second control signal (e.g., the high-level signal), the PCH 13 turns on the display 300 and the switch unit 14 controls the USB power source 200 to output the voltage to power the I/O devices.
In this embodiment, the PCH 13 is a south bridging chip of the computing device 1. The PCH 13 can be integrated on a motherboard (not shown) of the computing device 1. The PCH 13 controls the display 300 to output signals or not output signals by controlling a video card of the computing device 1.
The signal generation unit 12 includes a buffer 121 and a D trigger 122. The buffer 121 includes an input pin A, a ground pin GND, an output pin Y, and a first power pin VCC. The input pin A is electrically connected to the power button 11 to receive the voltage signal when the power button 11 is pressed. The input pin A is further electrically connected to a power source P3V3 (e.g., 3.3V) via a first resistor R1, to make the input pin be in a high-level state when the power button 11 is not pressed. When the power button 11 is pressed, the input pin A is pulled down to a low-level state. The output pin Y outputs the voltage signal (low-level voltage signal) received from the input pin A to the D trigger 122 after delaying a predetermined time duration (e.g., 100 ms). The first power pin VCC is electrically connected to the power source P3V3 to power the buffer 121. The ground pin GND is grounded.
The D trigger 122 includes a clock pin CLK, a second power pin VDD, a ground pin GND, a triggering pin D, an inverted output pin
The switch unit 14 includes a first transistor Q1 and a second transistor Q2. Each of the first transistor Q1 and the second transistor Q2 includes a base, an emitter, and a collector. The base of the first transistor Q1 is electrically connected to the noninverting output pin Q of the D trigger 122 via a third resistor R3, the collector of the first transistor Q1 is electrically connected to the power source P3V3, and the emitter of the first transistor Q1 is grounded. The base of the second transistor Q2 is electrically connected to the collector of the first transistor Q1, the collector of the second transistor Q2 is electrically connected to the Vout of the USB power source 200, and the emitter of the second transistor Q2 is grounded.
When the control signal output from the D trigger 122 is the first control signal (e.g., the low-level signal), the base of the first transistor Q1 is pulled down to turn off the first transistor Q1, so that the base of the second transistor Q2 receives a voltage from the power source to turn on the second transistor Q2. When the second transistor Q2 is turned on, the USB power source 200 is grounded via the second transistor Q2, so that the USB power source 200 stops outputting the voltage via the Vout.
When the control signal output from the D trigger 122 is the second control signal (e.g., the high-level signal), the base of first transistor Q1 is pulled up to turn on the first transistor Q1, so that the base of the second transistor Q2 is grounded via the first transistor Q1 to turn off the second transistor Q2. When the second transistor Q2 is turned off, the USB power source 200 is not grounded via the second transistor Q2. Thus, the USB power source 200 can output the voltage via the Vout to power the I/O devices.
In this embodiment, capacitors C1, C2, C3, and C4, which are electrically connected between the power source and ground, are voltage stabilizing capacitors.
As described above, the switch circuit 100 can synchronously turns off the display 300 and other I/O devices of the computing device. Thus, power is prevented from being wasted by the I/O devices when the display 300 is turned off.
Although certain embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
Number | Date | Country | Kind |
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2013104341833 | Sep 2013 | CN | national |