1. Field of the Disclosure
This application relates to an airflow control into an internal combustion engine. More particularly, the application relates to performing an optimal control of an internal combustion engine using an explicit model predictive controller in combination with a switch gain scheduler.
2. Description of the Related Art
Air flow control of an internal combustion engine is an important strategy to increase engine performance and fuel economy. This is particularly true with diesel engines. Traditionally, an air flow control strategy is developed using a proportional (P), integral (I), and differential (D) control design. PID control design is focused on nominal engine operating conditions and consequently does not perform effectively under off-nominal conditions. PID is a well-known simple control approach utilized for single input single output (SISO) systems. PID approaches have been extended to multiple-input multiple output (MIMO) systems; however more advanced control techniques are able to deliver better performance, e.g. Model Predictive Controller (MPC). MPCs are popular in the process industry such as in chemical processing technologies and are currently being adopted with limited use in the automotive industry. Internal combustion engines operate under different conditions (e.g., high speed or load vs low speed or load) during their use. Each engine operating condition has an air flow dynamic that necessitates design of multiple controllers. Design and use of multiple controllers trigger problems related to the limited memory of an engine control unit (ECU) and the cost of controller calibration.
In order to reduce the memory usage and processing time, a Switch Gain Scheduled controller is designed and implemented in conjunction with an explicit MPC.
According to an embodiment, a switch gain scheduler used in conjunction with an explicit MPC makes an off-nominal operating condition resemble a nominal operating condition. The switch gain scheduler changes a controller gain depending on operating conditions.
The forgoing general description of the illustrative implementations and the following detailed description thereof are merely exemplary aspects of the teachings of this disclosure, and are not restrictive.
A more complete appreciation of this disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words “a”, “an” and the like generally carry a meaning of “one or more”, unless stated otherwise. The drawings are generally drawn to scale unless specified otherwise or illustrating schematic structures or flowcharts.
Furthermore, the terms “approximately,” “proximate,” and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10% or preferably 5%, and any values there between.
The advantage of this embodiment is only one explicit model predictive controller (MPC) may be designed. Hence, the ECU memory usage is significantly reduced in addition to the calibration requirement reduction, while maintaining the performance of the engine such as the diesel engine.
Referring to
In process step 204, constraint parameters for the scaled plant with Hid are computed in real-time online, where i is the operating condition. Next, in process step 205, the diagonal matrix Hid is used to determine the optimal control strategy. The optimal control strategy is obtained using the using explicit MPC solver and scaled constraints parameters. In process step 206, the diagonal matrix Hid is multiplied to the optimal control action taken by the explicit MPC to calculate a new controlled plant input u. Then the switch gain scheduled explicit MPC waits for the next half step sample time 207.
In the process step 208, constraint parameters for the scaled plant with Hio are computed in real-time, where i is the operating condition. In the process step 209, the diagonal matrix Hio is used to determine the optimal control strategy. The optimal control strategy is obtained using the explicit MPC solver and scaled constraints parameters. In the process step 210, the off-diagonal matrix Hio is multiplied to the optimal control action taken by the explicit MPC to calculate a new controlled plant input u. Then the switch gain scheduled explicit MPC waits for the next half step sample time 211. The processes 204-211 are repeated as the time advances.
The switch gain scheduled explicit MPC is general enough to be applied to any internal combustion engine control system application. In this embodiment, diesel engine air flow control is used as a sample application.
Referring to
Each of the nominal and off-nominal plants may be controlled by different explicit MPCs 301 and 304, respectively. In case of off-nominal conditions, if there are i different operating condition, then i different MPCs may be implemented, which in turn increases the memory storage and processing requirement of the ECU 601 used for the engine 604 in
In the present embodiment, the plurality of MPC issue is resolved by designing a single explicit MPC at nominal operating condition and inserting the switching gain scheduler block 102. The switch gain scheduler 102 is coupled with the off-nominal plant model 103 as illustrated in
The design and implementation of a gain scheduler itself is dependent on the type of controller and system dynamics, which include different operating conditions, that render the gain scheduler a specialized module. The present embodiment designs and implements the gain scheduler for an explicit MPC type of controller. In addition, the switch gain scheduler is designed based on splitting the gain matrix Hi into Hid and Hio, where i refers to the operating condition, d denotes the diagonal matrix and o denotes the off-diagonal matrix. The switch gain scheduler defines a switching variable which dynamically switches between the Hid and the Hio gain matrices.
The basis of splitting the gain matrix Hi is illustrated in
Applying the gain scheduling (GS) matrix Hi in the traditional way transforms the control issued by the explicit MPC. An exemplary transformation 402 shows that the original control constraints 401 are violated (shaded regions).
The mathematical form of the exemplary
V u≦W (1)
Where,
On applying the gain scheduling after the explicit MPC, equation (1) is transformed to equation (2). The resulting matrix does not fully satisfy the constraints W.
V H
i
u*≦W (2)
Where,
When working with explicit MPC, the control constraints restrict one to use special cases of Hi such that the transformation u=Hi u* (refer
Referring to
Referring to
Referring again to
V u≦W′ (3)
Where,
V and u are same as in equation (1)
On applying the gain scheduling after the explicit MPC, equation (3) is transformed to equation (4). The resulting matrix now fully satisfies the constraints W 401.
V H
i
d
u*≦W (4)
Where,
V and u* are same as in equation (1)
Referring to
V u≦W″ (5)
Where,
V and u are same as in equation (1)
On applying the gain scheduling after the explicit MPC, equation (5) is transformed to equation (6). The resulting matrix now fully satisfies the constraints W 401.
V H
i
o
u*≦W (6)
Where,
A mathematical proof illustrating why a gain scheduling method that switches between a gain matrix Hid and Hio works as well as a full gain scheduling, in which there is no switching between gain matrix, is discussed hereafter. Recall, a switched gain scheduled matrix also satisfies the real control constraints as opposed to a full gain scheduler (see
A discretized dynamic system employing a full gain scheduling can be represented mathematically as equations 7 and 8.
x
k+1
=A x
k
+B H u
k (7)
x
k+2
=A
2
x
k
+A B H u
k (8)
Where, A and B are system dynamics matrices, H is a full gain scheduling matrix, xk is the system input at time-step k, and uk is the controlled plant input at time-step k.
A dynamic system employing a switched gain scheduling can be represented mathematically as equations 9 and 10.
k+1
=A
k
+B H
d
u
k (9)
k+2
=A
2
k
+A B H
d
u
k
+B H
o
u
k (10)
An error system may be defined as ek=xk−
e
k+2
=A
2
e
k+(A B H−A B Hd−B Ho) uk (11)
As long as the eigenvalues of A are inside the unit circle, and the control uk is bounded, the error can also be bounded. Now consider a first order Taylor series expansion of an exponential matrix as given by equation 12.
e
A
ΔT
=I+A
c
ΔT+higher order terms (12)
Applying (12) to the discretized equation 11 and assuming H=Hd+Ho we get,
e
k+2
=A
2
e
k
+ΔT
2
A B H
o
u
k+higher order terms of ΔT (13)
Note in equation 13, for small sampling period ΔT, the term ΔT2 A B Ho uk dominates over the higher order terms of ΔT. As ΔT tends to zero, a switch gain scheduled system approaches the dynamic system under consideration.
The results of sample implementation of the switch gain scheduled explicit MPC for a diesel engine air flow control are shown in
An exemplary engine control unit (ECU) such as ECU 601 contains at least one micro-processor or the equivalent, such as a central processing unit (CPU) or application specific processor ASP (not shown), input and output interfaces 607, memory circuit 606 (e.g., ROM, EPROM, EEPROM, flash memory, static memory, DRAM, SDRAM, and their equivalent), power circuitry, and other supporting components. The microprocessor is circuitry that utilizes a computer readable storage medium, such as the memory circuit 606, configured to control the microprocessor to perform and/or control the processes discussed in this embodiment.
The microprocessor or aspects thereof, in alternate implementations, can include or exclusively include a logic device for augmenting or fully implementing this disclosure. Such a logic device includes, but is not limited to, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a generic-array of logic (GAL), and their equivalent. The microprocessor can be a separate device or a single processing mechanism. Further, this disclosure can benefit from parallel processing capabilities of a multi-cored CPU. Control circuitry provided by one or more processors in multi-processing arrangement may also be employed to execute sequences of instructions contained in memory. Alternatively, hard-wired circuitry may be used in place of or in combination with software instructions. The exemplary implementations discussed herein are not limited to any specific combination of hardware circuitry and software.