Switch matrix

Abstract

A switch matrix module (600) includes programmable stub breakers (508-512, 514-518) which can break off the bus and isolate unused portion of the switch matrix. Using three-way stub breakers (508-512, 514-518) at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, allows for the formation of very large matrices which have improved operational performance.

Description

FIELD OF THE INVENTION

This invention relates to field of electronics and more specifically to a switch matrix module for switching electrical signals.

BACKGROUND

Designing a switch matrix module that can handle large current loads and that can also have a high frequency bandwidth in a small footprint is no easy task to accomplish. As the dimensional size of a switch matrix increases, signal path lengths typically increase, causing a degradation of the signals being transmitted through the switch matrix.

N×M switch matrices generally are classified into one of three types: cross-point, blocking, or non-blocking. An example 2×2 switch matrix constructed as a non-blocking switch matrix is shown in the FIG. 1, a 2×2 blocking matrix is shown in FIG. 2, and a 2×2 crosspoint matrix is shown in FIG. 3.

In order to better understand these different switch matrix types, a discussion of some of the advantages and disadvantages of each type of switch matrix follows.

Non-Blocking Switch Matrices

A prior art non-blocking switch matrix as shown in FIG. 1 provides the highest frequency capabilities of any of the other types of switch matrices, well into the Giga-Hertz (GHz) range with appropriate switch selection. An N×M non-blocking switch matrix allows up to the smaller of N or M simultaneous and independent paths while minimizing or eliminating stubs that generate high Voltage Standing Wave Ratios (VSWRs).

One disadvantage found with non-blocking switch matrices is that they are the least space efficient of all three matrix types since the size of the matrix determines the number of switches and poles required. Hence an 8×8 switch would require 16 separate 1×8 switches to implement. Non-blocking switch matrices make it difficult to route electrical interconnections on printed circuit boards. Such interconnections are typically implemented in practice using discrete coaxial cable connections which create a bulky, space-inefficient situation. Non-blocking switch matrices are also difficult to use as a building block for a larger sized switch matrix since even more difficult interconnects would be required.

Blocking Switch Matrices

Blocking switching matrices as shown in FIG. 2 have the highest operating frequency potential, well into the GHz range with appropriate switch selection. These switch matrices also use up a very small footprint and require only one switch with N poles and another with M poles. Another advantage of the blocking switch matrices is that they require single cable interconnects which minimizes the tangling of cables.

Some of the disadvantage inherent with blocking switch matrices is that they are difficult to use as building blocks to build larger-sized switch matrices a major disadvantage in some applications. Also, blocking switch matrices only allow for a single electrical signal path to exist at any given point in time.

Cross-Point Matrices:

Cross-point matrices such as that shown in FIG. 3 have the highest density potential of all matrix types and as such are conducive to printed circuit board layout designs. An N×M cross-point matrix allows up to the smaller of N or M simultaneous and independent paths. A cross-point matrix also makes it easy to replace relays when a printed circuit board layout design is used for interconnects. Other advantages of cross-point matrices are that they have relatively few internal interconnects: N+M, provide for single cable interconnects and are easy to use as building blocks to create larger matrix sizes on the same circuit board.

A disadvantage of cross-point matrices is that stubbing is difficult to control on larger matrix sizes and can seriously deteriorate higher frequency performance if not controlled. Cross-point matrices also have frequency performance characteristics significantly less than the other matrix types, in the MHz range versus GHz for the other types since high-frequency (“can”) switches do not have a physical geometry conductive to this matrix layout. Cross-point switch matrices also make it difficult to build larger matrix sizes where the matrices span different circuit cards (modules) without creating additional stubbing problems.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:

FIG. 1 shows a prior art 2×2 non-blocking matrix.

FIG. 2 shows a prior art 2×2 blocking matrix.

FIG. 3 shows a prior art 2×2 crosspoint matrix.

FIG. 4 shows a 4×2 crosspoint matrix with software controlled stub breakers in accordance with one aspect of the invention.

FIG. 5 shows a switch matrix module in accordance with one aspect of the invention.

FIG. 6 shows a physical block diagram of a switch matrix module in accordance with an embodiment of the invention.

FIG. 7 shows a logical block diagram of the switch matrix module shown in FIG. 6.

FIG. 8 a signal flow block diagram of the switch matrix module shown in FIG. 6.

FIG. 9 shows a logical relay layout schematic of the switch matrix module shown in FIG. 6.

FIG. 10 shows a set of front panel connectors of the switch matrix module shown in FIG. 6.

FIG. 11 shows a block diagram of the switch matrix module shown in FIG. 6.

FIG. 12 shows a block diagram of a switch matrix system in accordance with an embodiment of the invention.

FIG. 13 shows a static structure of a path selection in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures.

In accordance with one embodiment of the invention a high density switch matrix module comprising three 8×24 single-wire matrices, which are interconnected via a 10-lane, single wire bus and placed in a single-slot VXI card with each path having 2 ampere (A) switching capability and a minimum 60 MHz bandwidth is disclosed. Onboard configurable relays allow for software control of the matrix configuration. The switch module of the invention uses a cross-point matrix design with software-coordinated stub breakers which are switches which can break-off and isolate unused portions of the switch matrix in order to achieve its improved performance characteristics.

In one embodiment of the invention, the switch matrix module can be used to connect a large number of test instruments to a large number of test points as one example of its use. Designed for single-wire 50 ohm operation and providing exceptional signal isolation, the switch matrix module can be used for example for audio, video, telecom, data-com and automatic test equipment (ATE) systems testing. Although a single-wire design is discussed, the present invention can also support differential measurement designs. In another design, multiple switching modules are chained together via their expansion bus. It should be noted that the invention is not limited to the embodiments described herein and that other switch matrix designs can take advantage of the features of the invention.

In one embodiment, the switch matrix module achieves some of the specifications shown in Table 1 below, although other specifications may be achieved depending on the particular design requirements at hand.

TABLE 1
Maximum Switching Voltage: 220 VDC or 250 VAC
Maximum Switching Current: 2 ADC or 2 AAC
DC Performance:
Path Resistance:           >1.1 Ohm (8 × 24 configuration)
                           500 m Ohm (1 × 4 configuration)
Thermal EMF:               <10 uV
Impedance:                 50 ohm
AC Performance:
Bandwidth:                 >40 MHz (8 × 24 configuration)
                           >40 MHz (1 × 4 configuration)
Insertion Loss:
8 × 24 Configuration:
10 MHz:                    <1.0 dB
40 MHZ:                    <3.0 dB
1 × 4 Configuration:
10 MHz:                    <1.0 dB
40 MHZ:                    <2.5 dB
Isolation:
8 × 24 Configuration:
100 KHz:                   >80 dB
1 MHZ:                     >60 dB
10 MHz:                    >40 dB
1 × 4 Configuration:
100 KHz:                   >80 dB
1 MHZ:                     >60 dB
10 MHz:                    >40 dB
Crosstalk:
8 × 24 Configuration:
100 KHz:                   <−70 dB
1 MHZ:                     <−55 dB
10 MHz:                    <−38 dB
Crosstalk:
1 × 4 Configuration:
100 KHz:                   <−70 dB
1 MHZ:                     <−60 dB
10 MHz:                    <−40 dB
Terminations:
There is a one load set for each 8 × 24 matrix including one pull-up
(to +5 V)/one pull-down (to ground). The load set is individually
programmable to the following values and accuracies:
50 ohms:                   +15/−5 Ohms, ¾ W
75 ohms:                   +17.5/−7.5 Ohms, ¾ W
100 ohms:                  +20/−10 Ohms, ¾ W
1000 ohms:                 +110/0100 Ohms, ¾ W

Referring to FIG. 4, there is shown an example of two separate 2×2 cross-point matrices 408 and 410 with a stub breaker 406 having switches 404 and 402 which are software controlled to isolate and connect the required portions of the matrix to create a 4×2 matrix with improved performance in accordance with the invention. Based on any given path, the software controlling the switch matrix can determine the closest stub breakers (e.g., stub breaker 406) to open using signal graph theory for optimal frequency performance. The software is executed by a switch matrix controller (not shown) which can be implemented using one of a number of computers or computer cards (e.g., VXI computer card) depending on the particular design requirements. One of the biggest drawbacks of using cross-point matrices, stub formation, is reduced automatically by using these software controlled stub breakers as used in the invention. By mapping of any switch topology into Mutually Exclusive Sets has allowed the switch matrix module to retain good switch driver performance.

The controller for the switch matrix card complies a path search data structure which takes O(log 2n) using a Red-Black tree embedded within a Red-black tree. The advantages of this approach over using a hash table is that the Red-Black tree is always balanced so searching for any path takes roughly the same amount of time. This data structure is also unique in that it can store multiple alternative paths so that if one path is restricted, the driver can quickly search for other alternative paths which do not suffer from the same restrictions which has enabled the implementation of a highly interconnected topology such as the switch matrix module of the present invention. A best path searching algorithm is also provided that can determine the best possible path by traversing through each edge of the graph representing the switch matrix module and recursively walking the graph until a best possible path or until no path is found to satisfy the required switching conditions.

Another technique used in the invention to provide improved performance is to minimize the frequency limiting stubs caused when cross-point matrices span over multiple circuit cards. In order to overcome this stub formation in large switch matrices, in the invention each matrix implements a “3-way” stub-breakers at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices. FIG. 5 illustrates this using a 2×6 matrix comprising cards 502, 504 and 506 each having a 2×2 cross-point matrix 546, 548 and 550 as an example. Like the intra-matrix stub-breakers previously described above, the software operating the switch matrix implements signal flow optimization to determine which of the three switches, if any should be connected and to which expansion bus to effect the connections that span the multiple cards 502, 504 and 506.

Card #1 (502) includes a first three-way switch including switches 508, 510 and 512 and a second three-way switch including switches 514, 516 and 518. Each of the other two cards, Card #2 (504) and Card #3 (506) include two three-way switches. Card #2 (504) includes a first three-way switch including switches 524, 526 and 528 and a second three-way switch that includes switches 530, 532 and 534. Card #3 (506) includes a first three-way switch that includes switches 540, 542 and 544 and a second three-way switch that includes switches 552, 554 and 556. These three-way switches control the connections that can span multiple cards (expansion points) while maximizing frequency performance since any unneeded paths are isolated via the software controlled switches.

The switch matrix of the invention utilizes a physical layout geometry that is optimized for frequency performance and yet also allows programmable load terminations to exist in the design without creating additional stub penalties. In FIG. 8, block diagram 800 of a switch matrix module illustrates the signal flow in block form through the matrix. In card 802, the programmable load selection is performed in block 808, with the three 4×4 matrices 812, 816 and 820 can be isolated from each other as needed by stub breakers 810, 814 and 818. In block 822 expansion block selection is performed. An upstream 824 and a downstream 828 expansion bus which is 10 channels wide are also shown in switch matrix module 800. The other two cards that make up the switch matrix module 800 are also shown.

Referring now to FIG. 6, there is shown a physical block diagram of a switch matrix module 600 in accordance with one embodiment of the invention. The switch matrix module 600 includes a VXI bus interface 604, a controller board 606, a relay board 608 coupled to the controller board 606 via a plurality of 200-pin connectors 610 interconnecting the two boards. The relay board 608 is coupled to an interface board 602 via two 80 pin flex cables or connectors. The main controller board 606 is used in interfacing to the VXI bus and thus has all the control logic for communicating with the bus. In addition the control board 606 decodes the address's that select the relay enable read/write ports.

In one embodiment, the relay board 608 contains 900 relays of which 450 relays are on top (first side) with another 450 relays on the bottom (opposite side) of the printed circuit board. As mentioned, the controller board 606 connects to the relay board 608 via 200 pin flex cables 610. The flex cables pass the relay coil enabling signals from the control board 606 to the relay board 608. The interface board 602 contains eight connectors used to connect to the outside world. The interface board 602 connects to the relay board 608 using two 80 pin flex cables 612 as previously mentioned.

A logical block diagram of the switch matrix module 600 is shown in FIG. 7. The Interface board includes six 34-pin front-panel connectors, labeled J200-J205 and two 20-pin connectors, labeled J206 and J207. Each matrix includes a pair of 34-pin connectors. The two 20-pin connectors are used for bussing the 10 lane bus in and out of the matrix module. Table 2 shows the signal assignments to connector pins for each of the connectors:

TABLE 2
Front Panel Pinouts
J200
1	GND	2	O23C+
3	GND	4	O21C+
5	GND	6	O19C+
7	GND	8	O17C+
9	GND	10	O15C+
11	GND	12	O13C+
13	GND	14	O11C+
15	GND	16	O9C+
17	GND	18	O7C+
19	GND	20	O5C+
21	GND	22	O3C+
23	GND	24	O1C+
25	GND	26	I7C+
27	GND	28	I5C+
29	GND	30	I3C+
31	GND	32	I1C+
33	NC	34	NC
J201
1	GND	2	O24C+
3	GND	4	O22C+
5	GND	6	O20C+
7	GND	8	O18C+
9	GND	10	O16C+
11	GND	12	O14C+
13	GND	14	O12C+
15	GND	16	O10C+
17	GND	18	O8C+
19	GND	20	O6C+
21	GND	22	O4C+
23	GND	24	O2C+
25	GND	26	I8C+
27	GND	28	I6C+
29	GND	30	I4C+
31	GND	32	I2C+
33	NC	34	NC
J202
1	GND	2	O23B+
3	GND	4	O21B+
5	GND	6	O19B+
7	GND	8	O17B+
9	GND	10	O15B+
11	GND	12	O13B+
13	GND	14	O11B+
15	GND	16	O9B+
17	GND	18	O7B+
19	GND	20	O5B+
21	GND	22	O3B+
23	GND	24	O1B+
25	GND	26	I7B+
27	GND	28	I5B+
29	GND	30	I3B+
31	GND	32	I1B+
33	NC	34	NC
J203
1	GND	2	O24B+
3	GND	4	O22B+
5	GND	6	O20B+
7	GND	8	O18B+
9	GND	10	O16B+
11	GND	12	O14B+
13	GND	14	O12B+
15	GND	16	O10B+
17	GND	18	O8B+
19	GND	20	O6B+
21	GND	22	O4B+
23	GND	24	O2B+
25	GND	26	I8B+
27	GND	28	I6B+
29	GND	30	I4B+
31	GND	32	I2B+
33	NC	34	NC
J204
1	GND	2	O23A+
3	GND	4	O21A+
5	GND	6	O19A+
7	GND	8	O17A+
9	GND	10	O15A+
11	GND	12	O13A+
13	GND	14	O11A+
15	GND	16	O9A+
17	GND	18	O7A+
19	GND	20	O5A+
21	GND	22	O3A+
23	GND	24	O1A+
25	GND	26	I7A+
27	GND	28	I5A+
29	GND	30	I3A+
31	GND	32	I1A+
33	NC	34	NC
J205
1	GND	2	O24A+
3	GND	4	O22A+
5	GND	6	O20A+
7	GND	8	O18A+
9	GND	10	O16A+
11	GND	12	O14A+
13	GND	14	O12A+
15	GND	16	O10A+
17	GND	18	O8A+
19	GND	20	O6A+
21	GND	22	O4A+
23	GND	24	O2A+
25	GND	26	I8A+
27	GND	28	I6A+
29	GND	30	I4A+
31	GND	32	I2A+
33	NC	34	NC
J206
1	GND	2	BUS_IN 9+
3	GND	4	BUS_IN 8+
5	GND	6	BUS_IN 7+
7	GND	8	BUS_IN 6+
9	GND	10	BUS_IN 5+
11	GND	12	BUS_IN 4+
13	GND	14	BUS_IN 3+
15	GND	16	BUS_IN 2+
17	GND	18	BUS_IN 1+
19	GND	20	BUS_IN 0+
J207
1	GND	2	BUS_OUT 9+
3	GND	4	BUS_OUT 8+
5	GND	6	BUS_OUT 7+
7	GND	8	BUS_OUT 6+
9	GND	10	BUS_OUT 5+
11	GND	12	BUS_OUT 4+
13	GND	14	BUS_OUT 3+
15	GND	16	BUS_OUT 2+
17	GND	18	BUS_OUT 1+
19	GND	20	BUS_OUT 0+

In one embodiment, the matrix module is operated in a register-based mode, the user writes directly to the control registers on the matrix module. The matrix command module does not monitor these operations, and does not keep track of the relay states on the matrix module in this mode. The register-based mode provides faster control of relay channels. In this mode, relay operations are processed in less than nine microseconds, not counting relay settling time or software overhead inherent in I/O libraries such as VISA.

In the register mode, the matrix module is operated by directly writing to control registers and reading from status registers on the matrix module. There are 180 control/status register pairs on the matrix module. When a control register is written to, all channels controlled by that register are operated simultaneously. Default value for all control registers is hex “00” after reset. The matrix module has a 10 lane bus that is routed through the three matrices. With the exception of the matrix output relay groups, each group of relays operating on the bus is comprised of 10 relays. The matrix output relay groups only operate on 5 of the 10 signals of the bus and thus have only one control/status register associated with each group. For the rest of the relay groups an A and B control/status register pair is assigned to each group. Only bits 4-0 of the register are used. Bits 7-5 are not used and will display “111” when the status register is read. Register “A” is assigned to bus signals 4-0 while register “B: is assigned to bus signals 9-5.

The control registers are located in the VXI bus A24 address space. The A24 address for a control register depends on:

• • 1. The A24 Address Offset assigned to the command module by the resource manager program. The resource manager program is provided by the VXI bus slot-0 controller vendor. The A24 Address Offset is placed into the “Offset Register” of the command module by the Resource Manger.
  • 2. The <module address> of the matrix module have a value in the range of 1 through 12.
  • 3. Each control/status register on the matrix module has a unique address.
  • The base A24 address for the matrix module may be calculated by:(A24 Offset of Option-01T)+(1024×Module Address of the matrix module).
  • The A24 address offset is usually expressed in hexadecimal. A typical value of 204000₁₆ is used in the examples that follow. A matrix module with a module address of 6 would have the base A24 address computed as follows:Base A24 Address of matrix module=204000₁₆+(400₁₆×6₁₆)=205800₁₆
  • The control registers for these series of VXI modules are always on odd-numbered A24 Addresses. The first two control registers for the matrix module reside at the first two odd-numbered A24 addresses for the module:(Base A24 Address of matrix module)+1=Control Register 0;(Base A24 Address of matrix module)+3=Control Register 1;
  • So, for our example, the two control registers are located at:
  • 205801 for Control Register 0 and 205803 for Control Register1.

Table 3 below shows the Address assignment for each Control/Status register, while Table 4 shows the Control/Status Register Relay/Bus Assignments.

TABLE 0
Control/Status Register Address Offset Assignments
Control/Status	Address	Function
Reg. 00A	001	Input Bus to Matrix Bus ‘A’ (lower bus bits 4-0)
Reg. 00B	003	Input Bus to Matrix Bus ‘A’ (upper bus bits 9-5)
Reg. 01A	005	Bypass Matrix Bus ‘A’ to Internal Bus ‘B’
		(lower bus bits 4-0)
Reg. 01B	007	Bypass Matrix Bus ‘A’ to Internal Bus ‘B’
		(upper bus bits 9-5)
Reg. 02A	009	Internal Bus ‘B’ to Matrix Bus ‘B’ (lower
		bus bits 4-0)
Reg. 02B	00B	Internal Bus ‘B’ to Matrix Bus ‘B’ (upper
		bus bits 9-5)
Reg. 03A	00D	Bypass Matrix Bus ‘B’ to Internal Bus ‘C’
		(lower bus bits 4-0)
Reg. 03B	00F	Bypass Matrix Bus ‘B’ to Internal Bus ‘C’
		(upper bus bits 9-5)
Reg. 04A	011	Internal Bus ‘C’ to Matrix Bus ‘C’ (lower bus
		bits 4-0)
Reg. 04B	013	Internal Bus ‘C’ to Matrix Bus ‘C’ (upper bus
		bits 9-5)
Reg. 05A	015	Bypass Matrix Bus ‘C’ to Output Bus (lower
		bus bits 4-0)
Reg. 05B	017	Bypass Matrix Bus ‘C’ to Output Bus (upper
		bus bits 9-5)
Reg. 06A	019	Matrix Bus ‘A’ Stub Break 1 (lower bus bits 4-0)
Reg. 06B	01B	Matrix Bus ‘A’ Stub Break 1 (upper bus bits 9-5)
Reg. 07A	01D	Matrix Bus ‘A’ Stub Break 2 (lower bus bits 4-0)
Reg. 07B	01F	Matrix Bus ‘A’ Stub Break 2 (upper bus bits 9-5)
Reg. 08A	021	Matrix Bus ‘A’ Stub Break 3 (lower bus bits 4-0)
Reg. 08B	023	Matrix Bus ‘A’ Stub Break 3 (upper bus bits 9-5)
Reg. 09A	025	Matrix Bus ‘A’ Stub Break 4 (lower bus bits 4-0)
Reg. 09B	027	Matrix Bus ‘A’ Stub Break 4 (upper bus bits 9-5)
Reg. 10A	029	Matrix Bus ‘B’ Stub Break 1 (lower bus bits 4-0)
Reg. 10B	02B	Matrix Bus ‘B’ Stub Break 1 (upper bus bits 9-5)
Reg. 11A	02D	Matrix Bus ‘B’ Stub Break 2 (lower bus bits 4-0)
Reg. 11B	02F	Matrix Bus ‘B’ Stub Break 2 (upper bus bits 9-5)
Reg. 12A	031	Matrix Bus ‘B’ Stub Break 3 (lower bus bits 4-0)
Reg. 12B	033	Matrix Bus ‘B’ Stub Break 3 (upper bus bits 9-5)
Reserved	035-03F
Reg. 13A	041	Matrix Bus ‘B’ Stub Break 4 (lower bus bits 4-0)
Reg. 13B	043	Matrix Bus ‘B’ Stub Break 4 (upper bus bits 9-5)
Reg. 14A	045	Matrix Bus ‘C’ Stub Break 1 (lower bus bits 4-0)
Reg. 14B	047	Matrix Bus ‘C’ Stub Break 1 (upper bus bits 9-5)
Reg. 15A	049	Matrix Bus ‘C’ Stub Break 2 (lower bus bits 4-0)
Reg. 15B	04B	Matrix Bus ‘C’ Stub Break 2 (upper bus bits 9-5)
Reg. 16A	04D	Matrix Bus ‘C’ Stub Break 3 (lower bus bits 4-0)
Reg. 16B	04F	Matrix Bus ‘C’ Stub Break 3 (upper bus bits 9-5)
Reg. 17A	051	Matrix Bus ‘C’ Stub Break 4 (lower bus bits 4-0)
Reg. 17B	053	Matrix Bus ‘C’ Stub Break 4 (upper bus bits 9-5)
Reg. 18A	055	Matrix Bus ‘A’ Pull-up/Pull-down for Load 1
Reg. 18B	057	Matrix Bus ‘A’ Pull-up/Pull-down for Load 2
Reg. 19A	059	Matrix Bus ‘A’ Resistor Selection for Load 1
Reg. 19B	05B	Matrix Bus ‘A’ Resistor Selection for Load 2
Reg. 20A	05D	Matrix Bus ‘A’ Load 1 Connection (lower bus
		bits 4-0)
Reg. 20B	05F	Matrix Bus ‘A’ Load 1 Connection (upper bus
		bits 9-5)
Reg. 21A	061	Matrix Bus ‘A’ Load 2 Connection (lower bus
		bits 4-0)
Reg. 21B	063	Matrix Bus ‘A’ Load 2 Connection (upper bus
		bits 9-5)
Reg. 22A	065	Matrix Bus ‘B’ Pull-up/Pull-down for Load 1
Reg. 22B	067	Matrix Bus ‘B’ Pull-up/Pull-down for Load 2
Reg. 23A	069	Matrix Bus ‘B’ Resistor Selection for Load 1
Reg. 23B	06B	Matrix Bus ‘B’ Resistor Selection for Load 2
Reg. 24A	06D	Matrix Bus ‘B’ Load 1 Connection (lower bus
		bits 4-0)
Reg. 24B	06F	Matrix Bus ‘B’ Load 1 Connection (upper bus
		bits 9-5)
Reg. 25A	071	Matrix Bus ‘B’ Load 2 Connection (lower bus
		bits 4-0)
Reg. 25B	073	Matrix Bus ‘B’ Load 2 Connection (upper bus
		bits 9-5)
Reserved	075-07F
Reg. 26A	081	Matrix Bus ‘C’ Pull-up/Pull-down for Load 1
Reg. 26B	083	Matrix Bus ‘C’ Pull-up/Pull-down for Load 2
Reg. 27A	085	Matrix Bus ‘C’ Resistor Selection for Load 1
Reg. 27B	087	Matrix Bus ‘C’ Resistor Selection for Load 2
Reg. 28A	089	Matrix Bus ‘C’ Load 1 Connection (lower bus
		bits 4-0)
Reg. 28B	08B	Matrix Bus ‘C’ Load 1 Connection (upper bus
		bits 9-5)
Reg. 29A	08D	Matrix Bus ‘C’ Load 2 Connection (lower bus
		bits 4-0)
Reg. 29B	08F	Matrix Bus ‘C’ Load 2 Connection (upper bus
		bits 9-5)
Reg. 30A	091	Matrix Bus ‘A’ Instrument Input 1 (lower bus
		bits 4-0)
Reg. 30B	093	Matrix Bus ‘A’ Instrument Input 1 (upper bus
		bits 9-5)
Reg. 31A	095	Matrix Bus ‘A’ Instrument Input 2 (lower bus
		bits 4-0)
Reg. 31B	097	Matrix Bus ‘A’ Instrument Input 2 (upper bus
		bits 9-5)
Reg. 32A	099	Matrix Bus ‘A’ Instrument Input 3 (lower bus
		bits 4-0)
Reg. 32B	09B	Matrix Bus ‘A’ Instrument Input 3 (upper bus
		bits 9-5)
Reg. 33A	09D	Matrix Bus ‘A’ Instrument Input 4 (lower bus
		bits 4-0)
Reg. 33B	09F	Matrix Bus ‘A’ Instrument Input 4 (upper bus
		bits 9-5)
Reg. 34A	0A1	Matrix Bus ‘A’ Instrument Input 5 (lower bus
		bits 4-0)
Reg. 34B	0A3	Matrix Bus ‘A’ Instrument Input 5 (upper bus
		bits 9-5)
Reg. 35A	0A5	Matrix Bus ‘A’ Instrument Input 6 (lower bus
		bits 4-0)
Reg. 35B	0A7	Matrix Bus ‘A’ Instrument Input 6 (upper bus
		bits 9-5)
Reg. 36A	0A9	Matrix Bus ‘A’ Instrument Input 7 (lower bus
		bits 4-0)
Reg. 36B	0AB	Matrix Bus ‘A’ Instrument Input 7 (upper bus
		bits 9-5)
Reg. 37A	0AD	Matrix Bus ‘A’ Instrument Input 8 (lower bus
		bits 4-0)
Reg. 37B	0AF	Matrix Bus ‘A’ Instrument Input 8 (upper bus
		bits 9-5)
Reg. 38	0B1	Matrix Bus ‘A’ Output 1
Reg. 39	0B3	Matrix Bus ‘A’ Output 2
Reserved	0B5-0BF
Reg. 40	0C1	Matrix Bus ‘A’ Output 3
Reg. 41	0C3	Matrix Bus ‘A’ Output 4
Reg. 42	0C5	Matrix Bus ‘A’ Output 5
Reg. 43	0C7	Matrix Bus ‘A’ Output 6
Reg. 44	0C9	Matrix Bus ‘A’ Output 7
Reg. 45	0CB	Matrix Bus ‘A’ Output 8
Reg. 46	0CD	Matrix Bus ‘A’ Output 9
Reg. 47	0CF	Matrix Bus ‘A’ Output 10
Reg. 48	0D1	Matrix Bus ‘A’ Output 11
Reg. 49	0D3	Matrix Bus ‘A’ Output 12
Reg. 50	0D5	Matrix Bus ‘A’ Output 13
Reg. 51	0D7	Matrix Bus ‘A’ Output 14
Reg. 52	0D9	Matrix Bus ‘A’ Output 15
Reg. 53	0DB	Matrix Bus ‘A’ Output 16
Reg. 54	0DD	Matrix Bus ‘A’ Output 17
Reg. 55	0DF	Matrix Bus ‘A’ Output 18
Reg. 56	0E1	Matrix Bus ‘A’ Output 19
Reg. 57	0E3	Matrix Bus ‘A’ Output 20
Reg. 58	0E5	Matrix Bus ‘A’ Output 21
Reg. 59	0E7	Matrix Bus ‘A’ Output 22
Reg. 60	0E9	Matrix Bus ‘A’ Output 23
Reg. 61	0EB	Matrix Bus ‘A’ Output 24
Reg. 62A	0ED	Matrix Bus ‘B’ Instrument Input 1 (lower bus
		bits 4-0)
Reg. 62B	0EF	Matrix Bus ‘B’ Instrument Input 1 (upper bus
		bits 9-5)
Reg. 63A	0F1	Matrix Bus ‘B’ Instrument Input 2 (lower bus
		bits 4-0)
Reg. 63B	0F3	Matrix Bus ‘B’ Instrument Input 2 (upper bus
		bits 9-5)
Reserved	0F5-0FF
Reg. 64A	101	Matrix Bus ‘B’ Instrument Input 3 (lower bus
		bits 4-0)
Reg. 64B	103	Matrix Bus ‘B’ Instrument Input 3 (upper bus
		bits 9-5)
Reg. 65A	105	Matrix Bus ‘B’ Instrument Input 4 (lower bus
		bits 4-0)
Reg. 65B	107	Matrix Bus ‘B’ Instrument Input 4 (upper bus
		bits 9-5)
Reg. 66A	109	Matrix Bus ‘B’ Instrument Input 5 (lower bus
		bits 4-0)
Reg. 66B	10B	Matrix Bus ‘B’ Instrument Input 5 (upper bus
		bits 9-5)
Reg. 67A	10D	Matrix Bus ‘B’ Instrument Input 6 (lower bus
		bits 4-0)
Reg. 67B	10F	Matrix Bus ‘B’ Instrument Input 6 (upper bus
		bits 9-5)
Reg. 68A	111	Matrix Bus ‘B’ Instrument Input 7 (lower bus
		bits 4-0)
Reg. 68B	113	Matrix Bus ‘B’ Instrument Input 7 (upper bus
		bits 9-5)
Reg. 69A	115	Matrix Bus ‘B’ Instrument Input 8 (lower bus
		bits 4-0)
Reg. 69B	117	Matrix Bus ‘B’ Instrument Input 8 (upper bus
		bits 9-5)
Reg. 70	119	Matrix Bus ‘B’ Output 1
Reg. 71	11B	Matrix Bus ‘B’ Output 2
Reg. 72	11D	Matrix Bus ‘B’ Output 3
Reg. 73	11F	Matrix Bus ‘B’ Output 4
Reg. 74	121	Matrix Bus ‘B’ Output 5
Reg. 75	123	Matrix Bus ‘B’ Output 6
Reg. 76	125	Matrix Bus ‘B’ Output 7
Reg. 77	127	Matrix Bus ‘B’ Output 8
Reg. 78	129	Matrix Bus ‘B’ Output 9
Reg. 79	12B	Matrix Bus ‘B’ Output 10
Reg. 80	12D	Matrix Bus ‘B’ Output 11
Reg. 81	12F	Matrix Bus ‘B’ Output 12
Reg. 82	131	Matrix Bus ‘B’ Output 13
Reg. 83	133	Matrix Bus ‘B’ Output 14
Reserved	135-13F
Reg. 84	141	Matrix Bus ‘B’ Output 15
Reg. 85	143	Matrix Bus ‘B’ Output 16
Reg. 86	145	Matrix Bus ‘B’ Output 17
Reg. 87	147	Matrix Bus ‘B’ Output 18
Reg. 88	149	Matrix Bus ‘B’ Output 19
Reg. 89	14B	Matrix Bus ‘B’ Output 20
Reg. 90	14D	Matrix Bus ‘B’ Output 21
Reg. 91	14F	Matrix Bus ‘B’ Output 22
Reg. 92	151	Matrix Bus ‘B’ Output 23
Reg. 93	153	Matrix Bus ‘B’ Output 24
Reg. 94A	155	Matrix Bus ‘C’ Instrument Input 1 (lower bus
		bits 4-0)
Reg. 94B	157	Matrix Bus ‘C’ Instrument Input 1 (upper bus
		bits 9-5)
Reg. 95A	159	Matrix Bus ‘C’ Instrument Input 2 (lower bus
		bits 4-0)
Reg. 95B	15B	Matrix Bus ‘C’ Instrument Input 2 (upper bus
		bits 9-5)
Reg. 96A	15D	Matrix Bus ‘C’ Instrument Input 3 (lower bus
		bits 4-0)
Reg. 96B	15F	Matrix Bus ‘C’ Instrument Input 3 (upper bus
		bits 9-5)
Reg. 97A	161	Matrix Bus ‘C’ Instrument Input 4 (lower bus
		bits 4-0)
Reg. 97B	163	Matrix Bus ‘C’ Instrument Input 4 (upper bus
		bits 9-5)
Reg. 98A	165	Matrix Bus ‘C’ Instrument Input 5 (lower bus
		bits 4-0)
Reg. 98B	167	Matrix Bus ‘C’ Instrument Input 5 (upper bus
		bits 9-5)
Reg. 99A	169	Matrix Bus ‘C’ Instrument Input 6 (lower bus
		bits 4-0)
Reg. 99B	16B	Matrix Bus ‘C’ Instrument Input 6 (upper bus
		bits 9-5)
Reg. 100A	16D	Matrix Bus ‘C’ Instrument Input 7 (lower bus
		bits 4-0)
Reg. 100B	16F	Matrix Bus ‘C’ Instrument Input 7 (upper bus
		bits 9-5)
Reg. 101A	171	Matrix Bus ‘C’ Instrument Input 8 (lower bus
		bits 4-0)
Reg. 101B	173	Matrix Bus ‘C’ Instrument Input 8 (upper bus
		bits 9-5)
Reserved	175-17F
Reg. 102	181	Matrix Bus ‘C’ Output 1
Reg. 103	183	Matrix Bus ‘C’ Output 2
Reg. 104	185	Matrix Bus ‘C’ Output 3
Reg. 105	187	Matrix Bus ‘C’ Output 4
Reg. 106	189	Matrix Bus ‘C’ Output 5
Reg. 107	18B	Matrix Bus ‘C’ Output 6
Reg. 108	18D	Matrix Bus ‘C’ Output 7
Reg. 109	18F	Matrix Bus ‘C’ Output 8
Reg. 110	191	Matrix Bus ‘C’ Output 9
Reg. 111	193	Matrix Bus ‘C’ Output 10
Reg. 112	195	Matrix Bus ‘C’ Output 11
Reg. 113	197	Matrix Bus ‘C’ Output 12
Reg. 114	199	Matrix Bus ‘C’ Output 13
Reg. 115	19B	Matrix Bus ‘C’ Output 14
Reg. 116	19D	Matrix Bus ‘C’ Output 15
Reg. 117	19F	Matrix Bus ‘C’ Output 16
Reg. 118	1A1	Matrix Bus ‘C’ Output 17
Reg. 119	1A3	Matrix Bus ‘C’ Output 18
Reg. 120	1A5	Matrix Bus ‘C’ Output 19
Reg. 121	1A7	Matrix Bus ‘C’ Output 20
Reg. 122	1A9	Matrix Bus ‘C’ Output 21
Reg. 123	1AB	Matrix Bus ‘C’ Output 22
Reg. 124	1AD	Matrix Bus ‘C’ Output 23
Reg. 125	1AF	Matrix Bus ‘C’ Output 24
ID Byte	201	Identification Byte (Read Only)
EPROM	203	EPROM Data (Read Only)

TABLE 4
Control/Status Register Relay Assignments
Control/Status	Bit 7							Bit 0
Register	(MSB)	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	(LSB)
	Input Bus to Matrix Bus ‘A’ (lower bus bits 4-0)
Reg. 00A	NC	NC	NC	K5	K4	K3	K2	K1
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Input Bus to Matrix Bus ‘A’ (upper bus bits 9-5)
Reg. 00B	NC	NC	NC	K15	K14	K13	K12	K11
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Bypass Matrix Bus ‘A’ to Internal Bus ‘B’ (lower bus bits 4-0)
Reg. 01A	NC	NC	NC	K10	K9	K8	K7	K6
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Bypass Matrix Bus ‘A’ to Internal Bus ‘B’ (upper bus bits 9-5)
Reg. 01B	NC	NC	NC	K20	K19	K18	K17	K16
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Internal Bus ‘B’ to Matrix Bus ‘B’ (lower bus bits 4-0)
Reg. 02A	NC	NC	NC	K25	K24	K23	K22	K21
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Internal Bus ‘B’ to Matrix Bus ‘B’ (upper bus bits 9-5)
Reg. 02B	NC	NC	NC	K35	K34	K33	K32	K31
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Bypass Matrix Bus ‘B’ to Internal Bus ‘C’ (lower bus bits 4-0)
Reg. 03A	NC	NC	NC	K30	K29	K28	K27	K26
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Bypass Matrix Bus ‘B’ to Internal Bus ‘C’ (upper bus bits 9-5)
Reg. 03B	NC	NC	NC	K40	K39	K38	K37	K36
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Internal Bus ‘C’ to Matrix Bus ‘C’ (lower bus bits 4-0)
Reg. 04A	NC	NC	NC	K45	K44	K43	K42	K41
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Internal Bus ‘C’ to Matrix Bus ‘C’ (upper bus bits 9-5)
Reg. 04B	NC	NC	NC	K55	K54	K53	K52	K51
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Bypass Matrix Bus ‘C’ to Output Bus (lower bus bits 4-0)
Reg. 05A	NC	NC	NC	K50	K49	K48	K47	K46
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Bypass Matrix Bus ‘C’ to Output Bus (upper bus bits 9-5)
Reg. 05B	NC	NC	NC	K60	K59	K58	K57	K56
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Stub Break 1 (lower bus bits 4-0)
Reg. 06A	NC	NC	NC	K65	K64	K63	K62	K61
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Stub Break 1 (upper bus bits 9-5)
Reg. 06B	NC	NC	NC	K85	K84	K83	K82	K81
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Stub Break 2 (lower bus bits 4-0)
Reg. 07A	NC	NC	NC	K70	K69	K68	K67	K66
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Stub Break 2 (upper bus bits 9-5)
Reg. 07B	NC	NC	NC	K90	K89	K88	K87	K86
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Stub Break 3 (lower bus bits 4-0)
Reg. 08A	NC	NC	NC	K79	K77	K75	K73	K71
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Stub Break 3 (upper bus bits 9-5)
Reg. 08B	NC	NC	NC	K99	K97	K95	K93	K91
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Stub Break 4 (lower bus bits 4-0)
Reg. 09A	NC	NC	NC	K80	K78	K76	K74	K72
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Stub Break 4 (upper bus bits 9-5)
Reg. 09B	NC	NC	NC	K100	K98	K96	K94	K92
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Stub Break 1 (lower bus bits 4-0)
Reg. 10A	NC	NC	NC	K105	K104	K103	K102	K101
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Stub Break 1 (upper bus bits 9-5)
Reg. 10B	NC	NC	NC	K125	K124	K123	K122	K121
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Stub Break 2 (lower bus bits 4-0)
Reg. 11A	NC	NC	NC	K110	K109	K108	K107	K106
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Stub Break 2 (upper bus bits 9-5)
Reg. 11B	NC	NC	NC	K130	K129	K128	K127	K126
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Stub Break 3 (lower bus bits 4-0)
Reg. 12A	NC	NC	NC	K119	K117	K115	K113	K111
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Stub Break 3 (upper bus bits 9-5)
Reg. 12B	NC	NC	NC	K139	K137	K135	K133	K131
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Stub Break 4 (lower bus bits 4-0)
Reg. 13A	NC	NC	NC	K120	K118	K116	K114	K112
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Stub Break 4 (upper bus bits 9-5)
Reg. 13B	NC	NC	NC	K140	K138	K136	K134	K132
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Stub Break 1 (lower bus bits 4-0)
Reg. 14A	NC	NC	NC	K145	K144	K143	K142	K141
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Stub Break 1 (upper bus bits 9-5)
Reg. 14B	NC	NC	NC	K165	K164	K163	K162	K161
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Stub Break 2 (lower bus bits 4-0)
Reg. 15A	NC	NC	NC	K150	K149	K148	K147	K146
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Stub Break 2 (upper bus bits 9-5)
Reg. 15B	NC	NC	NC	K170	K169	K168	K167	K166
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Stub Break 3 (lower bus bits 4-0)
Reg. 16A	NC	NC	NC	K159	K157	K155	K153	K151
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Stub Break 3 (upper bus bits 9-5)
Reg. 16B	NC	NC	NC	K179	K177	K175	K173	K171
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Stub Break 4 (lower bus bits 4-0)
Reg. 17A	NC	NC	NC	K160	K158	K156	K154	K152
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Stub Break 4 (upper bus bits 9-5)
Reg. 17B	NC	NC	NC	K180	K178	K176	K174	K172
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Pull-up/Pull-down for Load 1
Reg. 18A	NC	NC	NC	K185	K184	K183	K182	K181
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Pull-up/Pull-down for Load 2
Reg. 18B	NC	NC	NC	K195	K194	K193	K192	K191
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Resistor Selection for Load 1
Reg. 19A	NC	NC	NC	K190	K189	K188	K187	K186
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Resistor Selection for Load 2
Reg. 19B	NC	NC	NC	K200	K199	K198	K197	K196
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Load 1 Connection (lower bus bits 4-0)
Reg. 20A	NC	NC	NC	K205	K204	K203	K202	K201
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Load 1 Connection (upper bus bits 9-5)
Reg. 20B	NC	NC	NC	K210	K209	K208	K207	K206
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Load 2 Connection (lower bus bits 4-0)
Reg. 21A	NC	NC	NC	K215	K214	K213	K212	K211
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Load 2 Connection (upper bus bits 9-5)
Reg. 21B	NC	NC	NC	K220	K219	K218	K217	K216
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Pull-up/Pull-down for Load 1
Reg. 22A	NC	NC	NC	K225	K224	K223	K222	K221
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrtx Bus ‘B’ Pull-up/Pull-down for Load 2
Reg. 22B	NC	NC	NC	K235	K234	K233	K232	K231
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Resistor Selection for Load 1
Reg. 23A	NC	NC	NC	K230	K229	K228	K227	K226
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Resistor Selection for Load 2
Reg. 23B	NC	NC	NC	K240	K239	K238	K237	K236
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Load 1 Connection (lower bus bits 4-0)
Reg. 24A	NC	NC	NC	K245	K244	K243	K242	K241
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Load 1 Connection (upper bus bits 9-5)
Reg. 24B	NC	NC	NC	K250	K249	K248	K247	K246
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Load 2 Connection (lower bus bits 4-0)
Reg. 25A	NC	NC	NC	K255	K254	K253	K252	K251
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Load 2 Connection (upper bus bits 9-5)
Reg. 25B	NC	NC	NC	K260	K259	K258	K257	K256
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Pull-up/Pull-down for Load 1
Reg. 26A	NC	NC	NC	K265	K264	K263	K262	K261
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Pull-up/Pull-down for Load 2
Reg. 26B	NC	NC	NC	K275	K274	K273	K272	K271
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Resistor Selection for Load 1
Reg. 27A	NC	NC	NC	K270	K269	K268	K267	K266
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Resistor Selection for Load 2
Reg. 27B	NC	NC	NC	K280	K279	K278	K277	K276
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Load 1 Connection (lower bus bits 4-0)
Reg. 28A	NC	NC	NC	K285	K284	K283	K282	K281
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Load 1 Connection (upper bus bits 9-5)
Reg. 28B	NC	NC	NC	K290	K289	K288	K287	K286
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Load 2 Connection (lower bus bits 4-0)
Reg. 29A	NC	NC	NC	K295	K294	K293	K292	K291
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Load 2 Connection (upper bus bits 9-5)
Reg. 29B	NC	NC	NC	K300	K299	K298	K297	K296
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 1 (lower bus bits 4-0)
Reg. 30A	NC	NC	NC	K305	K304	K303	K302	K301
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 1 (upper bus bits 9-5)
Reg. 30B	NC	NC	NC	K310	K309	K308	K307	K306
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 2 (lower bus bits 4-0)
Reg. 31A	NC	NC	NC	K315	K314	K313	K312	K311
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 2 (upper bus bits 9-5)
Reg. 31B	NC	NC	NC	K320	K319	K318	K317	K316
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 3 (lower bus bits 4-0)
Reg. 32A	NC	NC	NC	K325	K324	K323	K322	K321
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 3 (upper bus bits 9-5)
Reg. 32B	NC	NC	NC	K330	K329	K328	K327	K326
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 4 (lower bus bits 4-0)
Reg. 33A	NC	NC	NC	K335	K334	K333	K332	K331
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 4 (upper bus bits 9-5)
Reg. 33B	NC	NC	NC	K340	K339	K338	K337	K336
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ instrument Input 5 (lower bus bits 4-0)
Reg. 34A	NC	NC	NC	K345	K344	K343	K342	K341
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 5 (upper bus bits 9-5)
Reg. 34B	NC	NC	NC	K350	K349	K348	K347	K346
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 6 (lower bus bits 4-0)
Reg. 35A	NC	NC	NC	K355	K354	K353	K352	K351
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 6 (upper bus bits 9-5)
Reg. 35B	NC	NC	NC	K360	K359	K358	K357	K356
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 7 (lower bus bits 4-0)
Reg. 36A	NC	NC	NC	K365	K364	K363	K362	K361
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 7 (upper bus bits 9-5)
Reg. 36B	NC	NC	NC	K370	K369	K368	K367	K366
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Instrument Input 8 (lower bus bits 4-0)
Reg. 37A	NC	NC	NC	K375	K374	K373	K372	K371
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Instrument Input 8 (upper bus bits 9-5)
Reg. 37B	NC	NC	NC	K380	K379	K378	K377	K376
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘A’ Output 1
Reg. 38	NC	NC	NC	K385	K384	K383	K382	K381
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 2
Reg. 39	NC	NC	NC	K390	K389	K388	K387	K386
				Bus 7	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 3
Reg. 40	NC	NC	NC	K395	K394	K393	K392	K391
				Bus 6	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 4
Reg. 41	NC	NC	NC	K400	K399	K398	K397	K396
				Bus 6	Bus 4	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 5
Reg. 42	NC	NC	NC	K405	K404	K403	K402	K401
				Bus 5	Bus 4	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 6
Reg. 43	NC	NC	NC	K410	K409	K408	K407	K406
				Bus 5	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 7
Reg. 44	NC	NC	NC	K415	K414	K413	K412	K411
				Bus 7	Bus 6	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 8
Reg. 45	NC	NC	NC	K420	K419	K418	K417	K416
				Bus 7	Bus 4	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 9
Reg. 46	NC	NC	NC	K425	K424	K423	K422	K421
				Bus 7	Bus 5	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 10
Reg. 47	NC	NC	NC	K430	K429	K428	K427	K426
				Bus 5	Bus 4	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 11
Reg. 48	NC	NC	NC	K435	K434	K433	K432	K431
				Bus 6	Bus 4	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 12
Reg. 49	NC	NC	NC	K440	K439	K438	K437	K436
				Bus 6	Bus 5	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 13
Reg. 50	NC	NC	NC	K445	K444	K443	K442	K441
				Bus 6	Bus 4	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 14
Reg. 51	NC	NC	NC	K450	K449	K448	K447	K446
				Bus 7	Bus 4	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 15
Reg. 52	NC	NC	NC	K455	K454	K453	K452	K451
				Bus 8	Bus 4	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 16
Reg. 53	NC	NC	NC	K460	K459	K458	K457	K456
				Bus 8	Bus 5	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 17
Reg. 54	NC	NC	NC	K465	K464	K463	K462	K461
				Bus 7	Bus 5	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 18
Reg. 55	NC	NC	NC	K470	K469	K468	K467	K466
				Bus 6	Bus 5	Bus 3	Bus 2	Bus 0
	Matrix Bus ‘A’ Output 19
Reg. 56	NC	NC	NC	K475	K474	K473	K472	K471
				Bus 8	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 20
Reg. 57	NC	NC	NC	K480	K479	K478	K477	K476
				Bus 8	Bus 6	Bus 4	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 21
Reg. 58	NC	NC	NC	K485	K484	K483	K482	K481
				Bus 7	Bus 4	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 22
Reg. 59	NC	NC	NC	K490	K489	K488	K487	K486
				Bus 7	Bus 6	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 23
Reg. 60	NC	NC	NC	K495	K494	K493	K492	K491
				Bus 6	Bus 5	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘A’ Output 24
Reg. 61	NC	NC	NC	K500	K499	K498	K497	K496
				Bus 7	Bus 5	Bus 3	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 1 (lower bus bits 4-0)
Reg. 62A	NC	NC	NC	K505	K504	K503	K502	K501
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 1 (upper bus bits 9-5)
Reg. 62B	NC	NC	NC	K510	K509	K508	K507	K506
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Instrument Input 2 (lower bus bits 4-0)
Reg. 63A	NC	NC	NC	K515	K514	K513	K512	K511
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 2 (upper bus bits 9-5)
Reg. 63B	NC	NC	NC	K520	K519	K518	K517	K516
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ instrument Input 3 (lower bus bits 4-0)
Reg. 64A	NC	NC	NC	K525	K524	K523	K522	K521
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ instrument Input 3 (upper bus bits 9-5)
Reg. 64B	NC	NC	NC	K530	K529	K528	K527	K526
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Instrument Input 4 (lower bus bits 4-0)
Reg. 65A	NC	NC	NC	K535	K534	K533	K532	K531
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrtx Bus ‘B’ Instrument Input 4 (upper bus bits 9-5)
Reg. 65B	NC	NC	NC	K540	K539	K538	K537	K536
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Instrument Input 5 (lower bus bits 4-0)
Reg. 66A	NC	NC	NC	K545	K544	K543	K542	K541
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 5 (upper bus bits 9-5)
Reg. 66B	NC	NC	NC	K550	K549	K548	K547	K546
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrtx Bus ‘B’ Instrument Input 6 (lower bus bits 4-0)
Reg. 67A	NC	NC	NC	K555	K554	K553	K552	K551
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 6 (upper bus bits 9-5)
Reg. 67B	NC	NC	NC	K560	K559	K558	K557	K556
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Instrument Input 7 (lower bus bits 4-0)
Reg. 68A	NC	NC	NC	K565	K564	K563	K562	K561
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 7 (upper bus bits 9-5)
Reg. 68B	NC	NC	NC	Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
				K570	K569	K568	K567	K566
	Matrix Bus ‘B’ Instrument Input 8 (lower bus bits 4-0)
Reg. 69A	NC	NC	NC	K575	K574	K573	K572	K571
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘B’ Instrument Input 8 (upper bus bits 9-5)
Reg. 69B	NC	NC	NC	K580	K579	K578	K577	K576
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘B’ Output 1
Reg. 70	NC	NC	NC	K585	K584	K583	K582	K581
				Bus 5	Bus 4	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 2
Reg. 71	NC	NC	NC	K590	K589	K588	K587	K586
				Bus 8	Bus 4	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 3
Reg. 72	NC	NC	NC	K595	K594	K593	K592	K591
				Bus 7	Bus 4	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 4
Reg. 73	NC	NC	NC	K600	K599	K598	K597	K596
				Bus 7	Bus 5	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 5
Reg. 74	NC	NC	NC	K605	K604	K603	K602	K601
				Bus 6	Bus 5	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 6
Reg. 75	NC	NC	NC	K610	K609	K608	K607	K606
				Bus 6	Bus 4	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 7
Reg. 76	NC	NC	NC	K615	K614	K613	K612	K611
				Bus 8	Bus 7	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 8
Reg. 77	NC	NC	NC	K620	K619	K618	K617	K616
				Bus 8	Bus 5	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 9
Reg. 78	NC	NC	NC	K625	K624	K623	K622	K621
				Bus 8	Bus 6	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 10
Reg. 79	NC	NC	NC	K630	K629	K628	K627	K626
				Bus 6	Bus 5	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 11
Reg. 80	NC	NC	NC	K635	K634	K633	K632	K631
				Bus 7	Bus 5	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 12
Reg. 81	NC	NC	NC	K640	K639	K638	K637	K636
				Bus 7	Bus 6	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 13
Reg. 82	NC	NC	NC	K645	K644	K643	K642	K641
				Bus 7	Bus 5	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 14
Reg. 83	NC	NC	NC	K650	K649	K648	K647	K646
				Bus 8	Bus 5	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 15
Reg. 84	NC	NC	NC	K655	K654	K653	K652	K651
				Bus 9	Bus 5	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 16
Reg. 85	NC	NC	NC	K660	K659	K658	K657	K656
				Bus 9	Bus 6	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 17
Reg. 86	NC	NC	NC	K665	K664	K663	K662	K661
				Bus 8	Bus 6	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 18
Reg. 87	NC	NC	NC	K670	K669	K668	K667	K666
				Bus 7	Bus 6	Bus 4	Bus 3	Bus 1
	Matrix Bus ‘B’ Output 19
Reg. 88	NC	NC	NC	K675	K674	K673	K672	K671
				Bus 9	Bus 4	Bus 3	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 20
Reg. 89	NC	NC	NC	K680	K679	K678	K677	K676
				Bus 9	Bus 7	Bus 5	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 21
Reg. 90	NC	NC	NC	K685	K684	K683	K682	K681
				Bus 8	Bus 5	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 22
Reg. 91	NC	NC	NC	K690	K689	K688	K687	K686
				Bus 8	Bus 7	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 23
Reg. 92	NC	NC	NC	K695	K694	K693	K692	K691
				Bus 7	Bus 6	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘B’ Output 24
Reg. 93	NC	NC	NC	K700	K699	K698	K697	K696
				Bus 8	Bus 6	Bus 4	Bus 2	Bus 1
	Matrix Bus ‘C’ Instrument Input 1 (lower bus bits 4-0)
Reg. 94A	NC	NC	NC	K705	K704	K703	K702	K701
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 1 (upper bus bits 9-5)
Reg. 94B	NC	NC	NC	K710	K709	K708	K707	K706
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 2 (lower bus bits 4-0)
Reg. 95A	NC	NC	NC	K715	K714	K713	K712	K711
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 2 (upper bus bits 9-5)
Reg. 95B	NC	NC	NC	K720	K719	K718	K717	K716
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 3 (lower bus bits 4-0)
Reg. 96A	NC	NC	NC	K725	K724	K723	K722	K721
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 3 (upper bus bits 9-5)
Reg. 96B	NC	NC	NC	K730	K729	K728	K727	K726
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ instrument Input 4 (lower bus bits 4-0)
Reg. 97A	NC	NC	NC	K735	K734	K733	K732	K731
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 4 (upper bus bits 9-5)
Reg. 97B	NC	NC	NC	K740	K739	K738	K737	K736
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 5 (lower bus bits 4-0)
Reg. 98A	NC	NC	NC	K745	K744	K743	K742	K741
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 5 (upper bus bits 9-5)
Reg. 98B	NC	NC	NC	K750	K749	K748	K747	K746
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 6 (lower bus bits 4-0)
Reg. 99A	NC	NC	NC	K755	K754	K753	K752	K751
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 8 (upper bus bits 9-5)
Reg. 99B	NC	NC	NC	K760	K759	K758	K757	K756
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 7 (lower bus bits 4-0)
Reg. 100A	NC	NC	NC	K765	K764	K763	K762	K761
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ instrument Input 7 (upper bus bits 9-5)
Reg. 100B	NC	NC	NC	K770	K769	K768	K767	K766
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Instrument Input 8 (lower bus bits 4-0)
Reg. 101A	NC	NC	NC	K775	K774	K773	K772	K771
				Bus 4	Bus 3	Bus 2	Bus 1	Bus 0
	Matrix Bus ‘C’ Instrument Input 8 (upper bus bits 9-5)
Reg. 101B	NC	NC	NC	K780	K779	K778	K777	K776
				Bus 9	Bus 8	Bus 7	Bus 6	Bus 5
	Matrix Bus ‘C’ Output 1
Reg. 102	NC	NC	NC	K785	K784	K783	K782	K781
				Bus 6	Bus 5	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 2
Reg. 103	NC	NC	NC	K790	K789	K788	K787	K786
				Bus 9	Bus 5	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 3
Reg. 104	NC	NC	NC	K795	K794	K793	K792	K791
				Bus 8	Bus 5	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 4
Reg. 105	NC	NC	NC	K800	K799	K798	K797	K796
				Bus 8	Bus 6	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 5
Reg. 106	NC	NC	NC	K805	K804	K803	K802	K801
				Bus 7	Bus 6	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 6
Reg. 107	NC	NC	NC	K810	K809	K808	K807	K806
				Bus 7	Bus 5	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 7
Reg. 108	NC	NC	NC	K815	K814	K813	K812	K811
				Bus 9	Bus 8	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 8
Reg. 109	NC	NC	NC	K820	K819	K818	K817	K816
				Bus 9	Bus 6	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 9
Reg. 110	NC	NC	NC	K825	K824	K823	K822	K821
				Bus 9	Bus 7	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 10
Reg. 111	NC	NC	NC	K830	K829	K828	K827	K826
				Bus 7	Bus 6	Bus 5	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 11
Reg. 112	NC	NC	NC	K835	K834	K833	K832	K831
				Bus 8	Bus 6	Bus 5	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 12
Reg. 113	NC	NC	NC	K840	K839	K838	K837	K836
				Bus 8	Bus 7	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 13
Reg. 114	NC	NC	NC	K845	K844	K843	K842	K841
				Bus 8	Bus 6	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 14
Reg. 115	NC	NC	NC	K850	K849	K848	K847	K848
				Bus 9	Bus 6	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 15
Reg. 116	NC	NC	NC	K855	K854	K853	K852	K851
				Bus 0	Bus 6	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 16
Reg. 117	NC	NC	NC	K860	K859	K858	K857	K856
				Bus 0	Bus 7	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 17
Reg. 118	NC	NC	NC	K865	K864	K863	K862	K861
				Bus 9	Bus 7	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 18
Reg. 119	NC	NC	NC	K870	K869	K868	K867	K866
				Bus 8	Bus 7	Bus 5	Bus 4	Bus 2
	Matrix Bus ‘C’ Output 19
Reg. 120	NC	NC	NC	K875	K874	K873	K872	K871
				Bus 0	Bus 5	Bus 4	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 20
Reg. 121	NC	NC	NC	K880	K879	K878	K877	K876
				Bus 0	Bus 8	Bus 6	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 21
Reg. 122	NC	NC	NC	K885	K884	K883	K882	K881
				Bus 9	Bus 6	Bus 5	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 22
Reg. 123	NC	NC	NC	K890	K889	K888	K887	K886
				Bus 9	Bus 8	Bus 5	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 23
Reg. 124	NC	NC	NC	K895	K894	K893	K892	K891
				Bus 8	Bus 7	Bus 5	Bus 3	Bus 2
	Matrix Bus ‘C’ Output 24
Reg. 125	NC	NC	NC	K900	K899	K898	K897	K896
				Bus 9	Bus 7	Bus 5	Bus 3	Bus 2

In FIG. 9 there is shown a logical relay layout for a switch matrix modules in accordance with an embodiment of the invention. Each of the three 8×24 matrix 902, 904 and 906 are highlighted. Achieving the packaging of three 8×24 matrices into one VXI card slot required a large amount of consideration in the packaging of the relays. One solution was the connection of the over one thousand signals from the control board to the relay board which was accomplished by using 5 high density 200-pin connectors. Also, the nine hundred relays used in this embodiment were placed on two boards joined together with through interconnects. The bottom (mother board) contains all of the VXI interconnects and driver devices. The top (daughter board) card contains the switching components, with the design being single wire.

The diagram legend for the triple 8×24 matrix block diagram shown in FIG. 9 is as follows:

M=Bus select multiplexer (mux)

B=Inter-matrix bus select

S=Stub breaking relays

L=Load select multiplexer (mux)

P=Termination select

The design achieved parameters such as:

Path resistance: <900 mOhm

Bandwidth: >60 MHz

Isolation: >60 dB

Impedance: 50 Ohm

Impulse withstanding voltage: >1000 Vrms

Also shown in FIG. 9 are the programmable load terminations 908 which were previously discussed.

By adding stub breakers for every 4 relays in one embodiment of the invention, the bus can be broken off and unused portions of the matrix can be isolated. This minimizes frequency degradation due to unused stub lengths. With the implementation of “3-way: stub-breakers at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, larger matrices can be formed on the 10 lane expansion bus by daisy-chaining multiple switch matrix modules via the front panel. This is accomplished by connecting the J207 connector (see FIG. 7) of one switch matrix module to the J206 connection of the following switch matrix module. The stub breakers also allow for flexibility of configuration. For example, an 8×24 matrix can be configured as a 1×4 or other switch configuration through the application of the stub breakers. The programmability of the stub breakers allows for maximum flexibility in the design.

In FIG. 10 there is shown the front panel connectors for the triple 8×24 matrix module in accordance with one embodiment of the invention. By adding stub breakers for every 4 relays in one embodiment, the bus can be broken off and unused portions of the matrix can be isolated. This minimizes frequency degradation due to unused stub lengths. With the implementation of “3-way” stub breakers at the matrix front-ends that can either completely insolate a middle matrix or cut off stubs left or right of the destination and source matrices, larger matrices can be formed on the 10-lane expansion bus by daisy-chaining multiple matrices via their front panel connectors. This is accomplished by connecting the J207 connector of one matrix to the J206 connector of the following matrix, etc. A block diagram of the matrix module is shown in FIG. 11.

In FIG. 12 there is shown a block diagram of a switch matrix system in accordance with an embodiment of the invention. The system includes a controller such as a personal computer 1202 that includes a user application in communication with a matrix IVI com driver, which is in communication with a VISA block. An external communication interface couples the personal computer 1202 to the VXI chassis 1204 which includes the plurality of modules Module #1 to Module #N. The personal computer 1202 controls the switching of the different modules found in the VXI chassis 1204.

A static diagram of the path selection algorithm is shown in FIG. 13. Through the use of Mutually Exclusive Sets to represent switch topology which has enabled the invention to define switch cards for arbitrary topology which can still retain reasonable switch IVI driver performance. The algorithms for implementing IVI switch cards IVI-COM drivers are unique in nature. The switch topology is represented as a changing undirected graph amenable to standard graph theory algorithms.

One area of improvement in the invention is a Fast Path Lookup data structure. Previously, this was implemented with a basic array heap and hash table. In the invention, the software compiles a path search data structure which takes O(log 2 n) using a Red-Black tree embedded within a Red-Black tree. The advantages to this approach over hash table is that the Red-Black tree is always balanced so search for any path all takes roughly the same amount of time. The issue with hash table is that the search key in our case switch channel names are not randomly distributed over the alphabet. Hash tables rely on the fact that hash keys are randomly distributed evenly over the entire alphabet to be efficient. The hash function has to produce an even distribution otherwise, there will be an excessive number of collisions resulting in poor hash table insert and retrieve performance. This data structure is also unique in that it can store multiple alternative paths so that if one path is restricted, the driver can quickly search for other alternative paths which do not suffer from the same restrictions which has enabled us to be able to implement a complex highly interconnected topology such as the 1260-43. The Red-Black tree by itself is a standard computer science data structure. But a novel feature of the invention is the use of a Red-Black tree to create the Fast Path Lookup data structure. It is used essentially to create a dictionary map (channel 1 as key) each entry is another dictionary map which points a simple path, a composite path or an array of composite paths. The structure of this Fast Path Lookup table is showed in the UML diagram of FIG. 13. In the invention there is an option to turn off a “Best Path Searching Algorithm” from a complex to a simple mode. In the Complex Mode, in the invention, the IVI switch cores are enabled so that IVI switch features such as sources and configuration channels can be used. The driver can be set to operate in simple mode to disable these features so as to optimize the speed of switch drivers. The Simple mode allows the driver to close a channel which normally takes 50-150 ms (in complex mode) to around 1 ms (in simple mode). We are able to determine how to determine the best possible path by traversing though each edge of the graph representing our switch card and recursively walking the graph until we arrive at a best possible suitable path or until no path is found to satisfy the conditions.

While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A switch matrix module, comprising: a switch matrix having first and second expansion points;first and second three-way stub-breaker switches coupled respectively to the first and second expansion points;the switch matrix comprises a cross-point switch matrix and is located in a first printed circuit board;a second printed circuit board including: a second matrix switch having first and second expansion points;first and second three-way stub-breaker switches coupled respectively to the first and second expansion points; andwherein the first and second three-way stub-breaker switches coupled respectively to the first and second expansion points on the switch matrix located on the first printed circuit board includes upstream and downstream switches and the first and second three-way stub-breaker switches coupled respectively to the first and second expansion points on the second switch matrix located on the second printed circuit board also includes upstream and downstream switches, and wherein the downstream switch of the first three-way stub breaker switch located on the first printed circuit board is electrically connected to the upstream switch of the first three-way stub breaker switch located on the second printed circuit board.

2. A switch matrix module as defined in claim 1, wherein the cross-point switch matrix comprises a N×M matrix.

3. A switch matrix module as defined in claim 1, wherein the downstream switch of the second three-way stub breaker switch located on the first printed circuit board is electrically connected to the upstream switch of the second three-way stub breaker switch located on the second printed circuit board.

4. A switch matrix module as defined in claim 1 wherein the first and second three-way stub-breaker switches are programmable.

5. A switch matrix module as defined in claim 4 further comprising: an expansion bus coupled to the switch matrix anda programmable load termination set to one of a plurality of different values and accuracies coupled to the expansion bus.

6. A switch matrix module as defined in claim 5, wherein the plurality of different values and accuracies are selected without incurring additional stub penalties.

7. A switch matrix module as defined in claim 4, wherein the switch matrix module is VXI compliant.

8. A switch matrix module, comprising: a programmable load selection block;a first set of stub breakers coupled to the programmable load selection block;a first switch matrix coupled to the first set of stub breakers;a second set of stub breakers coupled to the first switch matrix;a second switch matrix coupled to the second set of stub breakers; anda controller coupled to the first and second set of stub breakers, the controller stores multiple alternative switch matrix paths in case one switch matrix path is restricted the controller can quickly search for an alternative switch matrix path among the alternative switch matrix paths.

9. A switch matrix module as defined in claim 8, wherein the first and second set of stub breakers are software programmable and each includes at least one three-way switch.

10. A switch matrix module as defined in claim 9, further comprising an expansion bus selection block coupled to the second switch matrix.

11. A switch matrix module as defined in claim 9, wherein the controller uses mutually exclusive sets to represent switch matrix topologies.

12. A switch matrix module as defined in claim 8, wherein the programmable load selection block includes a load set including a pull-up to a predetermined voltage and a pull-down to ground potential.

13. A switch matrix module as defined in claim 12, wherein the load set is individually programmable to one of a plurality of predetermined values and accuracies.

14. A switch matrix module, comprising: a programmable load selection block;a first set of stub breakers coupled to the programmable load selection block;a first switch matrix coupled to the first set of stub breakers;a second set of stub breakers coupled to the first switch matrix;a second switch matrix coupled to the second set of stub breakers;a controller coupled to the first and second set of stub breakers, the controller uses mutually exclusive sets to represent switch matrix topologies;the first and second set of stub breakers are software programmable and each includes at least one three-way switch; andwherein the controller performs a switch path search data structure using a Red-Black tree embedded within a Red-Black tree.

15. A switch matrix module as defined in claim 14, wherein the controller stores multiple alternative switch matrix paths in case one switch matrix path is restricted the controller can quickly search for an alternative switch matrix path among the alternative switch matrix paths.

16. A switch matrix module as defined in claim 14, further comprising a switch driver coupled to the controller and the controller can disable a best path searching routine in order to optimize the speed of the switch driver.

17. A VXI compliant single slot switch matrix module, comprising: a plurality of N×M switch matrices;a set of programmable stub breaker switches which couple the plurality of N×M switch matrices to each other and break-off and isolate any unused portions of the plurality of N×M switch matrices in order to improve performance of the switch matrix module; andwherein the set of programmable stub breaker switches comprise 3-way stub breaker switches that isolate upstream or downstream portions of the plurality of N×M switch matrices.

18. A VXI compliant single slot switch matrix module as defined in claim 17 wherein the N×M switch matrices comprise cross-point switches.

19. A VXI compliant single slot switch matrix module as defined in claim 17, an expansion bus coupled to the plurality of N×M switch matrices.

20. A VXI compliant single slot switch matrix module as defined in claim 19, further comprising a programmable load termination coupled to the expansion bus.

21. A switch matrix module, comprising: a plurality of N×M switch matrices;a set of programmable 3-way stub breaker switches that couple the plurality of N×M switch matrices to each other and break-off and isolate any unused portions of the plurality of N×M switch matrices, the 3-way stub breaker switches isolate any upstream or downstream portions of the plurality of N×M switch matrices; anda controller coupled to the set of programmable 3-way stub breaker switches, the controller stores multiple alternative switch matrix paths in case one switch matrix path is restricted the controller can quickly search for an alternative switch matrix path among the alternative switch matrix paths.